A method for improving processor bus arbitration mechanism

Abstract

The application discloses a method for improving processor bus arbitration mechanism, belonging to the field of memory access control, based on the bus authority control unit including bus arbitration module, data packet buffer module, host gating module, slave and several hosts; the bus arbitration module is used for receiving the authority request signal of each host, and dynamically allocating bus authority according to the received request signal; the data packet buffer module is used for buffering the data packet of each host, and sending the data packet of the corresponding host to the host multiplexing module according to the authority determined by the bus arbitration module; the host multiplexing module receives the data packet of the corresponding host from the data packet buffer module according to the authority determined by the bus arbitration module, and sends the data packet to the slave; the data packet from the slave is received and returned to the corresponding host. The application can realize reasonable dynamic allocation of the authority requested by each host with the same priority, and the authority requested by each host with different priorities is allocated according to the priority.

Description

Technical Field

[0001] This invention relates to the field of memory access control technology, and in particular to a method for improving processor bus arbitration mechanisms. Background Technology

[0002] In current hierarchical storage systems, the AXI bus is commonly used to access DDR (Double-data-rate synchronous Dynamic Random access memory) memory. AXI is a bus protocol and a key component of ARM's AMBA (Advanced Microcontroller Bus Architecture). It is an on-chip bus designed for high performance, high bandwidth, and low latency, meeting the needs of ultra-high performance and complex SoC (System-on-Chip) designs.

[0003] To save space and cost, AXI buses typically employ a multi-master, multi-slave topology. However, multiple hosts involve permission arbitration issues. If permissions are not allocated reasonably among multiple hosts with the same or different priorities, it can easily lead to congestion on certain hosts and reduced system transmission efficiency. Therefore, ensuring the reasonable and dynamic allocation of permissions requested by each host is a crucial component in overcoming SoC performance bottlenecks. Summary of the Invention

[0004] The purpose of this invention is to provide a method for improving the processor bus arbitration mechanism to solve the problem of dynamically allocating bus privileges to hosts with the same priority.

[0005] To address the aforementioned technical problems, this invention provides a method for improving the processor bus arbitration mechanism, based on a bus access control unit comprising a bus arbitration module, a data packet buffer module, a host selection module, a slave device, and several hosts;

[0006] The input of the bus arbitration module is connected to the output of each host, and the output is simultaneously connected to the input of the data packet buffer module and the input of the host gating module. The bus arbitration module is used to receive permission request signals from each host and dynamically allocate bus permissions based on the received request signals.

[0007] The input of the data packet buffer module is connected to the output of each host and the output of the bus arbitration module, and the output is connected to the input of the host gating module. The data packet buffer module is used to buffer the data packets of each host and send the corresponding host's data packets to the host multiplexing module according to the permissions determined by the bus arbitration module.

[0008] The output of the master gating module is interconnected with the slave device, and the output of the master gating module is connected to the input of each master device. The master multiplexing module receives data packets from the corresponding master device of the data packet buffer module according to the permissions determined by the bus arbitration module, and sends them to the slave device; it receives data packets from the slave device and returns them to the corresponding master device.

[0009] In one implementation, the bus arbitration module mediates requests from multiple hosts and controls the system according to a priority state machine based on the current owner's status.

[0010] In one implementation, the bus arbitration module uses a sequential polling mechanism to mediate bus usage right requests, allocating usage rights according to the order of requests and treating hosts of the same priority equally.

[0011] In one implementation, when the bus arbitration module dynamically allocates bus permissions, the bus permission allocation order changes in a circular pattern whenever the bus permissions change, and all hosts with the same priority will equally obtain bus ownership.

[0012] In one implementation, the bus arbitration module supports two or more levels of cascading. First, permissions are allocated to high-priority hosts. After the high-priority hosts release their bus permissions, permissions are then allocated to the next lower priority hosts.

[0013] In one implementation, the plurality of hosts are host 0, host 1, and host 2, and each host has the same priority.

[0014] In one implementation, the bus arbitration module has three transition states: "Host 0 has bus control", "Host 1 has bus control", and "Host 2 has bus control". When Host 0 has bus access rights, the priority order of bus requests is Host 0 > Host 1 > Host 2. When Host 1 has bus access rights, the priority order is Host 1 > Host 2 > Host 0. When Host 2 has bus access rights, the priority order is Host 2 > Host 0 > Host 1.

[0015] The present invention provides a method for improving the processor bus arbitration mechanism, which has the following beneficial effects:

[0016] (1) It can achieve reasonable dynamic allocation of request permissions for hosts with the same priority;

[0017] (2) Permission requests from different hosts are allocated according to priority. Attached Figure Description

[0018] Figure 1A structural block diagram of the bus privilege control unit on which the method for improving the processor bus arbitration mechanism provided by the present invention is based;

[0019] Figure 2 The present invention provides a method for improving the processor bus arbitration mechanism, which includes a bus permission status transition diagram of the bus arbitration module. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for improving the processor bus arbitration mechanism proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0021] To better achieve dynamic allocation of AXI bus permissions, this invention provides a method for improving the processor bus arbitration mechanism, which can reasonably and dynamically allocate bus permissions and reduce hardware overhead.

[0022] The structural block diagram of the present invention is as follows: Figure 1 As shown, it includes 3 hosts, a bus arbitration module 104, a data packet buffer module 105, and a host gating module 106. The 3 hosts are host 0 101, host 102, and host 2 103, and these three hosts have the same priority.

[0023] The bus arbitration module 104 is used to mediate bus usage rights. The bus arbitration module 104 is connected to the host 0 101, the host 1 102 and the host 2 103 respectively, mediates the requests issued by these three hosts, receives and responds to the host's permission requests, and assigns usage rights to the appropriate host.

[0024] The bus arbitration module 104 controls the bus according to the current owner's status using a priority state machine. For mediation of bus usage right requests, it uses a sequential polling mechanism to allocate usage rights according to the order of requests and treats hosts of the same priority equally.

[0025] The jump state of the bus arbitration module 104 is as follows: Figure 2 As shown, there are three states: "Host 0 has bus control", "Host 1 has bus control", and "Host 2 has bus control". When Host 0 101 has bus access, the priority order for bus requests is "Host 0 > Host 1 > Host 2". If Host 0 101 requests to continue using the bus, it will be granted permission.

[0026] When host 0 releases the bus, and host 1 requests the bus, the right to use the bus will be granted to host 102 regardless of whether host 2 requests it. If host 0 releases the bus, host 102 does not request to use the bus, but host 2 requests to use the bus, host 103 will obtain the right to use the bus. If none of the hosts request to use the bus, the current state will remain unchanged.

[0027] Similarly, when host 102 holds the right to use the bus, the priority order is "host 1 > host 2 > host 0"; when host 2 103 holds the right to use the bus, the priority order is "host 2 > host 0 > host 1". Since the priority of bus permissions changes in a circular pattern whenever bus permissions change, all hosts with the same priority will equally acquire ownership of the bus.

[0028] All three hosts and the bus arbitration module 104 are connected to the data packet buffer module 105. The data packet buffer module 105 is used to cache data from each host and send data packets of the corresponding host to the host multiplexing module 106 according to the permissions determined by the bus arbitration module 104.

[0029] The host multiplexing module 106 receives data packets from the corresponding host of the data packet buffer module 105 and sends them to the slave device according to the permissions determined by the bus arbitration module 104; it also receives data packets from the slave device and returns them to the corresponding host.

[0030] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method of improving a processor bus arbitration mechanism, comprising: The bus arbitration module, the data packet buffer module, the host gating module, the slave and the bus authority control unit comprising a plurality of hosts; The input end of the bus arbitration module is connected with the output end of each host, and the output end is connected with the input end of the data packet buffer module and the input end of the host gating module; the bus arbitration module is used for receiving the authority request signals of each host, and dynamically allocating bus authority according to the received request signals; The input end of the data packet buffer module is connected with the output end of each host and the output end of the bus arbitration module, and the output end is connected with the input end of the host gating module; the data packet buffer module is used for buffering the data packets of each host, and sending the data packets of the corresponding host to the host gating module according to the authority determined by the bus arbitration module; The output end of the host gating module is interconnected with the slave, and the output end of the host gating module is connected with the input end of each host; the host gating module receives the data packets of the corresponding host from the data packet buffer module according to the authority determined by the bus arbitration module, and sends the data packets to the slave; the host gating module receives the data packets from the slave and returns the data packets to the corresponding host; The plurality of hosts are host 0, host 1 and host 2, and the priority of each host is the same; the bus arbitration module has three jump states, which are "host 0 has bus control authority", "host 1 has bus control authority" and "host 2 has bus control authority"; when host 0 holds the bus use right, the priority order of bus request is host 0>host 1>host 2; when host 1 holds the bus use right, the priority order is host 1>host 2>host 0; when host 2 holds the bus use right, the priority order is host 2>host 0>host 1.

2. The method for improving processor bus arbitration mechanism as recited in claim 1, wherein, The bus arbitration module mediates the requests sent by the plurality of hosts, and controls according to the state of the current owner in a priority state machine mode.

3. The method for improving processor bus arbitration mechanism as recited in claim 2, wherein, The bus arbitration module uses a sequential polling mechanism for mediation of bus use right requests, and allocates use rights according to the request sequence, and treats hosts with the same priority equally.

4. The method for improving processor bus arbitration mechanism as recited in claim 3, wherein, When the bus arbitration module dynamically allocates bus authority, the bus authority allocation sequence changes in a ring shape every time the bus authority changes, and all hosts with the same priority equally obtain bus ownership.

5. The method for improving processor bus arbitration mechanism as recited in claim 4, wherein, The bus arbitration module supports two levels or more cascades, first allocates authority to high-priority hosts, and then allocates authority to low-priority hosts after the high-priority hosts release the bus authority.

Images