Leak detection for three-dimensional NAND memory

Abstract

The present disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first coupled capacitor and a second coupled capacitor. First terminals of the first and second coupled capacitors are connected to a first word line and a second word line, respectively. The first terminals of the first and second coupled capacitors are also connected to a first voltage supply and a second voltage supply, respectively. The circuit further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupled capacitor and a second input of the comparator is connected to a second terminal of the second coupled capacitor. The comparator is configured to send an alarm signal when a differential voltage between the first and second inputs of the comparator is greater than a hysteresis level of the comparator.

Description

[0001] This disclosure is a divisional application of Chinese patent application No. CN202180002122.2, filed on June 9, 2021, entitled "Leakage Detection for Three-Dimensional NAND Memory". Technical Field

[0002] This disclosure relates generally to the field of semiconductor technology, and more specifically to methods and circuits for detecting word line leakage in three-dimensional NAND flash memory. Background Technology

[0003] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to fabrication limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0004] In 3D NAND flash memory, many layers of memory cells can be vertically stacked, significantly increasing the storage density per unit area. Vertically stacked memory cells form memory strings, where the channels of the memory cells in each string are connected. Each memory cell can be addressed via word lines and bit lines. In pursuing multidimensional scaling for high storage density, the distance between word lines decreases. However, different voltages can be applied to word lines during read and program operations. Voltage differences between adjacent word lines can lead to leakage, thus affecting the performance and reliability of 3D NAND memory. Therefore, there is a need to detect leakage between word lines in 3D NAND memory. Summary of the Invention

[0005] This disclosure describes embodiments of methods and circuits for detecting word line leakage in a three-dimensional (3D) memory device.

[0006] A first aspect of this disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuit further includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is also connected to a second voltage supply via a fourth switch. The circuit further includes a comparator, wherein a first input terminal of the comparator is connected to a second terminal of the first coupling capacitor, and a second input terminal of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send a signal indicating the existence of leakage between the first word line and the second word line when the differential voltage between the first and second input terminals of the comparator is greater than the hysteresis level of the comparator.

[0007] In some embodiments, the hysteresis level of the comparator is defined by the difference between the first reference voltage and the second reference voltage of the comparator.

[0008] In some embodiments, the comparator is a hysteresis comparator.

[0009] In some embodiments, the circuit further includes a resistive voltage divider, wherein a first terminal of the resistive voltage divider is connected to a second terminal of the first coupling capacitor, and a second terminal of the resistive voltage divider is connected to a second terminal of the second coupling capacitor.

[0010] In some embodiments, the resistive voltage divider includes a first bias resistor connected in series with a second bias resistor.

[0011] In some embodiments, the resistive voltage divider is configured to provide a common-mode reference voltage for the comparator at the connection between the first bias resistor and the second bias resistor.

[0012] In some embodiments, the first reference voltage of the comparator is the sum of the common-mode reference voltage and half of the hysteresis level.

[0013] In some embodiments, the second reference voltage of the comparator is the difference between the common-mode reference voltage and half of the hysteresis level.

[0014] In some embodiments, the first bias resistor and the second bias resistor can be adjusted to a resistance value such that the differential voltage is approximately zero during the pre-charging phase, wherein the second switch and the fourth switch are turned on to charge the first coupling capacitor and the second coupling capacitor.

[0015] In some embodiments, the memory device is a three-dimensional (3D) NAND flash memory.

[0016] A second aspect of this disclosure provides a three-dimensional (3D) memory device. The 3D memory device includes: a plurality of memory cells connected to word lines and bit lines for addressing each of the plurality of memory cells, wherein the plurality of memory cells are vertically stacked; and circuitry for detecting leakage between word lines. The circuitry includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuitry further includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is also connected to a second voltage supply via a fourth switch. The circuitry further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor, and a second input of the comparator is connected to a second terminal of the second coupling capacitor, wherein the comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage between the first input and the second input of the comparator is greater than a hysteresis level of the comparator.

[0017] A third aspect of this disclosure provides a storage system. The storage system includes a memory controller and a three-dimensional (3D) memory device. The 3D memory device includes a plurality of memory cells connected to word lines and bit lines configured to address each of the plurality of memory cells, wherein the plurality of memory cells are vertically stacked. The storage system further includes circuitry for detecting leakage between word lines. The circuitry includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuitry also includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is connected to a second voltage supply via a fourth switch. The circuitry also includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor, and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage between the first input and the second input of the comparator is greater than the hysteresis level of the comparator.

[0018] A fourth aspect of this disclosure provides a method for detecting leakage between word lines in a memory device. The method includes pre-charging a detection circuit and detecting leakage between a first word line and a second word line. Pre-charging the detection circuit includes connecting a first terminal of a first coupling capacitor in the detection circuit to a first voltage supply terminal; and connecting a first terminal of a second coupling capacitor in the detection circuit to a second voltage supply terminal. Detecting leakage between the first word line and the second word line includes connecting the first terminal of the first coupling capacitor to the first word line; and connecting the first terminal of the second coupling capacitor to the second word line. Detecting leakage between the first word line and the second word line further includes comparing a differential voltage at a first input terminal and a second input terminal of a comparator with a hysteresis level of the comparator, wherein the first input terminal of the comparator is connected to a second terminal of the first coupling capacitor; and the second input terminal of the comparator is connected to a second terminal of the second coupling capacitor.

[0019] In some embodiments, the method further includes sending a signal indicating leakage between the first word line and the second word line when the differential voltage is greater than the hysteresis level of the comparator.

[0020] In some embodiments, precharging the detection circuit further includes: disconnecting the first terminal of the first coupling capacitor from the first word line; and disconnecting the first terminal of the second coupling capacitor from the second word line.

[0021] In some embodiments, detecting leakage between the first word line and the second word line further includes: disconnecting the first terminal of the first coupling capacitor from the first voltage supply terminal; and disconnecting the first terminal of the second coupling capacitor from the second voltage supply terminal.

[0022] In some embodiments, the method further includes: setting the common-mode reference voltage of the comparator using a resistive voltage divider, wherein a first terminal of the resistive voltage divider is connected to a first input terminal of the comparator; a second terminal of the resistive voltage divider is connected to a second input terminal of the comparator; and the resistive voltage divider includes a first bias resistor connected in series with a second bias resistor.

[0023] In some embodiments, the method further includes: setting a first reference voltage and a second reference voltage for the comparator, wherein the first reference voltage is the sum of the common-mode reference voltage and half of the hysteresis level; and the second reference voltage is the difference between the common-mode reference voltage and half of the hysteresis level.

[0024] In some embodiments, the method further includes adjusting the first bias resistor and / or the second bias resistor to a resistance value such that the differential voltage is approximately zero during a pre-charging phase, wherein the second switch and the fourth switch are turned on during the pre-charging phase to charge the first coupling capacitor and the second coupling capacitor.

[0025] In some embodiments, the method further includes sending a signal indicating that there is no leakage between the first word line and the second word line while the differential voltage remains less than the hysteresis level of the comparator.

[0026] In some embodiments, detecting leakage between word lines in the memory device includes detecting leakage between word lines in 3DN NAND flash memory.

[0027] Other aspects of this disclosure will be understood by those skilled in the art based on the description, claims and drawings. Attached Figure Description

[0028] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0029] Figure 1 A schematic top view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure is shown.

[0030] Figure 2 A schematic top view of a region of a 3D memory die according to some embodiments of the present disclosure is shown.

[0031] Figure 3 A perspective view of a portion of an exemplary 3D memory array structure according to some embodiments of the present disclosure is shown.

[0032] Figure 4 A schematic circuit diagram of a 3D memory device according to some embodiments of the present disclosure is shown.

[0033] Figure 5 A schematic circuit diagram of a detection circuit according to some embodiments of the present disclosure is shown.

[0034] Figure 6 A flowchart is shown of a method for detecting leakage between word lines in a memory device according to some embodiments of the present disclosure.

[0035] Figure 7 Timing diagrams of various electrical components of a detection circuit according to some embodiments of the present disclosure are shown.

[0036] Figure 8 and Figures 9A-9B A storage system having one or more memory chips is shown according to some embodiments of the present disclosure.

[0037] Figure 10 A schematic diagram of a memory die according to some embodiments of the present disclosure is shown.

[0038] The features and advantages of the invention will become more apparent from the detailed description set forth below, taken in conjunction with the accompanying drawings, in which corresponding elements are consistently indicated by similar reference numerals. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements. The leftmost reference numeral in the corresponding drawing indicates the drawing in which the element first appears.

[0039] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0040] Although specific configurations and arrangements have been discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a wide variety of other applications.

[0041] It should be noted that the use of terms such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily needs to include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the scope of knowledge of those skilled in the art.

[0042] Generally, terms should be understood at least partly by their use in context. For example, the word "one or more" in a text can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "a," "one," or "the" can be understood to convey either singular or plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for other factors that are not necessarily explicitly stated, again at least partly depending on the context.

[0043] It should be understood that the meanings of "on," "above," and "on top of" in this disclosure should be interpreted in the broadest sense. Thus, "on" not only means being directly on something, but also includes the meaning of having an intermediate feature or layer while being on something. Furthermore, "above" or "on top of" not only means being "above" or "on top of" something, but can also include the meaning of being "above" or "on top of" something without any intermediate feature or layer (i.e., being directly on something).

[0044] In addition, for ease of explanation, spatial relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatial relative terms are intended to encompass different orientations of the apparatus in use or process steps other than those shown in the figures. The apparatus may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0045] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, semiconductor devices are formed on the top side of the substrate unless otherwise specified. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entirety of a lower or upper overlay structure, or may have a smaller extent than the lower or upper overlay structure. Furthermore, a layer may be a region comprising a homogeneous or non-homogeneous continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any set of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (forming contacts, interconnects, and / or vertical interconnect channels (VIAs) therein) and one or more dielectric layers.

[0047] In this disclosure, for ease of description, the term "level" is used to refer to elements that have substantially the same height along the vertical direction. For example, a word line and the lower gate dielectric layer can be referred to as a "level", a word line and the lower insulating layer together can be referred to as a "level", word lines that have substantially the same height can be referred to as a "word line level", and so on.

[0048] As used herein, the term "nominal / nominally" refers to an expected or target value, along with a range of values ​​higher and / or lower than the expected value, for a feature or parameter of a component or process step set during the design phase of a product or process. This range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates that the value of a given quantity may vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0049] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is nominally parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a lateral surface that is nominally perpendicular to the substrate.

[0050] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” e.g., NAND strings) located on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate.

[0051] Figure 1 A top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure is shown. The 3D memory device 100 (e.g., a 3D NAND flash memory) can be a memory chip (package), a memory die, or any portion thereof, and may include one or more memory planes 101, each of which may include a plurality of memory blocks 103. The same concurrent operations can occur at each memory plane 101. A memory block 103, which may have a size of several megabytes (MB), is the minimum size for performing an erase operation. Figure 1 As shown, an exemplary 3D memory device 100 includes four memory planes 101, and each memory plane 101 includes six memory blocks 103. Each memory block 103 may include a plurality of memory cells, wherein each memory cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be vertically arranged (e.g., by rows and columns, respectively), thereby forming an array of metal lines. Figure 1 In this disclosure, the directions of bit lines and word lines are indicated as "BL" and "WL". The memory block 103 is also referred to as a "memory array" or "array". A memory array is the core area in a memory device that performs storage functions.

[0052] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the memory plane 101. The peripheral region 105 contains a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row decoders, column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0053] It should be pointed out that, Figure 1 The arrangement of memory planes 101 in the 3D memory device 100 shown and the arrangement of memory blocks 103 in each memory plane 101 are for illustrative purposes only and do not limit the scope of this disclosure.

[0054] refer to Figure 2 It illustrates some embodiments according to this disclosure. Figure 1 An enlarged top view of region 108 in the 3D memory device 100. Region 108 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each memory string including a plurality of stacked memory cells. The stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, a plurality of slot structures 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 are capable of dividing a memory block into a plurality of memory fingers 218. At least some of the slot structures 216 may serve as common source contacts (e.g., array common source) for the array of memory strings 212 in the channel structure region 211. A top select gate (TSG) notch 220 can be positioned, for example, at the center of each memory finger 218, thereby dividing the TSG of the memory finger 218 into two portions and thus enabling the memory finger to be divided into two memory stripes 224, wherein memory cells sharing the same word line in the memory stripes 224 form programmable (read / write) memory pages. Erasing operations on the 3D NAND memory can be performed at the memory block level, while read and write operations can be performed at the memory page level. Memory pages can have a size of several kilobytes (KB). In some embodiments, region 108 also includes a dummy memory string 222 for process variation control and / or additional mechanical support during manufacturing.

[0055] Figure 3 A perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure is shown. The memory array structure 300 includes a substrate 330, an insulating film 331 above the substrate 330, a lower select gate (LSG) 332 of one layer above the insulating film 331, and multiple layers of control gates 333 (also referred to as “word lines (WL)”) stacked on top of the LSG 332 to form a film stack 335 consisting of alternating conductive and dielectric layers. Figure 3 For clarity, the dielectric layers adjacent to the control gates of each level are not shown.

[0056] Each level of control gate is separated by slot structures 216-1 and 216-2 that penetrate the film stack 335. The memory array structure 300 also includes a top select gate (TSG) 334 of one level located above the stack of control gates 333. The stack of TSG 334, control gate 333, and LSG 332 is also referred to as a “gate electrode”. The memory array structure 300 also includes memory strings 212 and doped source electrode regions 344 located in the portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel hole 336 extending through an insulating film 331 and a film stack 335 consisting of alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewall of the channel hole 336, a channel layer 338 above the memory film 337, and a core-filling film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. The portion of the channel layer 338 corresponding to the respective control gate may also be referred to as the channel 338 of that memory cell. The memory array structure 300 also includes multiple bit lines (BLs) 341 located above the TSG 334 and connected to the memory strings 212. The memory array structure 300 also includes multiple metal interconnects 343 connected to each gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured with a stepped shape to allow for electrical connections to the gate electrodes of each level.

[0057] exist Figure 3 For illustrative purposes, three levels of control gates 333-1, 333-2, and 333-3 are shown together with one level of TSG 334 and one level of LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be more than three to increase storage capacity. The memory array structure 300 may also include other structures, such as TSG cutouts, common source contacts (i.e., array common source), and dummy memory strings. For simplicity, Figure 3 These structures are not shown in the text.

[0058] Figure 4A schematic circuit diagram of a memory block 103 (also referred to as memory array 103) according to some embodiments of the present disclosure is shown. Memory array 103 includes a plurality of memory strings 212, each memory string 212 having a plurality of memory cells 340. Each memory string 212 also includes at least one field-effect transistor (e.g., MOSFET) controlled by a lower select gate (LSG) 332 and a top select gate (TSG) 334, respectively. These two corresponding transistors are referred to as lower select transistor 332-T and top select transistor 334-T. Memory cells 340 can be controlled by control gates 333, some of which can be electrically connected to the same word line of memory array 103. Thus, for simplicity, the control gates and their corresponding word lines are interchangeable in this disclosure. The drain terminal of the top select transistor 334-T can be connected to bit line 341, and the source terminal of the lower select transistor 332-T can be connected to array common source (ACS) 430. The ACS 430 can be shared by memory strings 212 throughout the entire memory block, and is therefore also known as the common source line.

[0059] In some embodiments, the memory array 103 may be formed based on floating gate technology. In some embodiments, the memory array 103 may be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. It stores data or logical states (“states”, for example, the threshold voltage V of memory cell 340). th It depends on the number of charge carriers trapped in the memory film 337 of the memory cell 340.

[0060] In NAND flash memory, read and write operations (also known as programming operations) can be performed on memory page 432 (including all memory cells 340 sharing the same word line), and erase operations can be performed on memory block 103.

[0061] In the NAND memory, memory cell 340 can be in an erase state ER or a programmable state P1. Initially, memory cell 340 in memory array 103 can be reset to the erase state ER, which is logic "1", by applying a negative voltage difference between control gate 333 and channel 338, thereby removing charge carriers trapped in the storage layer of memory cell 340. For example, this can be achieved by grounding the control gate 333 of memory cell 340 and applying a high positive voltage (erase voltage V) to ACS 430. erase This triggers the negative voltage difference. In the erase state ER (“state ER”), the threshold voltage V of memory cell 340... th It can be reset to the lowest value.

[0062] During programming (i.e., writing), a programming voltage V can be applied to the control gate 333, for example. pgm (For example, a positive voltage pulse between 10V and 20V) and grounding the corresponding bit line 341, thus establishing a positive voltage difference between the control gate 333 and the channel 338. As a result, charge carriers (e.g., electrons) can be injected into the storage layer of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. th Accordingly, memory cell 340 can be programmed to programming state P1 (“state P1”).

[0063] The threshold voltage V of the memory cell can be measured or sensed. th To determine the state of the memory cell (e.g., state ER or state P1). During a read operation, the read voltage V... read It can be applied to the control gate 333 of the memory cell, and the current flowing through the memory cell can be measured at bit line 341. Through voltage V pass It can be applied to an unselected word line to turn on an unselected memory cell.

[0064] NAND flash memory can be configured to operate in single-level cell (SLC) mode. To increase storage capacity, NAND flash memory can also be configured to operate in multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC) mode, or any combination of these modes. In SLC mode, the memory cell stores 1 bit and has two logic states (“states”): state ER and P1. In MLC mode, the memory cell stores 2 bits and has four states: state ER, P1, P2, and P3. In TLC mode, the memory cell stores 3 bits and has eight states: state ER and states P1–P7. In QLC mode, the memory cell stores 4 bits and has 16 states.

[0065] At programming voltage V pgm When applied to selected WL 333-S, selected memory cell 340-S on selected memory string 212-S can be programmed to a logic state (e.g., state P1). To achieve this, the selection line 341-S connected to selected memory string 212-S can be grounded and the top selection transistor 334-T on selected memory string 212-S can be turned on. Through voltage V... pass It can be applied to the unselected WL 333-U to turn on the unselected memory cell 340-U. In some embodiments, through voltage V pass It can operate within a range of 6V to 13V. When passing a voltage V...pass The threshold voltage V higher than that of the unselected memory cell 340-U th When selected, the unselected memory cell 340-U on the selected memory string 212-S can be turned on. Therefore, the channel 338 of the selected memory string 212-S can be connected to ground via the selection line 341-S. At the programming voltage V... pgm When applied to the selected WL 333-S, the large potential difference between the control gate 333 and the channel 338 causes charge carriers (i.e., electrons) to tunnel into the memory film 337. This is achieved by adjusting the programming voltage V. pgm It can adjust the number of charge carriers stored in the memory film 337. And it can correspondingly adjust the threshold voltage V of the selected memory cell 340-S. th Therefore, the selected memory cell 340-S can be programmed to the target state.

[0066] As described above, different voltages can be applied to two adjacent word lines during reading or programming. Therefore, leakage may occur between these two adjacent word lines due to this voltage difference, which can negatively impact the performance and data retention of the 3D memory device. Various techniques have been implemented to detect leakage between two word lines in 3D NAND flash memory. For example, by using a single-ended circuit, the voltage drop on the word line caused by leakage can be directly compared to a reference voltage at a comparator. The comparator can send an indication signal when the leakage between the two word lines exceeds a predetermined value. However, even when the leakage current is zero, common-mode noise exists, which may generate false alarms. Moreover, capacitive coupling or feedthrough from switches can also lead to inaccurate measurement results. This disclosure provides a method and circuit for detecting leakage between two word lines by differential voltage variation. Therefore, more accurate measurements can be performed with fewer circuit elements.

[0067] Figure 5 A circuit 500 for detecting leakage between two word lines is shown according to some embodiments of the present disclosure. In this example, the first word line (WL1) 333-1 and the second word line (WL2) 333-2 can be a pair of... Figure 1-4 The memory cell 340 in the 3DNAND flash memory shown is addressed by any word line 333. The leakage current between WL1 and WL2 can be represented by an analog resistor 548 with resistance R0, where a larger resistance R0 represents a smaller leakage current and a smaller resistance R0 represents a larger leakage current.

[0068] The detection circuit 500 includes a first switch (SW1) 550 and a third switch (SW3) 551 electrically connected to WL1 333-1 and WL2 333-2, respectively. The detection circuit 500 also includes a second switch (SW2) 552 and a fourth switch (SW4) 553 electrically connected to a first voltage supply terminal 554 and a second voltage supply terminal 555, respectively. SW1 550, SW2 552, SW3 551, and SW4 553 may include any electronic switch, such as any suitable diode and transistor, such as a bipolar junction transistor (BJT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), or any combination thereof. In some embodiments, SW1 550, SW2 552, SW3 551, and SW4 553 may also include any suitable electromechanical switch, such as a relay, actuator, toggle switch, push-button switch, etc.

[0069] In some embodiments, the first voltage supply terminal 554 can provide a first power supply voltage (V). HV It is higher than the second power supply voltage (V) provided by the second voltage supply terminal 555. SS For example, V HV It can be 12V and V SS It can be 1.2V. The detection circuit 500 can also include more switches and electronic components between WL1 333-1 and SW1 550, which can be represented as component X-PATH 556-1. Similarly, additional switches and electronic components between WL2 333-2 and SW3 551 can be represented as another component X-PATH 556-2.

[0070] The detection circuit 500 also includes a first coupling capacitor (CC1) 558-1 and a second coupling capacitor (CC2) 558-2. The first terminal 572 of CC1 558-1 can be connected to WL1333-1 via SW1 550, and the first terminal 573 of CC2 558-2 can be connected to WL2 333-2 via SW3 551. The first terminal 572 of CC1 558-1 can also be connected to a first voltage supply terminal 554 via SW2 552, and the first terminal 573 of CC2 558-2 can also be connected to a second voltage supply terminal 555 via SW4 553. The first terminal 572 of CC1 558-1 can have a potential V. a Furthermore, the first terminal 573 of CC2 558-2 can have a potential V. b .

[0071] The detection circuit 500 also includes a comparator 570 having a first input terminal (e.g., a positive input terminal) connected to a second terminal 574 of CC1 558-1 and a second input terminal (e.g., a negative input terminal) connected to a second terminal 575 of CC2 558-2. In some embodiments, the comparator 570 may include one or more functional amplifiers (e.g., differential amplifiers) or circuits designed to compare an input signal with a reference signal. In some embodiments, the comparator 570 may include a window comparator and is also referred to as a "hysteresis comparator". In some embodiments, the comparator 570 may be configured to amplify a first differential voltage between two input signals and compare the first differential voltage with a second differential voltage, wherein the second differential voltage may be set by two reference voltages.

[0072] In some embodiments, the first input terminal of comparator 570 may have a first detection voltage V. detp Furthermore, the second input terminal may have a second detection voltage V. detn The differential voltage ΔV of the detection circuit 500 can be defined as the first detection voltage V. detp With the second detection voltage V detn The voltage difference between them, i.e., ΔV = V detp -V detn In some embodiments, comparator 570 may have a first reference voltage V. refp Second reference voltage V refn Wherein, the first reference voltage V refp It can be greater than the second reference voltage V. refn The hysteresis level V of comparator 570 hys It can be defined as the first reference voltage V refp With the second reference voltage V refn The voltage difference between them, i.e., V hys =V refp -V refn The first reference voltage V of the comparator 570 can be designed. refp Second reference voltage V refn This enables the provision of a predetermined hysteresis level V. hys This is compared with the differential voltage ΔV. In some embodiments, when the differential voltage ΔV = V... detp -V detn Greater than the hysteresis level V hys =V refp -V refn At this time, comparator 570 can send an alarm signal V. leak This indicates a leakage between WL1333-1 and WL2 333-2. In some embodiments, the differential voltage ΔV = V detp -V detnMaintain a value less than the hysteresis level V hys =V refp -V refn At this time, comparator 570 can send a signal indicating that there is no leakage between WL1 333-1 and WL2 333-2.

[0073] The detection circuit 500 may further include a resistive voltage divider 561. The first terminal of the resistive voltage divider 561 can be connected to the second terminal 574 of CC1 558-1 and the first input terminal of comparator 570. The second terminal of the resistive voltage divider 561 can be connected to the second terminal 575 of CC2 558-2 and the second input terminal of comparator 570. The resistive voltage divider 561 may include a second bias resistor R. B The first bias resistor (R) connected in series in 2562-2 B 1) 562-1, where R B 1 562-1 and R B The potential at the connection between 2562-2 provides the common-mode reference voltage V for comparator 570. ref .

[0074] In some embodiments, a capacitive voltage divider 563 can be used to simulate the parasitic capacitance of the detection circuit 500. The first terminal of the capacitive voltage divider 563 is connected to the second terminal 574 of CC1 558-1 and the first input terminal of comparator 570. The second terminal of the capacitive voltage divider 563 can be connected to the second terminal 575 of CC2 558-2 and the second input terminal of comparator 570. The capacitive voltage divider 563 includes a first parasitic capacitance (Cp1) 560-1 connected in series with the second parasitic capacitance (Cp2) 560-2, wherein the potential at the connection between Cp1 560-1 and Cp2 560-2 can be equal to the low supply voltage V. SS In this example, capacitive voltage divider 563 is connected in parallel with resistive voltage divider 561.

[0075] In some embodiments, the first power supply voltage V can be adjusted independently. HV Second power supply voltage V SS The first coupling capacitor CC1 558-1, the second coupling capacitor CC2 558-2, and the first bias resistor R B 1 562-1 and second bias resistor R B 2 562-2, to obtain the common-mode reference voltage V ref .

[0076] By using the differential voltage ΔV = V detp -V detn With hysteresis level V hysThe comparison can filter out changes common to both the first and second inputs of comparator 570 (i.e., common-mode input changes). Detection circuit 500 can be configured to primarily respond to the difference between the first and second inputs of comparator 570 (i.e., differential-mode input changes).

[0077] Figure 6 A method 600 for detecting leakage between word lines in a 3D NAND flash memory is illustrated according to some embodiments of the present disclosure. It should be understood that the steps shown in method 600 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In some embodiments, some steps of method 600 may be omitted or may include other steps not described herein for simplicity. In some embodiments, the steps of method 600 may be performed in a different order and / or may vary.

[0078] Method 600 includes two phases: a pre-charging phase and a detection phase. At step S610, the second switch (SW2) 552 and the fourth switch 553 of the detection circuit 500 can be activated. Figure 5 As shown in the diagram, the pre-charging phase begins. Simultaneously, the first switch (SW1) 550 and the third switch 551 can be turned off. During the pre-charging phase, the first word line WL1 333-1 and the second word line WL2 333-2 are disconnected from other electronic components of the detection circuit 500 (e.g., the first coupling capacitor CC1 558-1 and the second coupling capacitor CC2 558-2, and the comparator 570), thereby enabling independent operation of the first detection voltage V without any leakage between WL1 333-1 and WL2 333-2. detp Second detection voltage V detn initialization.

[0079] Figure 7 A timing diagram of various components of a detection circuit 500 according to some embodiments of the present disclosure is shown. At step S610, SW1 and SW3 (dashed lines) are turned off, and SW2 and SW4 (solid lines) are turned on. As a result, the potential V at the first terminal 572 of CC1 558-1... a It can be maintained at the first power supply voltage V HV And the potential V at the second terminal 573 of CC2 558-2 b It can be maintained at the second power supply voltage V SS During the pre-charge phase, CC1 558-1 and CC2 558-2 can be powered by the first power supply voltage V, respectively. HV Second power supply voltage V SSPre-charging is performed. After a sufficiently long period of time, the detection circuit 500 reaches a steady state, i.e., common mode, in which the first detection voltage V... detp Equal to the second detection voltage V detn Therefore, the differential voltage ΔV is zero.

[0080] In some embodiments, the differential voltage ΔV during the pre-charge phase may have a non-zero value due to common-mode noise (e.g., additional parasitic resistance or capacitance associated with one or more word lines). This can be addressed by adjusting CC1 558-1 and CC2 558-2 and / or R. B 1 562-1 and R B 2562-2 can adjust the differential voltage ΔV to zero. In other words, it can adjust the first coupling capacitor CC1 558-1, the second coupling capacitor CC2 558-2, and the first bias resistor R. B 1 562-1 and second bias resistor R B 2 562-2 to minimize / reduce common-mode noise.

[0081] Re-reference Figure 6 In step S620, SW1 550 and SW3 551 can be turned on and SW2 552 and SW4 553 can be turned off. Detection circuit 500 can be connected to WL1 333-1 and WL2 333-2. Therefore, the detection phase begins. In some embodiments, CC1 558-1, CC2 558-2, Cp1 560-1, and Cp2 560-2 can discharge through the leakage current between WL1 333-1 and WL2 333-2.

[0082] The switching behavior of SW1-SW4 is as follows Figure 7 As shown in the diagram. If there is a leakage between WL1 333-1 and WL2 333-2, then the potential V at the first terminal 572 of CC1 558-1 will be... a The voltage drops, and the potential V at the first terminal 573 of CC2558-2 decreases. b The potential V increases. After a sufficiently long period of time, when CC1 558-1, CC2 558-2, Cp1 560-1, and Cp2 560-2 have been fully discharged, the potential V... a and V b It can be kept at the same voltage.

[0083] At the same time, the first detection voltage V at the first input terminal of comparator 570 detp The voltage can be increased at the beginning of the detection phase and then gradually decreased thereafter. The second detection voltage V at the second input terminal of comparator 570... detnThe voltage can be decreased at the beginning of the detection phase and then gradually increased thereafter. After a sufficiently long period of time, when CC1 558-1, CC2 558-2, Cp1560-1, and Cp2 560-2 have been fully discharged, the first detection voltage V... detp Second detection voltage V detn It can be kept at the same voltage.

[0084] Re-reference Figure 6 In step S630, the first detection voltage V is converted at comparator 570. detp Second detection voltage V detn With the first reference voltage V refp Second reference voltage V refn Compare them. If the differential voltage ΔV (i.e., V) detp -V detn () greater than the hysteresis level V hys (that is, V) refp -V refn Then, comparator 570 sends an alarm signal V at step S640. leak This indicates leakage between WL1 333-1 and WL2 333-2. If the differential voltage ΔV does not exceed the hysteresis level V... hys Then, comparator 570 sends another signal at step S650, indicating that there is no leakage between WL1 333-1 and WL2 333-2.

[0085] like Figure 7 As shown, the change in differential voltage ΔV during the detection phase depends on the resistance R0 of analog resistor 548. Figure 7 In the example, resistor R 0_3 (Dashed line) is the minimum and resistance R is... 0_1 (Dash line) Maximum. In other words, when the leakage between WL1 333-1 and WL2 333-2 is large, the differential voltage ΔV changes significantly. When the differential voltage ΔV exceeds the hysteresis level V... hys ( Figure 7 When the dotted line in the diagram is visible, comparator 570 can be triggered to send an alarm signal V. leak In this example, leakage between WL1333-1 and WL2333-2 can occur through the resistance R of analog resistor 548. 0_2 Or R 0_3 When indicated, comparator 570 can be triggered.

[0086] Therefore, by monitoring the differential voltage ΔV (i.e., V) of the detection circuit 500... detp -V detnThis allows for the detection of leakage current between word lines. Once the differential voltage ΔV exceeds a predetermined value, i.e., the hysteresis level V of comparator 570... hys This will generate an alarm signal V. leak .

[0087] Figure 8 A block diagram of an exemplary system 800 having a storage system 10 according to some embodiments of the present disclosure is shown. System 800 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage devices therein. Storage system 10 (also referred to as a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3…25-n. Each semiconductor memory chip 25 (hereinafter simply referred to as a “memory chip”) may be a NAND chip (i.e., “flash memory”, “NAND flash”, or “NAND”). Storage system 10 may communicate with host computer 15 via memory controller 20, wherein memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3…25-n via one or more memory channels 30-1, 30-2, 30-3…30-n. In some embodiments, each memory chip 25 may be managed by the memory controller 20 via the memory channel 30.

[0088] In some embodiments, the host computer 15 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system-on-a-chip (SoC), such as an application processor (AP). The host computer 15 sends data to be stored in the NAND storage system or storage system 10, or retrieves data by reading from storage system 10. The memory controller 20 may process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chips 25. The memory channel 30 may provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 may select one of the memory chips 25 based on a chip enable signal.

[0089] In some embodiments, Figure 8 Each memory chip 25 may include one or more memory dies 100, wherein each memory die can be coupled with... Figure 1 The 3D memory device 100 shown is similar.

[0090] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices, for example, contained in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 10 can be implemented and packaged into different types of end electronic products. Figure 9A In one example shown, the memory controller 20 and a single memory chip 25 can be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may also include a coupling between the memory card 22 and the host (e.g., Figure 8 The memory card connector 24 of the host computer 15). Figure 9B In another example shown, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 26. The SSD 26 may also include components coupling the SSD 26 to the host (e.g., Figure 8 The SSD connector 28 of the host computer 15).

[0091] Figure 10 A schematic diagram of a memory die 100 according to some embodiments of the present disclosure is shown. The memory die 100 includes one or more memory blocks 103. The peripheral circuitry of the memory die 100 includes a variety of digital, analog, and / or mixed-signal circuitry for supporting the functionality of the memory blocks 103, such as page buffers 50, word line drivers 40, control circuitry 70, voltage generators 65, and input / output buffers 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0092] It should be noted that, Figure 8 , Figure 9A -B and Figure 10 The arrangement of electronic components in the storage system 10 and memory die 100 is shown as an example. The storage system 10 and memory die 100 may have other layouts and may include additional components. For example, the memory die 100 may also include a sense amplifier, a column decoder, etc. The storage system 10 may also include firmware, a data scrambler, etc.

[0093] like Figure 10As shown, memory block 103 is coupled to word line driver 40 via word lines (e.g., WL 333) and / or select lines (e.g., LSG 332 and TSG 334). Memory block 103 is coupled to page buffer 50 via bit lines (e.g., BL 341). Word line driver 40 can select one of the memory blocks 103 on memory die 100 in response to a control signal provided by control circuitry 70. Word line driver 40 can deliver a voltage from voltage generator 65 to the word line according to the control signal. During read and program operations, word line driver 40 can deliver a read voltage V according to a control signal received from control circuitry 70. read and programming voltage V pgm Transmitted to the selected word line, and will be transmitted through voltage V. pass Transmit to the unselected word line.

[0094] During programming operations, page buffer 50 can adjust the disable voltage V based on the I / O data to be programmed. inhibit The unselected bit lines are provided with input, and the selected bit lines are connected to ground. The input / output buffer 55 can transfer I / O data to the page buffer 50 and transfer input addresses or commands to the control circuit 70 or the word line driver 40.

[0095] Control circuitry 70 can control page buffer 50 and word line driver 40 in response to commands transmitted by input / output buffer 55. During programming operations, control circuitry 70 can control word line driver 40 and page buffer 50 to program selected memory cells. During read operations, control circuitry 70 can control word line driver 40 and page buffer 50 to read selected memory cells.

[0096] Voltage generator 65, under the control of control circuit 70, generates voltages to be supplied to word lines and bit lines. The voltages generated by voltage generator 65 include the programming voltage V. pgm Through voltage V pass Prohibited voltage V inhibit wait.

[0097] The detection circuit 500 can be added to peripheral circuitry to detect leakage between word lines. In some embodiments, the detection circuit 500 can be connected to the word line driver 40, the voltage generator 65, and the control circuit 70.

[0098] In summary, this disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuit further includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is also connected to a second voltage supply via a fourth switch. The circuit also includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor, and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send a signal indicating the existence of leakage between the first word line and the second word line when the differential voltage between the first and second inputs of the comparator is greater than the hysteresis level of the comparator.

[0099] This disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes: a plurality of memory cells connected to word lines and bit lines configured to address each of the plurality of memory cells, wherein the plurality of memory cells are vertically stacked; and circuitry for detecting leakage between word lines. The circuitry includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuitry further includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is also connected to a second voltage supply via a fourth switch. The circuitry further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor, and a second input of the comparator is connected to a second terminal of the second coupling capacitor, wherein the comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage between the first and second inputs of the comparator is greater than a hysteresis level of the comparator.

[0100] This disclosure also provides a storage system. The storage system includes a memory controller and a three-dimensional (3D) memory device. The 3D memory device includes a plurality of memory cells connected to word lines and bit lines configured to address each of the plurality of memory cells, wherein the plurality of memory cells are vertically stacked. The storage system also includes circuitry for detecting leakage between word lines. The circuitry includes a first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply via a second switch. The circuitry also includes a second coupling capacitor, wherein a first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is connected to a second voltage supply via a fourth switch. The circuitry also includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor, and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage between the first input and the second input of the comparator is greater than the hysteresis level of the comparator.

[0101] This disclosure also provides a method for detecting leakage between word lines in a memory device. The method includes pre-charging a detection circuit and detecting leakage between a first word line and a second word line. Pre-charging the detection circuit includes connecting a first terminal of a first coupling capacitor in the detection circuit to a first voltage supply terminal; and connecting a first terminal of a second coupling capacitor in the detection circuit to a second voltage supply terminal. Detecting leakage between the first word line and the second word line includes connecting the first terminal of the first coupling capacitor to the first word line; and connecting the first terminal of the second coupling capacitor to the second word line. Detecting leakage between the first word line and the second word line further includes comparing a differential voltage at a first input terminal and a second input terminal of a comparator with a hysteresis level of the comparator, wherein the first input terminal of the comparator is connected to a second terminal of the first coupling capacitor; and the second input terminal of the comparator is connected to a second terminal of the second coupling capacitor.

[0102] The foregoing description of specific embodiments will fully reveal the general essence of this disclosure. Those skilled in the art, without extensive experimentation, can readily modify and / or adjust such specific embodiments for various applications using their knowledge and skills, without departing from the general principles of this disclosure. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and their equivalents. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes; therefore, those skilled in the art should interpret the terminology or terminology of this specification in accordance with the teachings and guidance provided.

[0103] The embodiments of this disclosure have been described above using illustrative examples of implementations of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined, provided that the specified functions and their relationships are performed appropriately.

[0104] The Summary and Abstract sections may set forth one or more exemplary embodiments of this disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0105] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the following claims and their equivalents.

Claims

1. A detection circuit, characterized in that, include: A first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply terminal via a second switch; A second coupling capacitor, wherein the first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is also connected to a second voltage supply terminal via a fourth switch; and A comparator, wherein a first input terminal of the comparator is connected to a second terminal of the first coupling capacitor, and a second input terminal of the comparator is connected to a second terminal of the second coupling capacitor, wherein: The comparator is configured to determine whether there is leakage between the first word line and the second word line based on the differential voltage between the first input terminal and the second input terminal of the comparator.

2. The detection circuit according to claim 1, characterized in that, The comparator is configured to: The differential voltage between the first and second input terminals of the comparator and the hysteresis level of the comparator are used to determine whether there is leakage between the first word line and the second word line.

3. The detection circuit according to claim 2, characterized in that, The comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage is greater than the hysteresis level. When the differential voltage is less than the hysteresis level, a signal indicating that there is no leakage between the first word line and the second word line is sent.

4. The detection circuit according to claim 2, characterized in that, The hysteresis level is defined by the difference between the first reference voltage and the second reference voltage of the comparator.

5. The detection circuit according to claim 1, characterized in that, The comparator includes a hysteresis comparator.

6. The detection circuit according to claim 4, characterized in that, The detection circuit further includes: A resistive voltage divider, wherein a first terminal of the resistive voltage divider is connected to a second terminal of a first coupling capacitor, and a second terminal of the resistive voltage divider is connected to a second terminal of a second coupling capacitor.

7. The detection circuit according to claim 6, characterized in that, The resistive voltage divider includes a first bias resistor and a second bias resistor connected in series.

8. The detection circuit according to claim 7, characterized in that, The resistive voltage divider is configured to provide a common-mode reference voltage for the comparator at the connection between the first bias resistor and the second bias resistor.

9. The detection circuit according to claim 8, characterized in that, The first reference voltage of the comparator is the sum of the common-mode reference voltage and half of the hysteresis level.

10. The detection circuit according to claim 7, characterized in that, The first bias resistor and / or the second bias resistor are adjusted to a certain resistance value so that the differential voltage is equal to zero during the pre-charge phase, wherein the second switch and the fourth switch are turned on to charge the first coupling capacitor and the second coupling capacitor.

11. The detection circuit according to claim 1, characterized in that, The first coupling capacitor and / or the second coupling capacitor are adjusted to a certain capacitance value so that the differential voltage is equal to zero during the pre-charging phase, wherein the second switch and the fourth switch are turned on to charge the first coupling capacitor and the second coupling capacitor.

12. The detection circuit according to claim 6, characterized in that, The detection circuit further includes: A capacitive voltage divider, wherein a first terminal of the capacitive voltage divider is connected to a second terminal of a first coupling capacitor and a first input terminal of a comparator, and a second terminal of the capacitive voltage divider is connected to a second terminal of a second coupling capacitor and a second input terminal of a comparator.

13. The detection circuit according to claim 12, characterized in that, The capacitive voltage divider includes a first capacitor and a second capacitor connected in series.

14. The detection circuit according to claim 13, characterized in that, The voltage at the connection between the first capacitor and the second capacitor is equal to the voltage supplied by the second voltage supply terminal.

15. The detection circuit according to claim 13, characterized in that, Both the first capacitor and the second capacitor include parasitic capacitance.

16. The detection circuit according to claim 12, characterized in that, The capacitive voltage divider is connected in parallel with the resistive voltage divider.

17. The detection circuit according to claim 1, characterized in that, The detection circuit is located in the peripheral circuit of the memory device.

18. A memory device, characterized in that, include: A plurality of memory cells, the plurality of memory cells being connected to word lines and bit lines configured to address each of the plurality of memory cells; as well as The detection circuit includes: A first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply terminal via a second switch; A second coupling capacitor, wherein the first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is connected to a second voltage supply terminal via a fourth switch; and A comparator, wherein a first input terminal of the comparator is connected to a second terminal of the first coupling capacitor, and a second input terminal of the comparator is connected to a second terminal of the second coupling capacitor, wherein: The comparator is configured to determine whether there is leakage between the first word line and the second word line based on the differential voltage between the first input terminal and the second input terminal of the comparator.

19. The memory device according to claim 18, characterized in that, The comparator is configured to: The differential voltage between the first and second input terminals of the comparator and the hysteresis level of the comparator are used to determine whether there is leakage between the first word line and the second word line.

20. The memory device according to claim 19, characterized in that, The comparator is configured to send a signal indicating leakage between the first word line and the second word line when the differential voltage is greater than the hysteresis level. When the differential voltage is less than the hysteresis level, a signal indicating that there is no leakage between the first word line and the second word line is sent.

21. The memory device according to claim 19, characterized in that, The hysteresis level is defined by the difference between the first reference voltage and the second reference voltage of the comparator.

22. The memory device according to claim 18, characterized in that, The comparator includes a hysteresis comparator.

23. The memory device according to claim 21, characterized in that, The detection circuit further includes: A resistive voltage divider, wherein a first terminal of the resistive voltage divider is connected to a second terminal of a first coupling capacitor, and a second terminal of the resistive voltage divider is connected to a second terminal of a second coupling capacitor.

24. The memory device according to claim 23, characterized in that, The resistive voltage divider includes a first bias resistor and a second bias resistor connected in series.

25. The memory device according to claim 24, characterized in that, The resistive voltage divider is configured to provide a common-mode reference voltage for the comparator at the connection between the first bias resistor and the second bias resistor.

26. The memory device according to claim 25, characterized in that, The first reference voltage of the comparator is the sum of the common-mode reference voltage and half of the hysteresis level.

27. The memory device according to claim 23, characterized in that, The detection circuit further includes: A capacitive voltage divider, wherein a first terminal of the capacitive voltage divider is connected to a second terminal of a first coupling capacitor and a first input terminal of a comparator, and a second terminal of the capacitive voltage divider is connected to a second terminal of a second coupling capacitor and a second input terminal of a comparator.

28. The memory device according to claim 27, characterized in that, The capacitive voltage divider includes a first capacitor and a second capacitor connected in series.

29. The memory device according to claim 28, characterized in that, The voltage at the connection between the first capacitor and the second capacitor is equal to the voltage supplied by the second voltage supply terminal.

30. The memory device according to claim 28, characterized in that, Both the first capacitor and the second capacitor include parasitic capacitance.

31. The memory device according to claim 27, characterized in that, The capacitive voltage divider is connected in parallel with the resistive voltage divider.

32. The memory device according to claim 18, characterized in that, The detection circuit is located in the peripheral circuit of the memory device.

33. The memory device according to claim 32, characterized in that, The peripheral circuitry includes a word line driver, and the detection circuitry is connected to the word line driver.

34. A storage system, characterized in that, include: Memory controller; as well as A memory device comprising: A plurality of memory cells, the plurality of memory cells being connected to word lines and bit lines configured to address each of the plurality of memory cells; and The detection circuit includes: A first coupling capacitor, wherein a first terminal of the first coupling capacitor is connected to a first word line via a first switch, and the first terminal of the first coupling capacitor is also connected to a first voltage supply terminal via a second switch; A second coupling capacitor, wherein the first terminal of the second coupling capacitor is connected to a second word line via a third switch, and the first terminal of the second coupling capacitor is connected to a second voltage supply terminal via a fourth switch; and A comparator, wherein a first input terminal of the comparator is connected to a second terminal of the first coupling capacitor, and a second input terminal of the comparator is connected to a second terminal of the second coupling capacitor, wherein: The detection circuit is configured to determine whether there is leakage between the first word line and the second word line based on the differential voltage between the first input terminal and the second input terminal of the comparator.

35. The storage system according to claim 34, characterized in that, The comparator is configured to: The differential voltage between the first and second input terminals of the comparator and the hysteresis level of the comparator are used to determine whether there is leakage between the first word line and the second word line.

36. A detection method, characterized in that, include: Pre-charging the detection circuit includes: Charging the first and second coupling capacitors; and Detecting leakage between the first and second letter lines includes: The first and second coupling capacitors are discharged using the first and second word lines; the first coupling capacitor is connected to the first word line, and the second coupling capacitor is connected to the second word line. The differential voltage between the first and second input terminals of the comparator is used to determine whether there is leakage between the first and second word lines, where: The first input terminal of the comparator is connected to the second terminal of the first coupling capacitor; and the second input terminal of the comparator is connected to the second terminal of the second coupling capacitor.

37. The detection method according to claim 36, characterized in that, Charging the first coupling capacitor and the second coupling capacitor includes: Connect the first terminal of the first coupling capacitor to the first voltage supply terminal; Connect the first terminal of the second coupling capacitor to the second voltage supply terminal; Discharging the first and second coupling capacitors using the first and second word lines includes: Disconnect the first terminal of the first coupling capacitor from the first voltage supply terminal; Disconnect the first terminal of the second coupling capacitor from the second voltage supply terminal.

38. The detection method according to claim 36, characterized in that, Charging the first coupling capacitor and the second coupling capacitor includes: Disconnect the first terminal of the first coupling capacitor from the first word line; Disconnect the first terminal of the second coupling capacitor from the second word line; Discharging the first and second coupling capacitors using the first and second word lines includes: Connect the first terminal of the first coupling capacitor to the first word line; Connect the first terminal of the second coupling capacitor to the second word line.

39. The detection method according to claim 36, characterized in that, Determining whether leakage exists between the first word line and the second word line based on the differential voltage between the first and second input terminals of the comparator includes: The differential voltage between the first and second input terminals of the comparator and the hysteresis level of the comparator are used to determine whether there is leakage between the first word line and the second word line.

40. The detection method according to claim 39, characterized in that, Determining whether leakage exists between the first word line and the second word line based on the differential voltage between the first and second input terminals of the comparator includes: When the differential voltage is greater than the hysteresis level, a signal indicating leakage between the first word line and the second word line is sent. When the differential voltage is less than the hysteresis level, a signal indicating that there is no leakage between the first word line and the second word line is sent.

41. The detection method according to claim 39, characterized in that, Also includes: The common-mode reference voltage of the comparator is set using a resistive voltage divider, wherein: The first terminal of the resistive voltage divider is connected to the first input terminal of the comparator; The second terminal of the resistive voltage divider is connected to the second input terminal of the comparator; and The resistive voltage divider includes a first bias resistor and a second bias resistor connected in series.

42. The detection method according to claim 41, characterized in that, Also includes: A first reference voltage and a second reference voltage are set for the comparator, wherein: The first reference voltage is the sum of the common-mode reference voltage and half of the hysteresis level; and The second reference voltage is the difference between the common-mode reference voltage and half of the hysteresis level.

43. The detection method according to claim 41, characterized in that, Also includes: The first bias resistor and / or the second bias resistor are adjusted to a certain resistance value so that the differential voltage is equal to zero during the pre-charge phase.

44. The detection method according to claim 36, characterized in that, Also includes: The first coupling capacitor and / or the second coupling capacitor are adjusted to a certain capacitance value so that the differential voltage is equal to zero during the pre-charge phase.

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