Method for manufacturing bipolar transistor and bipolar transistor

Abstract

The present invention provides a method for preparing a bipolar transistor and a bipolar transistor. The preparation method comprises: preparing a first oxide layer and a protective layer on the upper surface of an obtained substrate, and preparing a voltage divider ring at a corresponding position in the substrate through a preset window obtained by etching the protective layer; performing high-temperature annealing on the substrate after preparing the voltage divider ring, and preparing a second oxide layer at the position of the preset window, and removing the protective layer; determining a base region, an emitter region, and a boron-rich region, and performing corresponding ion implantation on the base region, the emitter region, and the boron-rich region; then preparing a first layer of metal leads and a second layer of metal leads, and preparing an interconnection lead layer between the two layers of metal leads; finally, preparing a first metal layer on the lower surface of the substrate and sintering, to obtain a bipolar transistor. The present invention effectively avoids the problem that the photolithography process cannot accurately limit the distribution of the base region according to the designed size when performing base region doping, and also effectively reduces the base region resistance and improves device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor preparation, and particularly relates to a preparation method of a bipolar transistor and the bipolar transistor. BACKGROUND

[0002] The bipolar transistor is an electronic component in which both electrons and holes participate in conduction, and has two basic types of NPN and PNP. In the prior art, during preparation of the bipolar transistor, the base region doping usually adopts a standard photolithography and implantation doping mode. However, the multiple photolithography processes greatly increase the manufacturing cost of the transistor, and since the photolithography process cannot accurately limit the base region to be distributed according to the designed size, the device may have defects, thereby affecting the performance of the device. SUMMARY

[0003] Embodiments of the present application provide a preparation method of a bipolar transistor and the bipolar transistor, to solve the problem in the prior art that the photolithography process cannot accurately limit the base region to be distributed according to the designed size during base region doping, so that the transistor has defects.

[0004] In a first aspect, embodiments of the present application provide a preparation method of a bipolar transistor, comprising:

[0005] A substrate is obtained, a first oxide layer and a protective layer are prepared in sequence on the upper surface of the substrate, and a first preset number of pressure distribution rings are prepared at the corresponding positions in the substrate through a pre-set window obtained after etching the protective layer;

[0006] High-temperature annealing and oxidation are performed on the substrate after the pressure distribution rings are prepared, to prepare a second oxide layer at the positions of the pre-set window, and the protective layer after etching is removed, to obtain a first sample;

[0007] Photolithography is performed on the upper surface of the first sample through a corresponding photomask to determine a base region, an emitter region and a boron-rich region, and corresponding ion implantation is performed on the base region, the emitter region and the boron-rich region respectively, to obtain a second sample;

[0008] A first dielectric layer is prepared on the upper surface of the second sample, a first layer of metal lead window is prepared on the first dielectric layer, and a first layer of metal lead is prepared at the first layer of metal lead window, to obtain a third sample; wherein the first layer of metal lead window corresponds to the positions of the emitter region and the boron-rich region;

[0009] A second medium layer is prepared on the upper surface of the third sample, and after a second layer of metal lead window is prepared on the second medium layer, an interconnection lead layer is prepared at the second layer of metal lead window, and a second layer of metal lead is prepared on the interconnection lead layer; the second layer of metal lead window corresponds to the position of the emitter region;

[0010] A first metal layer is prepared on the lower surface of the substrate and sintered to obtain a bipolar transistor.

[0011] In a possible implementation, the interconnection lead layer is a nickel-chromium alloy layer.

[0012] In a possible implementation, the first preset number of voltage dividing rings prepared at the corresponding positions in the substrate through the preset window obtained after etching the protective layer comprises:

[0013] A first photoresist is coated on the protective layer, and the first photoresist is exposed, developed and formed into a voltage dividing ring exposure pattern with a voltage dividing ring photo mask as a mask;

[0014] The first photoresist remaining on the voltage dividing ring exposure pattern is used as a mask to etch the protective layer to obtain the first preset number of preset windows;

[0015] For each of the preset windows, first ion implantation is performed in the substrate at the preset window to obtain the voltage dividing ring.

[0016] For each of the first preset number of voltage dividing rings, the implantation energy and dose of the first ion are different.

[0017] In a possible implementation, the base region is determined, and corresponding ion implantation is performed on the base region, comprising:

[0018] A second photoresist is coated on the upper surface of the first sample, and the second photoresist is exposed, developed and formed into a base region exposure pattern with a base region photo mask as a mask;

[0019] The second photoresist remaining on the base region exposure pattern is used as a mask to perform first ion implantation on the base region for a preset number of times.

[0020] In a possible implementation, the emitter region is determined, and corresponding ion implantation is performed on the emitter region, comprising:

[0021] A third photoresist is coated on the upper surface of the first sample, and the third photoresist is exposed, developed and formed into an emitter region exposure pattern with an emitter region photo mask as a mask;

[0022] Exposing the third photoresist remaining on the emission region pattern as a mask, the emission region is subjected to a second ion implantation.

[0023] In a possible implementation, the determining the boron concentration region and performing corresponding ion implantation on the boron concentration region comprises:

[0024] Coating a fourth photoresist on the upper surface of the first sample, exposing and developing the fourth photoresist to form a boron concentration region exposure pattern with the boron concentration region photoetching plate as a mask;

[0025] Exposing the fourth photoresist remaining on the boron concentration region exposure pattern as a mask, the boron concentration region is subjected to a first ion implantation.

[0026] In a possible implementation, after the first layer metal lead window is prepared on the first dielectric layer, a first layer metal lead is prepared at the first layer metal lead window to obtain a third sample comprises:

[0027] Coating a fifth photoresist on the upper surface of the first dielectric layer, exposing and developing the fifth photoresist to form a first layer metal lead window exposure pattern with the first layer metal lead window photoetching plate as a mask;

[0028] Exposing the fifth photoresist remaining on the first layer metal lead window exposure pattern as a mask, etching the first dielectric layer and the first oxide layer to obtain a second preset number of the first layer metal lead window;

[0029] Preparation of a seed layer at the first layer metal lead window and on the upper surface of the remaining first dielectric layer, coating a sixth photoresist on the upper surface of the seed layer, exposing and developing the sixth photoresist to obtain a first layer metal lead exposure pattern with the first layer metal lead photoetching plate as a mask;

[0030] Exposing the sixth photoresist remaining on the first layer metal lead exposure pattern as a mask, preparing a first layer metal lead at each of the metal lead windows to obtain the third sample.

[0031] In a possible implementation, after the second layer metal lead window is prepared on the second dielectric layer, an interconnection lead layer is prepared at the second layer metal lead window, and a second layer metal lead is prepared on the interconnection lead layer comprises:

[0032] Coating a seventh photoresist on the upper surface of the second dielectric layer, exposing and developing the seventh photoresist to form a second layer metal lead window exposure pattern with the second layer metal lead window photoetching plate as a mask;

[0033] Exposing the seventh photoresist remaining on the second layer metal lead window pattern as a mask, etching the second dielectric layer to obtain a third preset number of second layer metal lead windows;

[0034] Preparing an interconnection lead layer at the second layer metal lead window and the upper surface of the remaining second dielectric layer;

[0035] Coating an eighth photoresist on the upper surface of the interconnection lead layer, and exposing and developing the eighth photoresist to obtain a second layer metal lead exposure pattern using the second layer metal lead photoetching plate as a mask;

[0036] Preparing a second layer metal lead on the upper surface of the interconnection lead layer using the eighth photoresist remaining on the second layer metal lead exposure pattern as a mask, and removing the interconnection lead layer not covered by the second layer metal lead.

[0037] In a possible implementation, the preparing a first metal layer on the lower surface of the substrate and sintering to obtain a bipolar transistor comprises:

[0038] Preparing a first metal layer on the lower surface of the substrate;

[0039] After injecting arsenic elements between the lower surface of the substrate and the first metal layer, sintering to obtain the bipolar transistor.

[0040] In a second aspect, an embodiment of the present application provides a bipolar transistor, comprising:

[0041] A first metal layer;

[0042] A substrate arranged on the first metal layer; and the substrate is arranged with a voltage division ring, a base region, an emission region and a boron concentration region;

[0043] A first oxide layer arranged on the upper surface of the substrate; a second oxide layer arranged on the first oxide layer and corresponding to the voltage division ring in the substrate; and a first dielectric layer arranged on the first oxide layer and the second oxide layer;

[0044] A first layer metal lead arranged at a first layer metal lead window in the first oxide layer and the first dielectric layer; wherein the first layer metal lead window corresponds to the position of the emission region and the boron concentration region;

[0045] A second dielectric layer arranged on the upper surface of the first layer metal lead and the upper surface of the first dielectric layer;

[0046] An interconnection lead layer arranged at a second layer metal lead window in the second dielectric layer; wherein the second layer metal lead window corresponds to the position of the emission region;

[0047] a second layer of metal leads disposed on an upper surface of the interconnection lead layer.

[0048] The embodiment of the present application provides a preparation method of a bipolar transistor and the bipolar transistor. The preparation method comprises the following steps: obtaining a substrate; preparing a first oxidation layer and a protection layer on an upper surface of the substrate in sequence; and preparing a first preset number of voltage division rings in a corresponding position in the substrate through a preset window obtained after etching the protection layer. The preparation method can effectively reduce the surface electric field intensity of the bipolar transistor, and then improve the breakdown voltage of the bipolar transistor. Then, high-temperature annealing is performed on the substrate after the voltage division rings are prepared, so that the impurity elements in each voltage division ring can be fully doped and activated. In addition, the substrate is oxidized at the same time of the high-temperature annealing, so as to prepare a second oxidation layer at the position of the preset window. In this way, when ion implantation is performed on the base region subsequently, the second oxidation layer at the preset window can block the diffusion of the elements implanted into the base region, so that the implantation region of the base region is self-aligned and there is no photolithography deviation, thereby ensuring the good performance of the bipolar transistor. Then, the protection layer after etching is removed to obtain a first sample. Photolithography is performed on the upper surface of the first sample through a corresponding photomask to determine the base region, the emitter region and the boron-rich region, and corresponding ion implantation is performed on the base region, the emitter region and the boron-rich region respectively to obtain a second sample. The base region can be implanted with ions for multiple times based on the self-alignment process. On the one hand, the base resistance can be effectively reduced, and then the performance of the bipolar transistor is improved. On the other hand, the problem that the photolithography process cannot accurately limit the distribution of the base region according to the designed size when the base region is doped is avoided, and the device performance of the bipolar transistor is further improved. Then, an interconnection lead layer is arranged between the two layers of metal leads, so that the current stability can be effectively improved, and then the reliability of the bipolar transistor in operation is improved. Finally, a first metal layer is prepared on a lower surface of the substrate and is sintered to obtain the bipolar transistor. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative labor.

[0050] Figure 1 is a flowchart of the preparation method of the bipolar transistor provided by the embodiment of the present application;

[0051] Figure 2 is a process flowchart of preparing the preset window provided by the embodiment of the present application;

[0052] Figure 3is a structural schematic diagram of a prepared partial pressure ring provided by an embodiment of the present application;

[0053] Figure 4 is a process flow schematic diagram of preparing a first layer partial pressure ring provided by an embodiment of the present application;

[0054] Figure 5 is a structural schematic diagram of a prepared three-layer partial pressure ring provided by an embodiment of the present application;

[0055] Figure 6 is a process flow schematic diagram of removing the protective layer after etching after preparing a second oxide layer provided by an embodiment of the present application;

[0056] Figure 7 is a process flow schematic diagram of ion doping to a base region provided by an embodiment of the present application;

[0057] Figure 8 is a process flow schematic diagram of ion doping to an emission region provided by an embodiment of the present application;

[0058] Figure 9 is a process flow schematic diagram of ion doping to a boron concentration region provided by an embodiment of the present application;

[0059] Figure 10 is a process flow schematic diagram of preparing a first dielectric layer provided by an embodiment of the present application;

[0060] Figure 11 is a process flow schematic diagram of preparing a first layer metal lead window provided by an embodiment of the present application;

[0061] Figure 12 is a process flow schematic diagram of preparing a first layer metal lead provided by an embodiment of the present application;

[0062] Figure 13 is a process flow schematic diagram of preparing a second layer metal lead window provided by an embodiment of the present application;

[0063] Figure 14 is a structural schematic diagram of a prepared second layer metal lead provided by an embodiment of the present application;

[0064] Figure 15 is a structural schematic diagram of a bipolar transistor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0065] In the following, the technical solutions in the embodiments of the present application will be clearly described with reference to the accompanying drawings of the embodiments of the present application, so as to make the personnel in the technical field better understand the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by the personnel in the technical field without creative labor should belong to the protection scope of the present application.

[0066] The terms "include", "comprise" and other any variants thereof in the specification and claims of the present application and the above-described accompanying drawings mean "include but not limited to", and are intended to cover the non-exclusive inclusion, and are not limited to the examples listed in the text. In addition, the terms "first" and "second" and the like are used to distinguish different objects, rather than to describe a specific order.

[0067] The implementation of the present application will be described in detail below with reference to the specific accompanying drawings:

[0068] Figure 1 The flowchart of the preparation method of the bipolar transistor provided by the embodiments of the present application is shown in FIG. 1. Figure 1 The embodiments of the present application provide a preparation method of a bipolar transistor, which comprises:

[0069] Step 101: obtaining a substrate, preparing a first oxide layer and a protective layer on the upper surface of the substrate in sequence, and preparing a first preset number of voltage division rings in the corresponding position in the substrate through a preset window obtained by etching the protective layer.

[0070] In step 101, Figure 2 The process flow diagram for preparing the preset window provided by the embodiments of the present application is shown in FIG. 2. Figure 2 As shown in FIG. 2, a substrate 1 is obtained; for example, the substrate 1 can be a silicon substrate; a first oxide layer 2 is prepared on the upper surface of the substrate 1, and a protective layer 3 is prepared on the upper surface of the first oxide layer 2; for example, a silicon dioxide layer can be deposited on the upper surface of the silicon substrate by using a low pressure chemical vapor deposition method (LPCVD), and then a silicon nitride layer is deposited on the upper surface of the silicon dioxide layer; for example, the thickness of the silicon dioxide layer can be 200 angstroms (1 meter = 10 10 angstroms), and the thickness of the silicon nitride layer can be 3000 angstroms. As shown in FIG. 2, Figure 2As shown, when the first oxide layer 2 is prepared on the upper surface of the substrate 1, oxidation is performed in a low-temperature environment (illustratively, the temperature of the low-temperature environment can be maintained at 600°C-1000°C, for example, 900°C); a large flow of oxygen is introduced to change the temperature zone distribution on the surface of the substrate 1, and trichloroethylene is introduced into the oxidation equipment to fix the movable charges. In this way, the quality of the formed silicon dioxide oxide film can be effectively improved, which is beneficial to improving the working efficiency of the bipolar transistor.

[0071] In a possible implementation, preparing a first preset number of voltage divider rings at corresponding positions in the substrate through the preset windows obtained by etching the protective layer includes:

[0072] A first photoresist is coated on the protective layer, and the first photoresist is exposed and developed using a voltage divider ring photoresist as a mask to form a voltage divider ring exposure pattern.

[0073] The protective layer is etched using the first photoresist remaining on the voltage divider ring exposure pattern as a mask to obtain a first preset number of preset windows.

[0074] For each preset window, a first ion implantation is performed in the substrate at the preset window to obtain a voltage divider ring.

[0075] Wherein, for each of the first preset number of voltage divider rings, the implantation energy and dosage of the first ions are different.

[0076] In this embodiment, Figure 2 As shown, a first photoresist 4 is coated on the upper surface of the protective layer 3. The first photoresist 4 is exposed and developed using the voltage divider ring photoresist as a mask to form a voltage divider ring exposure pattern. The remaining first photoresist 4 on the voltage divider ring exposure pattern is used as a mask to etch the protective layer 3 to obtain a first preset number of preset windows 5. The remaining first photoresist 4 is removed, and the preparation process of the preset windows 5 is completed. Afterwards, Figure 3 A schematic diagram of the structure of the pressure divider ring provided in an embodiment of the present invention is shown in FIG. Figure 3 As shown, for each preset window 5, a first ion implantation is performed in the substrate 1 at the preset window 5 to obtain a first preset number of voltage divider rings 6 (for example, the number of voltage divider rings 6 can be as follows: Figure 3 The three shown in the figure may also be four or other numbers. Relevant technicians can design the voltage divider ring 6 according to the specific performance requirements of the bipolar transistor. For example, the number of voltage divider rings 6 can be determined according to the breakdown voltage of the bipolar transistor, and this application does not limit this.) For example, the protective layer 3 can be a silicon nitride layer, the first ion can be a boron element, and the substrate 1 can be a silicon substrate. In this embodiment, each voltage divider ring 6 can effectively reduce the surface electric field strength of the bipolar transistor, thereby increasing its breakdown voltage to ensure good performance of the bipolar transistor.

[0077] Optionally, for each of the first preset number of voltage divider rings 6, the implantation energy and dose of the first ion are different. For example, the first ion can be boron. Taking the preparation of the first layer of voltage divider rings 61 as an example, the preparation process of the first layer of voltage divider rings 61 is described in detail as follows:

[0078] Figure 4 A schematic diagram of a process flow for preparing a first layer of a voltage divider ring according to an embodiment of the present invention is shown in FIG. Figure 4 As shown, photoresist A is coated on each preset window 5 and the upper surface of the remaining protective layer 3, and the first layer of voltage divider ring photoresist is used as a mask to expose and develop the photoresist A to form a first layer of voltage divider ring exposure pattern. Using the remaining photoresist A on the first layer of voltage divider ring exposure pattern as a mask, boron element is injected into the substrate 1 at the preset window 5. For example, the dose and energy of the injected boron element can be 2E14 / 30KeV, 3E14 / 60KeV or 5E14 / 100KeV, which is not limited in this application. The first layer of voltage divider ring 61 is obtained, and then the remaining photoresist A is removed, thereby completing the preparation of the first layer of voltage divider ring 61. In addition, in the preparation process of the second layer of voltage divider ring and more layers of voltage divider ring, the dose and energy of the injected boron element can be the same or different. The specific dose and energy values ​​can be determined based on the specific process requirements, which is not limited in this application. Taking the preparation of three voltage divider rings as an example, Figure 5 A schematic diagram of the structure of a three-layer voltage divider ring prepared according to an embodiment of the present invention is shown in FIG. Figure 5 As shown, the three voltage divider rings are voltage divider ring 61, voltage divider ring 62, and voltage divider ring 63. The dose and energy of the boron element implanted in each of these three voltage divider rings can be different. In this embodiment, by implanting boron elements at different doses and energies at predetermined windows in different layers of the substrate, voltage divider rings of corresponding layers are obtained. Based on each voltage divider ring, the voltage withstand performance of the bipolar transistor can be effectively improved, thereby effectively ensuring the excellent performance of the bipolar transistor.

[0079] Step 102: The substrate on which the voltage divider ring is prepared is subjected to high-temperature annealing and oxidation to prepare a second oxide layer at the position of the preset window, and the etched protective layer is removed to obtain a first sample.

[0080] In step 102, Figure 6 A schematic diagram of a process flow for removing the etched protective layer after preparing the second oxide layer according to an embodiment of the present invention is provided. Figure 6 As shown, the substrate 1 after the voltage divider ring 6 is prepared is subjected to high temperature annealing to activate the impurity elements in each voltage divider ring 6 (for example, Figure 5As shown, high temperature annealing is performed on the substrate 1 after the preparation of the pressure rings to activate the impurities in the pressure rings 61, 62 and 63, so that the impurity elements in the pressure rings 6 can be fully doped and activated, and the breakdown voltage of the bipolar transistor can be effectively improved based on the pressure rings 6 to ensure excellent performance. In addition, while the high temperature annealing is performed on the substrate 1, a second oxide layer 7 is also prepared at each of the preset windows 5 on the substrate, and then the etched protective layer 3 is removed to obtain a first sample. For example, the second oxide layer can be a silicon dioxide layer, which can be deposited at each of the preset windows 5 by a low pressure chemical vapor deposition method, and the deposition thickness of the silicon dioxide layer can be 4000 angstroms. In addition, a suitable annealing temperature can fully activate the boron elements implanted in the preset windows 5 and dope the corresponding positions in the substrate to form pressure rings 6 of good quality. For example, the temperature of the high temperature annealing in the embodiment can be controlled at 1100-1200℃.

[0081] In the embodiment, high temperature annealing is performed on the substrate after the preparation of the pressure rings, so that the impurity elements in the pressure rings can be fully activated and fully doped at the corresponding positions in the substrate. In addition, the positions at each of the preset windows on the upper surface of the substrate are oxidized to prepare a second oxide layer with the remaining protective layer as a mask. In this way, when ion implantation is subsequently performed on the base region, the second oxide layer at the preset window can block the diffusion of the elements implanted in the base region, so that the implantation region of the base region is self-aligned without photolithography deviation, thereby ensuring the good performance of the bipolar transistor.

[0082] Step 103: photolithography is performed on the upper surface of the first sample by using a corresponding photomask to determine the base region, the emitter region and the boron-rich region, and corresponding ion implantation is performed on the base region, the emitter region and the boron-rich region to obtain a second sample.

[0083] In step 103, the base region, the emitter region and the boron-rich region are respectively determined by using the photomask corresponding to the base region, the emitter region and the boron-rich region to perform photolithography on the base region, the emitter region and the boron-rich region, and then the matching impurity elements are implanted into the base region, the emitter region and the boron-rich region to obtain the second sample. Optionally, when ion implantation is performed on the base region, the base region can be implanted with multiple different doses and energies based on a self-alignment process to reduce the resistance of the base region and improve the performance of the bipolar transistor.

[0084] In a possible implementation, the base region is determined, and corresponding ion implantation is performed on the base region, including:

[0085] A second photoresist is coated on the upper surface of the first sample, and the second photoresist is exposed and developed with the base region photomask as a mask to form a base region exposure pattern.

[0086] The second photoresist remaining on the base area exposure pattern is used as a mask to perform a preset number of first ion implantations on the base area.

[0087] In this embodiment, Figure 7 A schematic diagram of a process flow for ion doping a base region according to an embodiment of the present invention is shown in FIG. Figure 7 As shown, a second photoresist 8 is coated on the upper surface of the first sample, and the second photoresist 8 is exposed and developed using the base photoresist as a mask to form a base exposure pattern, that is, to determine the base position, and then the second photoresist 8 remaining on the base exposure pattern is used as a mask to perform a preset number of first ion implantations on the base region 9 to obtain a base region after multiple first ion implantations, and then the remaining second photoresist 8 on the upper surface of the first sample is removed, thereby completing the first ion implantation process of the base region 9, and then performing high-temperature annealing on the base region 9 after the ion implantation, so that the impurity elements in the base region 9 can be fully activated and fully doped in the corresponding positions in the substrate. Exemplarily, the first ion injected can be boron. In this embodiment, taking the preset number of times as three as an example, the first ion is injected into the base region 9. The first time, 2E14 / 30KeV of boron can be injected into the base region 9, the second time, 3E14 / 60KeV of boron can be injected into the base region 9, and the third time, 5E14 / 100KeV of boron can be injected into the base region 9. In addition, relevant technical personnel can also adjust the dosage and energy of the first ion injection into the base region according to the performance of the designed bipolar transistor, and this application does not limit this. In this embodiment, multiple ion injections are performed on the base region through a self-aligned process. On the one hand, it can effectively reduce the base region resistance and thus improve the performance of the bipolar transistor; on the other hand, it also effectively avoids the problem that the lithography process cannot accurately limit the distribution of the base region according to the designed size when performing base region doping, further improving the device performance of the bipolar transistor.

[0088] In a possible implementation, determining the emission region and performing corresponding ion implantation on the emission region includes:

[0089] A third photoresist is coated on the upper surface of the first sample, and the third photoresist is exposed and developed using the emission region photoresist as a mask to form an emission region exposure pattern.

[0090] The second ion implantation is performed on the emitter region using the third photoresist remaining on the exposure pattern of the emitter region as a mask.

[0091] In this embodiment, Figure 8 A schematic diagram of a process flow for ion doping an emitter region according to an embodiment of the present invention is shown in FIG. Figure 8As shown, the third photoresist 10 is coated on the upper surface of the first sample, the third photoresist 10 is exposed and developed with the emission region photoetching plate as a mask to form an emission region exposure pattern, that is, the position of the emission region is determined, then the second ion is injected into the emission region 11 with the third photoresist 10 remaining on the emission region exposure pattern as a mask to obtain the emission region 11 after the second ion injection, then the third photoresist 10 remaining on the upper surface of the first sample is removed, thus the ion injection process of the emission region 11 is completed, and then the emission region 11 after the ion injection is subjected to high-temperature annealing, so that the impurity elements in the emission region 11 can be fully activated and fully doped in the corresponding position in the substrate. Exemplarily, the injected second ion can be a phosphorus element.

[0092] In a possible implementation, the determining of the boron concentration region and the corresponding ion injection on the boron concentration region include:

[0093] The fourth photoresist is coated on the upper surface of the first sample, and the fourth photoresist is exposed and developed with the boron concentration region photoetching plate as a mask to form a boron concentration region exposure pattern.

[0094] The first ion is injected into the boron concentration region with the fourth photoresist remaining on the boron concentration region exposure pattern as a mask.

[0095] In the embodiment, Figure 9 The process flow diagram for ion doping on the boron concentration region provided by the embodiment of the present application is shown in FIG. 2. Figure 9 As shown, the fourth photoresist 12 is coated on the upper surface of the first sample, the fourth photoresist 12 is exposed and developed with the boron concentration region photoetching plate as a mask to form a boron concentration region exposure pattern, that is, the position of the boron concentration region is determined, then the first ion is injected into the boron concentration region 13 with the fourth photoresist 12 remaining on the boron concentration region exposure pattern as a mask to obtain the boron concentration region 13 after the first ion injection, then the fourth photoresist 12 remaining on the upper surface of the first sample is removed, thus the ion injection process of the boron concentration region 13 is completed, and then the boron concentration region 13 after the ion injection is subjected to high-temperature annealing, so that the impurity elements in the boron concentration region 13 can be fully activated and fully doped in the corresponding position in the substrate. Exemplarily, the injected first ion can be a boron element.

[0096] Step 104: A first dielectric layer is prepared on the upper surface of the second sample, a first layer of metal lead window is prepared on the first dielectric layer, and a first layer of metal lead is prepared at the first layer of metal lead window to obtain a third sample; wherein the first layer of metal lead window corresponds to the positions of the emission region and the boron concentration region.

[0097] In step 104, Figure 10 The process flow diagram for preparing the first dielectric layer provided by the embodiment of the present application is shown in FIG. 3. Figure 10As shown, the first dielectric layer 14 is prepared on the upper surface of the second sample. Exemplarily, the first dielectric layer 14 can be a silicon nitride layer, a silicon dioxide layer, a phosphor-silicon glass layer, a boron-silicon glass layer, a boron-phosphor-silicon glass layer, etc., which are not limited in the present application. Optionally, in order to match the stress between the first dielectric layer 14 and the first oxide layer 2, the second oxide layer 7 and the subsequent preparation material related to the first dielectric layer 14, the first dielectric layer 14 can be a silicon dioxide layer. Exemplarily, a low pressure chemical vapor deposition method can be used to prepare a 5000 angstrom silicon dioxide on the upper surface of the first oxide layer 2 and the second oxide layer 7 to form the first dielectric layer 14. After the first dielectric layer 14 is prepared, a first layer metal lead window is prepared on the upper surface of the first dielectric layer 14 to facilitate the preparation of the first layer metal lead at the first layer metal lead window, and a third sample is obtained. The first layer metal lead window corresponds to the positions of the emitter region and the boron-rich region, so as to facilitate the subsequent extraction of the emitter region and the base region based on the first layer metal lead at the first layer metal lead window.

[0098] In a possible implementation, after the first layer metal lead window is prepared on the first dielectric layer, the first layer metal lead is prepared at the first layer metal lead window to obtain the third sample, which includes:

[0099] The fifth photoresist is coated on the upper surface of the first dielectric layer, and the fifth photoresist is exposed and developed with the first layer metal lead window photomask as a mask to form a first layer metal lead window exposure pattern.

[0100] The first dielectric layer and the first oxide layer are etched with the remaining fifth photoresist on the first layer metal lead window exposure pattern as a mask to obtain a second preset number of first layer metal lead windows.

[0101] A seed layer is prepared on the upper surface of the first layer metal lead window and the remaining first dielectric layer, and a sixth photoresist is coated on the upper surface of the seed layer. The sixth photoresist is exposed and developed with the first layer metal lead photomask as a mask to obtain a first layer metal lead exposure pattern.

[0102] The first layer metal lead is prepared at each metal lead window with the remaining sixth photoresist on the first layer metal lead exposure pattern as a mask to obtain the third sample.

[0103] In the present embodiment, Figure 11 The process flow diagram for preparing the first layer metal lead window provided by the present embodiment is as follows: Figure 11As shown, the fifth photoresist 15 is coated on the upper surface of the first dielectric layer 14; the first layer metal lead window photoresist is used as a mask to expose and develop the fifth photoresist 15, thereby forming a first layer metal lead window exposure pattern; then the fifth photoresist 15 remaining on the first layer metal lead window exposure pattern is used as a mask to etch the first dielectric layer 14 and the first oxide layer 2 (until the upper surface of the substrate 1 is etched), thereby obtaining a second preset number of first layer metal lead windows; then the remaining fifth photoresist 15 is removed, thereby completing the process of preparing a plurality of first layer metal lead windows 16. Specifically, the specific number of first layer metal lead windows can be determined by the specific design of the bipolar transistor. In this embodiment, a plurality of first layer metal lead windows are prepared on the first dielectric layer 14 and the first oxide layer 2, so as to facilitate the subsequent preparation of the first layer metal lead at each first layer metal lead window, thereby leading out the base region and the emitter region, and ensuring the performance of the bipolar transistor.

[0104] In this embodiment, Figure 12 The process flow diagram for preparing the first layer metal lead provided in the embodiment of the present application is as follows: Figure 12 As shown, first, a seed layer 17 is prepared at the first layer metal lead window 16 and on the upper surface of the remaining first dielectric layer 14; the sixth photoresist 18 is coated on the upper surface of the seed layer 17; then the first layer metal lead photoresist is used as a mask to expose and develop the sixth photoresist 18, thereby obtaining a first layer metal lead exposure pattern; then the sixth photoresist 18 remaining on the first layer metal lead exposure pattern is used as a mask to prepare the first layer metal lead 19 at each metal lead window 16; finally, the remaining sixth photoresist 18 is removed, and the seed layer 17 not covered by the first layer metal lead 19 is removed, thereby obtaining a third sample. In this embodiment, the first layer metal lead 19 can be prepared by sputtering and plating, or by sputtering and etching, or by other methods that can prepare the first layer metal lead 19, which is not limited in the present application. By preparing the first layer metal lead 19, the base region and the emitter region can be accurately and safely led out, thereby ensuring the performance of the bipolar transistor.

[0105] Step 105: A second dielectric layer is prepared on the upper surface of the third sample, and after a second layer metal lead window is prepared on the second dielectric layer, an interconnection lead layer is prepared at the second layer metal lead window, and a second layer metal lead is prepared on the interconnection lead layer; the position of the second layer metal lead window corresponds to that of the emitter region.

[0106] In step 105, Figure 13 The process flow diagram for preparing the second layer metal lead window provided in the embodiment of the present application is as follows: Figure 14 The process flow diagram for preparing the second layer metal lead provided in the embodiment of the present application is as follows, please refer toFigure 13 and Figure 14 First, a second dielectric layer 20 is prepared on the upper surface of the third sample, and a second layer of metal lead window 21 is prepared on the second dielectric layer 20; for example, the second dielectric layer 20 can be a silicon nitride layer, a silicon dioxide layer, a phosphor silicon glass layer, a boron silicon glass layer, a boron phosphor silicon glass layer, etc., and the specific function of the second dielectric layer 20 can be to separate the first layer of metal leads and the second layer of metal leads, and the specific material of the second dielectric layer 20 can be determined according to the specific design process of the bipolar transistor, which is not limited in the present application. After the second layer of metal lead window 21 is prepared, an interconnection lead layer 22 is prepared at the second layer of metal lead window 21, and then a second layer of metal lead 23 is prepared on the interconnection lead layer 22; wherein the second layer of metal lead window 21 corresponds to the position of the emitter region 11. In this embodiment, the first layer of metal lead 19 and the second layer of metal lead 23 are interconnected based on the interconnection lead layer 22, which is a metal layer and also serves as an emitter resistance, which can effectively improve the stability of the current in the bipolar transistor, thereby effectively improving the reliability of the device operation.

[0107] In a possible implementation, after the second layer of metal lead window is prepared on the second dielectric layer, the interconnection lead layer is prepared at the second layer of metal lead window, and the second layer of metal lead is prepared on the interconnection lead layer, comprising:

[0108] A seventh photoresist is coated on the upper surface of the second dielectric layer, and the seventh photoresist is exposed and developed with the second layer of metal lead window photoresist as a mask to form a second layer of metal lead window exposure pattern.

[0109] The second dielectric layer is etched with the seventh photoresist remaining on the second layer of metal lead window exposure pattern as a mask to obtain a third preset number of second layer of metal lead windows.

[0110] The interconnection lead layer is prepared on the upper surface of the second layer of metal lead window and the remaining second dielectric layer.

[0111] An eighth photoresist is coated on the upper surface of the interconnection lead layer, and the eighth photoresist is exposed and developed with the second layer of metal lead photoresist as a mask to obtain a second layer of metal lead exposure pattern.

[0112] The second layer of metal lead is prepared on the upper surface of the interconnection lead layer with the eighth photoresist remaining on the second layer of metal lead exposure pattern as a mask, and the interconnection lead layer not covered by the second layer of metal lead is removed.

[0113] In this embodiment, the second dielectric layer 20 is taken as an example of boron phosphor silicon glass to describe the process of preparing the second layer of metal lead. Please refer to Figure 13 and Figure 14First, the seventh photoresist is coated on the upper surface of the second dielectric layer 20, and the seventh photoresist is exposed and developed with the second layer metal lead window mask as a mask to form a second layer metal lead window exposure pattern. The second dielectric layer is etched with the remaining seventh photoresist on the second layer metal lead window exposure pattern as a mask to obtain the second layer metal lead window 21. In this embodiment, the third preset number is three, and the specific number can be determined by the related technical personnel based on the specific design and performance requirements of the bipolar transistor, which is not limited in the present application. Then, the interconnection lead layer 22 is prepared at the second layer metal lead window 21 and the upper surface of the remaining second dielectric layer 20. Specifically, the interconnection lead layer 22 can be prepared by sputtering and plating, or by sputtering and etching, or by other methods that can prepare the interconnection lead layer 22, which is not limited in the present application. Then, when preparing the second layer metal lead 23, the eighth photoresist is usually coated on the upper surface of the interconnection lead layer 22, and the eighth photoresist is exposed and developed with the second layer metal lead mask as a mask to obtain a second layer metal lead exposure pattern. Then, the second layer metal lead is prepared on the upper surface of the interconnection lead layer with the remaining eighth photoresist on the second layer metal lead exposure pattern as a mask. In this embodiment, the second layer metal lead 23 can be prepared by sputtering and plating, or by sputtering and etching, or by other methods that can prepare the second layer metal lead 23, which is not limited in the present application. Finally, after removing the interconnection lead layer 22 not covered by the second layer metal lead 23 and removing the remaining eighth photoresist, the preparation of the second layer metal lead 23 is completed. In this embodiment, the first layer metal lead 19 and the second layer metal lead 23 are interconnected based on the interconnection lead layer 22, the interconnection lead layer 22 is a metal layer, and also serves as an emitter resistance, which can effectively improve the stability of the current in the bipolar transistor, thereby effectively improving the reliability of the device operation.

[0114] In a possible implementation, the interconnection lead layer is a nickel-chromium alloy layer.

[0115] In this embodiment, as shown in Figure 14 , the interconnection lead layer 22 can be a nickel-chromium alloy layer. For high-voltage and high-power bipolar transistors, especially in the case of high voltage and large current, more heat and voltage drop are distributed on the resistance of the device, which may cause the device to have a self-excited reaction or burnout phenomenon. Therefore, in this embodiment, a nickel-chromium alloy layer with a large resistivity is used as an emitter resistance, so that the resistance of the emitter region is large, which can meet the stability of the device in the case of high voltage and large current, so that the bipolar transistor can work stably.

[0116] Step 106: preparing a first metal layer on the lower surface of the substrate and sintering to obtain a bipolar transistor.

[0117] In step 106,Figure 15 A schematic diagram of the structure of a bipolar transistor provided in an embodiment of the present invention is shown in FIG. Figure 15 As shown, a first metal layer 24 is prepared on the lower surface of the substrate 1 and sintered to obtain a bipolar transistor. In this embodiment, the material of the first metal layer 24 can be gold.

[0118] In one possible implementation, preparing a first metal layer on the lower surface of a substrate and sintering the layer to obtain a bipolar transistor includes:

[0119] A first metal layer is formed on the lower surface of the substrate.

[0120] Arsenic is injected between the lower surface of the substrate and the first metal layer and then sintered to obtain a bipolar transistor.

[0121] In this embodiment, Figure 15 As shown, after the first metal layer 24 is prepared on the lower surface of the substrate 1, arsenic is injected between the lower surface of the substrate 1 and the first metal layer 24. The amount of arsenic injected is as much as possible under the conditions allowed by the process (for example, after the arsenic is injected, the following is formed): Figure 15 The arsenic element layer 25 in the substrate 1 is formed, and finally the first metal layer 24 is thickened and the device is sintered at a low temperature to obtain a bipolar transistor. In this embodiment, since high temperature affects the dielectric stress, arsenic is doped between the lower surface of the substrate 1 and the first metal layer 24. On the one hand, the effect of high-temperature sintering on the dielectric stress is reduced. On the other hand, it can effectively reduce the resistance of the device, so that it has better ohmic contact sintering, and the obtained bipolar transistor device has good strength and low resistance. Compared with the process without arsenic doping, the first metal layer 24 doped with arsenic in this application can be sintered at a lower alloy temperature (usually, the sintering temperature is 400°C, while in this embodiment, the same quality device can be obtained by sintering at a lower temperature. For example, the sintering temperature can be 350°C.) to obtain the same quality AuSi alloy. Therefore, the sintering temperature is reduced by doping the gold layer with arsenic in this application. In addition, if the gold layer is too thin, the AuSi alloy layer will be discontinuous, affecting the performance of the device. Therefore, the thickening of the Au layer in this application is to make the AuSi alloy layer obtained during sintering more uniform.

[0122] The embodiment of the present application provides a preparation method of a bipolar transistor, which comprises the following steps: obtaining a substrate, preparing a first oxide layer and a protective layer on the upper surface of the substrate in sequence, and preparing a first preset number of voltage division rings in the corresponding position of the substrate through a preset window obtained after etching the protective layer, so that the surface electric field intensity of the bipolar transistor can be effectively reduced, and the breakdown voltage is improved; then, high-temperature annealing is performed on the substrate after the voltage division rings are prepared, so that the impurity elements in each voltage division ring can be fully doped and activated; in addition, the substrate is oxidized at the same time of high-temperature annealing, so that a second oxide layer is prepared at the position of the preset window, so that when ion implantation is performed on the base region in the subsequent process, the second oxide layer at the preset window can block the diffusion of the elements implanted into the base region, so that the implantation region of the base region is self-aligned and there is no photolithography deviation, thereby ensuring the good performance of the bipolar transistor; then, the protective layer after etching is removed to obtain a first sample; photolithography is performed on the upper surface of the first sample through a corresponding photomask to determine the base region, the emitter region and the boron-rich region, and corresponding ion implantation is performed on the base region, the emitter region and the boron-rich region respectively to obtain a second sample; the base region can be implanted with ions for multiple times based on the self-alignment process, which can effectively reduce the resistance of the base region and improve the performance of the bipolar transistor, and can also effectively avoid the problem that the photolithography process cannot accurately limit the distribution of the base region according to the designed size when the base region is doped, thereby further improving the device performance of the bipolar transistor; then, an interconnection lead layer is arranged between the two metal lead layers, which can effectively improve the current stability and improve the reliability of the bipolar transistor; finally, a first metal layer is prepared on the lower surface of the substrate and is sintered to obtain the bipolar transistor.

[0123] In a second aspect, the embodiment of the present application provides a bipolar transistor, comprising:

[0124] A first metal layer.

[0125] A substrate arranged on the first metal layer; and the substrate is provided with a voltage division ring, a base region, an emitter region and a boron-rich region.

[0126] A first oxide layer arranged on the upper surface of the substrate; a second oxide layer arranged at the corresponding position of the voltage division ring in the substrate on the first oxide layer; and a first dielectric layer arranged on the first oxide layer and the second oxide layer.

[0127] A first layer of metal lead arranged at a first layer of metal lead window in the first oxide layer and the first dielectric layer; wherein the first layer of metal lead window corresponds to the positions of the emitter region and the boron-rich region.

[0128] A second dielectric layer arranged on the upper surface of the first layer of metal lead and the upper surface of the first dielectric layer.

[0129] An interconnection wiring layer is provided at the second metal wiring window in the second dielectric layer; wherein the second metal wiring window corresponds to the position of the emission region.

[0130] A second layer of metal leads is provided on the upper surface of the interconnection lead layer.

[0131] In this example, if Figure 15 As shown, the bipolar transistor includes, from bottom to top: a first metal layer 24 and a substrate 1 arranged on the first metal layer 24; a plurality of voltage divider rings 6, a base region 9, an emitter region 11 and a concentrated boron region 13 are arranged in the substrate 1; in addition, a first oxide layer 2 is arranged on the upper surface of the substrate 1; a second oxide layer is arranged on the first oxide layer 2 at a position corresponding to the voltage divider ring 6 in the substrate 1; and a first dielectric layer 14 is arranged on the first oxide layer 2 and the second oxide layer; a first layer of metal leads 19 are arranged at the first layer of metal lead windows in the first oxide layer 2 and the first dielectric layer 14; wherein the first layer of metal lead windows correspond to the positions of the emitter region 11 and the concentrated boron region 13; a second dielectric layer 20 is arranged on the upper surface of the first layer of metal leads 19 and the upper surface of the first dielectric layer; an interconnection lead layer 22 is arranged at the second layer of metal lead windows in the second dielectric layer 20; wherein the second layer of metal lead windows correspond to the position of the emitter region 11; and a second layer of metal leads 23 are arranged on the upper surface of the interconnection lead layer 22.

[0132] The embodiment of the present application provides a bipolar transistor, by obtaining a substrate, preparing a first oxide layer and a protective layer on the upper surface of the substrate in sequence, and preparing a first preset number of voltage division rings in the corresponding position of the substrate through a preset window obtained after etching the protective layer, the surface electric field intensity of the bipolar transistor can be effectively reduced, and then the breakdown voltage is improved; then the substrate after preparing the voltage division ring is subjected to high temperature annealing to activate the impurity elements, so that the impurity elements in each voltage division ring can be fully doped and activated; in addition, the substrate is oxidized at the same time of high temperature annealing, so as to prepare a second oxide layer at the position of the preset window, in this way, when the base region is subjected to ion implantation subsequently, the second oxide layer at the preset window can block the diffusion of the elements implanted into the base region, so that the implantation region of the base region is self-aligned, without photolithography deviation, thereby ensuring the good performance of the bipolar transistor; then the protective layer after etching is removed to obtain a first sample; the base region, the emitter region and the boron-rich region are determined by photolithography on the upper surface of the first sample through a corresponding photomask, and the base region, the emitter region and the boron-rich region are subjected to corresponding ion implantation respectively to obtain a second sample; the base region can be subjected to multiple ion implantation based on the self-alignment process, on the one hand, the base resistance can be effectively reduced, and the performance of the bipolar transistor is improved, on the other hand, the problem that the photolithography process cannot accurately limit the distribution of the base region according to the designed size when the base region is doped is avoided, and the device performance of the bipolar transistor is further improved; then the interconnection lead layer is arranged between the two metal lead layers, the current stability can be effectively improved, and the reliability of the bipolar transistor is improved; finally, the first metal layer is prepared on the lower surface of the substrate and sintered to obtain the bipolar transistor.

[0133] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a bipolar transistor, characterized in that: include: Obtaining a substrate, sequentially forming a first oxide layer and a protective layer on the upper surface of the substrate, and forming a first preset number of voltage divider rings at corresponding positions in the substrate through preset windows obtained by etching the protective layer; Performing high-temperature annealing and oxidation on the substrate after the voltage divider ring is prepared to form a second oxide layer at the position of the preset window, and removing the etched protective layer to obtain a first sample; Performing photolithography on the upper surface of the first sample using a corresponding photomask to determine a base region, an emitter region, and a boron-rich region, and performing corresponding ion implantation on the base region, the emitter region, and the boron-rich region, respectively, to obtain a second sample; A first dielectric layer is formed on the upper surface of the second sample, and a first metal lead window is formed on the first dielectric layer. Then, a first metal lead is formed at the first metal lead window to obtain a third sample; wherein the first metal lead window corresponds to the position of the emitter region and the boron-concentrated region; A second dielectric layer is formed on the upper surface of the third sample, and a second metal lead window is formed on the second dielectric layer. Then, an interconnection lead layer is formed at the second metal lead window, and a second metal lead is formed on the interconnection lead layer; the second metal lead window corresponds to the position of the emitter region. preparing a first metal layer on the lower surface of the substrate and sintering it to obtain a bipolar transistor; Wherein, when preparing the first oxide layer on the upper surface of the substrate, oxidation is performed in a low-temperature environment, and the temperature of the low-temperature environment is 600°C-1000°C.

2. The method for preparing a bipolar transistor according to claim 1, wherein: The interconnection lead layer is a nickel-chromium alloy layer.

3. The method for preparing a bipolar transistor according to claim 1, wherein: The step of preparing a first preset number of voltage divider rings at corresponding positions in the substrate by etching the preset windows obtained by etching the protective layer comprises: Coating a first photoresist on the protective layer, exposing and developing the first photoresist using a voltage divider ring photoresist as a mask to form a voltage divider ring exposure pattern; Using the first photoresist remaining on the voltage divider ring exposure pattern as a mask, etching the protective layer to obtain the first preset number of the preset windows; For each of the preset windows, performing a first ion implantation in the substrate at the preset window to obtain the voltage divider ring; Wherein, for each of the first preset number of voltage divider rings, the implantation energy and dosage of the first ions are different.

4. The method for preparing a bipolar transistor according to claim 1, wherein: Determining a base region and performing corresponding ion implantation on the base region includes: Coating a second photoresist on the upper surface of the first sample, exposing and developing the second photoresist using a base region photoresist as a mask to form a base region exposure pattern; The second photoresist remaining on the base area exposure pattern is used as a mask to perform a preset number of first ion implantations on the base area.

5. The method for preparing a bipolar transistor according to claim 1, wherein: Determining an emission region and performing corresponding ion implantation on the emission region includes: coating a third photoresist on the upper surface of the first sample, exposing and developing the third photoresist using the emission region photoresist as a mask to form an emission region exposure pattern; The second ion implantation is performed on the emitter region using the third photoresist remaining on the exposure pattern of the emitter region as a mask.

6. The method for preparing a bipolar transistor according to claim 1, wherein: The determining of the boron-concentrated region and performing corresponding ion implantation on the boron-concentrated region includes: coating a fourth photoresist on the upper surface of the first sample, exposing and developing the fourth photoresist using the boron-rich region photoresist as a mask to form a boron-rich region exposure pattern; The fourth photoresist remaining on the exposure pattern of the concentrated boron region is used as a mask to perform a first ion implantation on the concentrated boron region.

7. The method for preparing a bipolar transistor according to claim 1, wherein: After preparing a first layer of metal lead windows on the first dielectric layer, preparing a first layer of metal leads at the first layer of metal lead windows to obtain a third sample includes: Coating a fifth photoresist on the upper surface of the first dielectric layer, exposing and developing the fifth photoresist using the first layer metal lead window photoresist as a mask to form a first layer metal lead window exposure pattern; Using the fifth photoresist remaining on the exposure pattern of the first layer of metal lead windows as a mask, etching the first dielectric layer and the first oxide layer to obtain a second preset number of the first layer of metal lead windows; A seed layer is prepared at the first layer metal lead window and the upper surface of the remaining first dielectric layer, a sixth photoresist is coated on the upper surface of the seed layer, and the sixth photoresist is exposed and developed using the first layer metal lead photoresist as a mask to obtain a first layer metal lead exposure pattern; The sixth photoresist remaining on the first layer of metal lead exposure pattern is used as a mask to prepare a first layer of metal leads at each of the metal lead windows to obtain the third sample.

8. The method for preparing a bipolar transistor according to claim 1, wherein: After preparing a second layer of metal lead windows on the second dielectric layer, preparing an interconnection lead layer at the second layer of metal lead windows, and preparing a second layer of metal leads on the interconnection lead layer includes: Coating a seventh photoresist on the upper surface of the second dielectric layer, exposing and developing the seventh photoresist using the second layer metal lead window photoresist as a mask to form a second layer metal lead window exposure pattern; Using the remaining seventh photoresist on the exposure pattern of the second layer of metal lead windows as a mask, etching the second dielectric layer to obtain a third preset number of the second layer of metal lead windows; preparing an interconnection lead layer at the second layer metal lead window and the upper surface of the remaining second dielectric layer; Coating an eighth photoresist on the upper surface of the interconnection lead layer, exposing and developing the eighth photoresist using the second layer metal lead photoresist as a mask to obtain a second layer metal lead exposure pattern; Using the eighth photoresist remaining on the second metal lead exposure pattern as a mask, a second layer of metal leads is prepared on the upper surface of the interconnection lead layer and the interconnection lead layer not covered by the second metal lead is removed.

9. The method for preparing a bipolar transistor according to claim 1, wherein: The step of preparing a first metal layer on the lower surface of the substrate and sintering the layer to obtain a bipolar transistor comprises: preparing a first metal layer on the lower surface of the substrate; Arsenic is injected between the lower surface of the substrate and the first metal layer and then sintered to obtain the bipolar transistor.

10. A bipolar transistor, characterized in that: include: a first metal layer; A substrate is provided on the first metal layer; wherein a voltage divider ring, a base region, an emitter region and a boron-rich region are provided in the substrate; a first oxide layer provided on the upper surface of the substrate; a second oxide layer provided on the first oxide layer at a position corresponding to the voltage divider ring in the substrate; and a first dielectric layer provided on the first oxide layer and the second oxide layer; A first layer of metal leads is provided at the first layer of metal lead windows in the first oxide layer and the first dielectric layer; wherein the first layer of metal lead windows corresponds to the positions of the emitter region and the boron-rich region; a second dielectric layer provided on the upper surface of the first metal lead layer and the upper surface of the first dielectric layer; An interconnection wiring layer is provided at a second metal wiring window in the second dielectric layer; wherein the second metal wiring window corresponds to a position of the emitter region; a second layer of metal leads provided on the upper surface of the interconnection lead layer; Wherein, when the first oxide layer is provided on the upper surface of the substrate, oxidation is performed in a low temperature environment, and the temperature of the low temperature environment is 600°C-1000°C.

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