Three-layer mask-based deep mesa etching process for infrared detector and infrared detector

Abstract

The application provides an infrared detector deep mesa etching process based on a three-layer mask and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer and curing the stress buffer layer; depositing a hard mask as an etching barrier layer; depositing an inorganic oxide; spin-coating a photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photolithography process; taking the mesa pattern as a mask, transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by using plasma until the surface of the superlattice epitaxial layer is exposed; taking the three-layer mask as a barrier, performing deep etching by using inductively coupled plasma, and the etching depth is 5.6-6 microns; and performing a post-processing step. The process of the application can realize high-quality and high-aspect-ratio mesa etching without introducing additional pollution and significant cost increase, and is suitable for the preparation of deep mesa and high-aspect-ratio devices.

Description

Technical Field

[0001] This application relates to the field of infrared detector mesa etching technology, and in particular to a deep mesa etching process for infrared detectors based on a three-layer mask and an infrared detector. Background Technology

[0002] With the rapid development of long-wave infrared detector technology, infrared detectors based on type II superlattice materials (such as InAs / GaSb, InAs / InAsSb, etc.) have attracted much attention due to their excellent bandgap control performance and high quantum efficiency. However, in the mesa deep etching process, due to the stress difference at the material heterojunction interface, the complexity of etching selectivity control, and the poor mechanical stability of high aspect ratio micro / nano structures, serious problems such as mesa edge collapse or undercut often occur, leading to crosstalk between adjacent pixels and significantly reducing device yield and performance stability.

[0003] In traditional processes, the fabrication of deep mesa structures mainly faces the following technical bottlenecks: First, when the etching depth is greater than 5 μm, the use of single-layer or double-layer masks is prone to edge collapse or lateral drilling, leading to mesa morphology distortion and short circuits between adjacent pixels, severely restricting device yield; second, traditional hard masks (such as SiO2 / SiN) x The significant difference in etching selectivity between the mask and superlattice multilayer materials (such as contact layers, absorption layers, and barrier layers) can easily lead to over-etching at the bottom of the mesa, causing interface damage and increased leakage current. Furthermore, due to the mismatch in the coefficient of thermal expansion (CTE) between the mask and the superlattice material, thermal stress can be easily introduced during high-temperature process steps, resulting in microcracks in the mask or superlattice material, which affects the mechanical and electrical reliability of the device.

[0004] Current industry solutions primarily involve introducing hard metal masks (such as Ni and Cr) to enhance etching resistance and morphology retention during the etching process, or using silicon-on-insulator (SOI) substrates to assist etching and improve isolation. However, hard metal masks are prone to introducing metal contamination during removal, affecting the electrical properties of type II superlattice materials. SOI-assisted processes significantly increase substrate complexity and manufacturing costs, and have poor compatibility with existing III-V process platforms, limiting their potential for large-scale application.

[0005] Therefore, in the process of developing higher-performance long-wave infrared detectors, how to achieve high-quality, high aspect ratio mesa etching processes without introducing additional pollution and significant cost increases remains an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical issues, this application proposes a deep mesa etching process for an infrared detector based on a three-layer mask, and an infrared detector thereof.

[0007] The technical solution adopted in this application is: a deep mesa etching process for infrared detectors based on a three-layer mask, comprising the following steps:

[0008] 1) A stress buffer layer is spin-coated onto the surface of the superlattice epitaxial layer and then cured.

[0009] 2) Deposition of a hard mask as an etching barrier layer;

[0010] 3) Deposition of inorganic oxides;

[0011] 4) Spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through photolithography;

[0012] After the above steps 1)-4), a three-layer mask—stress buffer layer, etch barrier layer, and composite patterned top layer—is formed from bottom to top on the surface of the superlattice substrate;

[0013] 5) Using the mesa pattern as a mask, the mesa pattern is transferred to the hard mask via reactive ion etching;

[0014] 6) Use plasma etching to etch the stress buffer layer until the surface of the superlattice epitaxial layer is exposed;

[0015] 7) Using a three-layer mask as a barrier, inductively coupled plasma is used for deep etching, with an etching depth of 5.6~6μm;

[0016] 8) Use photoresist to protect the etched sidewalls;

[0017] 9) Each mask layer is removed sequentially using a stepped wet chemical process.

[0018] Furthermore, the stress buffer layer is made of benzocyclobutene or poly(p-xylene) material, with a thickness of 1~3μm.

[0019] Furthermore, the etching barrier layer is made of aluminum nitride or aluminum titanium nitride material, with a thickness of 0.2~0.8μm.

[0020] Furthermore, the composite patterned top layer is a composite layer of photoresist and inorganic oxide, with a thickness of 1.5~3μm.

[0021] Furthermore, the superlattice epitaxial layer is an InAs / GaSb epitaxial wafer.

[0022] Furthermore, in step 2), a hard mask is deposited as an etch barrier layer using magnetron sputtering.

[0023] Furthermore, in step 6), an O2 plasma etching stress buffer layer is used.

[0024] Furthermore, in step 8), acetone solution is used to remove the photoresist, hot phosphoric acid is used to remove the hard mask used as the etching barrier layer, and tetramethylammonium hydroxide solution is used to remove the stress buffer layer material.

[0025] Furthermore, in step 7), the inductively coupled plasma for deep etching uses a Cl2 / BCl3 / N2 mixed gas, and the resulting mesa sidewalls are steep sidewalls of 89±0.5°.

[0026] An infrared detector is fabricated using the aforementioned deep mesa etching process based on a three-layer mask.

[0027] The advantages of this application over the prior art are as follows:

[0028] 1) Achieve ultra-high aspect ratio mesa etching, with the mesa sidewall verticality measured by scanning electron microscopy being greater than 89° and the aspect ratio reaching 12:1;

[0029] 2) The AlN intermediate mask layer has a high etching selectivity of 58:1 for superlattice materials, and the bottom non-uniformity measured by the step profiler is less than 3%, which effectively avoids over-etching and interface damage.

[0030] 3) The benzocyclobutene (BCB) layer can absorb approximately 90% of thermal stress, and the mask cracking rate measured by a stress tester is less than 0.1%;

[0031] 4) When applied to long-wavelength detectors, the long-wavelength crosstalk suppression ratio measured by the photoelectric testing system is better than 40dB, and the average quantum efficiency is increased to over 60%. Attached Figure Description

[0032] The following description, in conjunction with the accompanying drawings, further illustrates this application:

[0033] Figure 1 This is a schematic diagram of a three-layer mask structure provided in an embodiment of this application;

[0034] Figure 2 A flowchart of the etching process for the long-wave infrared detector platform provided in this application embodiment;

[0035] Figure 3 This is a schematic diagram of the structure of the superlattice epitaxial layer provided in this embodiment;

[0036] Figure 4 A cross-sectional view of a platform taken by a scanning electron microscope (SEM) in an embodiment of this application;

[0037] Figure 5 This application provides a flowchart for etching selectivity testing and stress testing in its embodiments.

[0038] In the figure: 100 is the superlattice substrate, 101 is the superlattice epitaxial layer, 102 is the stress buffer layer, 103 is the etch barrier layer, 104 is the composite patterned top layer, 1 is the P-type buffer layer, 2 is the P-type electrode, 3 is the Be temperature-varying layer, 4 is the absorption layer, 5 is the barrier gradient layer, 6 is the N-type electrode, and 7 is the capping layer. Detailed Implementation

[0039] like Figure 1-5 As shown, this application provides a deep mesa etching process for infrared detectors based on a three-layer mask, wherein the three-layer mask structure includes, from bottom to top:

[0040] Stress buffer layer 102: This layer serves as the bottom mask and is made of low-stress organic polymer materials, such as benzocyclobutene (BCB) or parylene, with a thickness controlled between 1 and 3 μm. This layer mainly serves to buffer thermal stress and enhance adhesion. Its coefficient of thermal expansion (CTE≈52ppm / ℃) matches that of the superlattice material, and its adhesion is higher than 8 MPa.

[0041] Etching barrier layer 103: This layer serves as an intermediate mask and can be made of high-hardness nitride materials, such as aluminum nitride (AlN) or aluminum titanium nitride (AlTiN), with a thickness of 0.2~0.8μm. This layer has an extremely high etching selectivity (>50:1) for InAs / GaSb, effectively blocking ion bombardment damage during the etching process;

[0042] Composite Patterning Top Layer 104: This layer serves as the top mask and is a composite layer of photoresist and inorganic oxides, such as a combination of SU-8 negative photoresist and SiO2, with a thickness of approximately 1.5~3μm. This layer is used to achieve high-precision pattern transfer and has high resistance to plasma erosion (etching rate <5nm / min).

[0043] Based on the above three-layer mask structure, the main steps of the deep mesa etching process for infrared detectors in this application are as follows:

[0044] 1) A superlattice epitaxial layer 101 is epitaxially grown on the surface of a superlattice substrate 100, a stress buffer layer 102 is spin-coated on the surface of the superlattice epitaxial layer 101, and cured at 250°C in a nitrogen atmosphere.

[0045] 2) A hard mask is deposited as the etch barrier layer 103 using magnetron sputtering.

[0046] 3) Silicon oxide is deposited using PECVD;

[0047] 4) Spin-coating photoresist to form a composite patterned top layer 104, which is then processed by photolithography to form a mesa pattern;

[0048] 5) Using the mesa pattern as a mask, the mesa pattern is transferred to the hard mask by reactive ion etching (RIE). The gas used is a Cl2 / Ar mixture.

[0049] 6) Use O2 plasma to etch the stress buffer layer 102 until the surface of the superlattice epitaxial layer 101 is exposed;

[0050] 7) Using a three-layer mask as a barrier, inductively coupled plasma (ICP) is used for deep etching. A mixed gas of Cl2 / BCl3 / N2 is used, and the process parameters are controlled (using Cl2, BCl3, N2 program, and the temperature is set to 200℃ in Table) to achieve a steep sidewall of 89±0.5°, with a final etching depth of 5.6~6μm.

[0051] 8) Use photoresist to protect the etched sidewalls and reduce dark current generation;

[0052] 9) A stepped wet chemical process is used to remove each mask layer sequentially: acetone solution is used to remove photoresist, hot phosphoric acid is used to remove hard mask, and TMAH (tetramethylammonium hydroxide, abbreviated as TMAH) solution is used to remove low-stress organic polymer material.

[0053] See Figure 1 , Figure 1 A three-layer mask structure on a superlattice substrate 100 and a superlattice epitaxial layer 101 is shown. Figure 1 From bottom to top, the layers are: superlattice substrate 100, superlattice epitaxial layer 101, stress buffer layer 102, etch barrier layer 103, and composite patterned top layer 104. The thickness of each layer is shown to scale, illustrating the interlayer interface bonding. The superlattice substrate 100 can be an InAs / GaSb substrate, and the superlattice epitaxial layer 101 can be an InAs / GaSb epitaxial wafer.

[0054] See Figure 2 , Figure 2The process flow diagram of the long-wave infrared detector mesa etching is shown. The specific steps are as follows: The superlattice epitaxial layer 101 with three masks is exposed by a photolithography machine. The mesa pattern on the photomask is transferred to the composite patterned top layer 104. After development and hardening, it is sent to RIE etching to remove the etch barrier layer 103 without photoresist protection. At this time, the mesa pattern on the composite patterned top layer 104 has been accurately transferred down to the etch barrier layer 103. The surface composite patterned top layer 104 is removed by wet organic cleaning. Then, using O2 plasma and with the etching barrier layer 103 as a mask, the exposed stress buffer layer 102 is selectively etched away. The mesa pattern on the etching barrier layer 103 is accurately transferred downward to the stress buffer layer 102. Then, the mask of the etching barrier layer 103 is removed by hot phosphoric acid etching at 80°C until the surface of the superlattice epitaxial layer 101 below is exposed. The superlattice material is etched by ICP dry etching with the stress buffer layer 102 as a mask. Finally, the stress buffer layer 102 is removed by 25% TMAH solution, and a mesa with a good sidewall morphology is obtained.

[0055] In this embodiment, the superlattice substrate 100 is a GaSb substrate, and the superlattice epitaxial layer 101 is a GaSb epitaxial wafer. The structure of the GaSb epitaxial wafer is as follows: Figure 3 As shown, from bottom to top, the layers are: P-type buffer layer 1, P-type electrode 2, Be temperature-varying layer 3, absorption layer 4, barrier gradient layer 5, N-type electrode 6, and capping layer 7, where P-type buffer layer 1 is a GaSb buffer layer.

[0056] The following section uses a long-wave infrared (LWIR) InAs / GaSb superlattice detector as an example to specifically illustrate the deep mesa etching process of this application:

[0057] 1) Select a long-wavelength (LW) Nonp InAs / GaSb superlattice epitaxial wafer (total thickness 6.35μm), where Nonp represents an epitaxial material structure in which P-type semiconductor material is doped at the bottom and N-type semiconductor material is doped at the top;

[0058] 2) Spin-coating benzocyclobutene (BCB) 4024-40 polymer with a thickness of 3μm, curing at 250℃ in a nitrogen environment for 30 minutes to form stress buffer layer 102;

[0059] 3) A 0.5 μm thick AlN layer was deposited by magnetron sputtering as an etch barrier layer 103, with an RF power of 500 W;

[0060] 4) SiO2 was deposited using PECVD with a thickness of 1 μm. The coating parameters were N2 / N2O / SiH4 = 1000 / 710 / 125; RF: 20W; pressure: 1000 mtorr.

[0061] 5) Spin-coat SU-8 photoresist to a thickness of 2μm to form an SU-8 / SiO2 composite layer, and then use photolithography to define a long-wavelength mesa array (16μm×16μm) to form a mesa pattern;

[0062] 6) The AlN layer was etched using RIE with a gas composition of Cl2:Ar = 20:10 sccm and a power of 150W.

[0063] 7) The BCB layer was etched using O2 plasma at a power of 200W for 60 seconds;

[0064] 8) The P electrode 2 was etched to the superlattice epitaxial layer 101 using ICP etching to a depth of 5.6 μm. A mixed gas of BCl3 / Cl2 / N2 (10 / 5 / 5 sccm) was used during the ICP etching.

[0065] 9) Stepped mask removal: SU-8 photoresist is removed with acetone solution, AlN is etched with 80℃ hot phosphoric acid, and BCB is removed with 25% TMAH solution.

[0066] To verify the beneficial effects of this process, the following tests were conducted:

[0067] 1) Morphology testing: The morphology of the etched mesa structure was characterized using scanning electron microscopy (SEM), measuring the sidewall angles and aspect ratios. The cross-sectional morphology of the etched mesa structure was also characterized using SEM. The angles between the mesa sidewalls and the substrate plane were directly measured from the acquired SEM images to determine the sidewall angles, and the depth of the mesa trenches was measured to calculate the aspect ratio. Figure 4 The image shows a cross-sectional view of a platform taken by a scanning electron microscope (SEM), and Table 1 below shows the verticality and aspect ratio of the platform in different test areas.

[0068] Table 1. Verticality and aspect ratio of the test surface in different test areas.

[0069] .

[0070] 2) Etching selectivity test: The thickness change of each layer before and after etching is measured by a step profiler, and the etching selectivity is calculated. Under the same inductively coupled plasma etching process conditions, samples coated with aluminum nitride (AlN) film and superlattice material samples are processed respectively. The thickness change of the material before and after etching is measured by a step profiler, and the etching rates of aluminum nitride and superlattice material are calculated respectively. The ratio of the two is the etching selectivity.

[0071] 3) Stress Testing: A stress tester was used to measure the stress changes and cracking of the mask during thermal cycling. Specific tests were conducted to verify the thermal stress absorption and crack resistance of the stress buffer layer 102 (benzocyclobutene, BCB). A substrate curvature method stress tester (Toho Technology FLX-2320) was used to prepare AlN mask samples with and without BCB buffer layers on GaSb substrates. Under the same thermal cycling conditions (25℃ to 250℃), the stress value of the sample with the BCB buffer layer was only about 10% of that of the control sample, indicating that the BCB buffer layer absorbed approximately 90% of the thermal stress. After the thermal cycling tests, the sample surface was observed using a scanning electron microscope. Randomly inspected 1 mm... 2 No microcracks were found within the area, and the calculated mask cracking rate was less than 0.1%.

[0072] Figure 5 The flowcharts for etching selectivity testing and stress testing are shown.

[0073] 4) Electrical Performance Testing: The crosstalk suppression ratio (CSR) and quantum efficiency of the detector were measured using a photoelectric testing system. A single pixel was illuminated with a laser beam (wavelength ~10μm), and the current of the stimulated pixel and adjacent dark pixels was simultaneously measured using a semiconductor parameter analyzer (Keithley 4200-SCS). The calculated CSR was better than 40dB, indicating that the deep mesa isolation achieved by the three-layer mask process is significant. A photoelectric testing system consisting of a Fourier transform infrared spectrometer (FTIR) and a standard blackbody radiation source was used to measure the photocurrent and incident light power of the detector at a specific wavelength, and its quantum efficiency was calculated. The results showed that the average quantum efficiency was improved to over 60%.

[0074] Long-wave infrared detectors can be fabricated using the above process.

[0075] This application focuses on precision control and damage suppression in deep mesa etching, and is applicable to long-wave infrared focal plane arrays.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A three-mask based deep mesa etching process for infrared detectors, comprising: The method comprises the following steps: ​ 1) spin-coating a stress buffer layer on the surface of the superlattice epitaxial layer and curing it into shape; 2) depositing a hard mask as an etching stop layer; 3) depositing an inorganic oxide; 4) spin-coating a photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; After the above steps 1) to 4), a three-layer mask of stress buffer layer-etching stop layer-composite patterned top layer is formed on the surface of the superlattice substrate from bottom to top; 5) using the mesa pattern as a mask, transferring the mesa pattern to the hard mask through reactive ion etching; 6) etching the stress buffer layer by plasma until the surface of the superlattice epitaxial layer is exposed; 7) using the three-layer mask as a barrier, performing deep etching by inductively coupled plasma, with an etching depth of 5.6-6 μm; 8) using the photoresist to protect the etched sidewall; 9) using a step wet chemical process to sequentially remove each layer of mask.

2. The three-mask based deep mesa etching process for infrared detectors according to claim 1, wherein: The stress buffer layer is made of benzocyclobutene or poly-p-xylylene material, with a thickness of 1-3 μm.

3. The three-mask based deep mesa etching process for infrared detectors according to claim 1, wherein: The etching stop layer is made of aluminum nitride or aluminum titanium nitride material, with a thickness of 0.2-0.8 μm.

4. The three-mask based deep mesa etching process for infrared detectors according to claim 1, wherein: The composite patterned top layer is a composite layer of photoresist and inorganic oxide, with a thickness of 1.5-3 μm.

5. The three-mask based deep mesa etching process for infrared detectors according to any one of claims 1-4, wherein: The superlattice epitaxial layer is an InAs / GaSb epitaxial wafer.

6. The three-mask based deep mesa etching process for infrared detectors according to claim 5, wherein: In step 2), a hard mask as an etching stop layer is deposited by magnetron sputtering process.

7. The three-mask based deep mesa etching process for infrared detectors according to claim 5, wherein: In step 6), the stress buffer layer is etched by O2 plasma.

8. The three-mask based deep mesa etching process for infrared detectors according to claim 5, wherein: In step 9), the photoresist is removed by acetone solution, the hard mask as the etching stop layer is removed by hot phosphoric acid, and the stress buffer layer material is removed by tetramethylammonium hydroxide solution.

9. The three-mask based deep mesa etching process for infrared detectors according to claim 1, wherein: The inductively coupled plasma for deep etching in step 7) uses Cl2 / BCl3 / N2 mixed gas, and the mesa sidewall obtained by etching is an abrupt sidewall with an angle of 89±0.5°.

10. An infrared detector prepared by the three-layer mask-based infrared detector deep mesa etching process according to claim 1.

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