Masking process correction method, device, equipment and storage medium

Abstract

The present application relates to the field of integrated circuit manufacturing, and particularly relates to a mask process correction method, device, equipment and storage medium, wherein a target mask pattern and a corresponding design thickness are received; the target mask pattern is input as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; mask layer bottom simulation pattern sizes and mask layer top simulation pattern sizes corresponding to each edge section in the simulation electron beam exposure pattern are determined, to obtain corresponding side wall included angles; size-included angle comparison data groups corresponding to each edge section are determined according to the mask layer bottom simulation pattern sizes, to obtain included angle offset amounts; a target size offset amount is further determined; and the positions of the corresponding edge sections in the mask layer bottom simulation pattern are adjusted according to the target size offset amount. The similarity between the wafer pattern obtained by performing a photolithography process on the mask layer corrected by the present application and the photolithography target pattern is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a mask process correction method, apparatus, equipment, and storage medium. Background Technology

[0002] In large-scale integrated circuit manufacturing, the masks used in photolithography processes are typically manufactured using electron beam lithography and etching processes. Due to effects such as electron beam scattering and etching deviations, there are differences between the final mask pattern and the electron beam lithography pattern. Therefore, advanced photolithography processes (28 nanometers and below) have introduced Mask Process Correction (MPC) technology. This technology corrects the electron beam lithography pattern based on the target mask pattern, making the final mask pattern closer to the target mask pattern.

[0003] Currently, MPC (Model-Based Calibration) technology is typically a model-based mask process correction technique. In this process, for a given electron beam exposure pattern, a mask process correction model is used to obtain a simulated mask profile. The electron beam exposure pattern is then corrected based on the difference between the simulated mask profile and the target mask pattern. However, in existing technologies, the mask process correction model can only predict the profile of a specific mask absorption layer plane. In reality, the sidewall angles of the mask absorption layer are not 90 degrees, and the cross-sectional profile may differ in different thickness directions, with significant variations for different patterns. Therefore, existing mask process correction methods lack consideration for the different profile shapes in the actual mask thickness direction, resulting in less than ideal correction effects. Even when using the corrected electron beam exposure pattern in existing technologies for mask production, the final mask pattern still differs significantly from the target mask pattern, thus reducing the similarity between the post-lithographic wafer pattern and the target lithographic pattern obtained in subsequent photolithography processes.

[0004] Therefore, how to improve the accuracy of mask process correction, and thus improve the similarity between the lithographic wafer pattern obtained by subsequent photolithography processes and the lithographic target pattern, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a mask process correction method, apparatus, equipment, and storage medium to solve the problem in the prior art that the final mask pattern obtained after correction of the electron beam exposure pattern still has a large difference from the target mask pattern, thereby reducing the similarity between the lithographic wafer pattern obtained in subsequent photolithography processes and the lithographic target pattern.

[0006] To solve the above-mentioned technical problems, the present invention provides a mask process correction method, comprising:

[0007] Receive the target mask pattern and its corresponding design thickness;

[0008] The target mask pattern is used as the initial electron beam exposure pattern and input into the pre-trained mask top and bottom surface process correction model to iterate and obtain the simulated electron beam exposure pattern.

[0009] The mask top and bottom surface process correction model is used to determine the size of the simulated pattern at the bottom of the mask layer and the size of the simulated pattern at the top of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern.

[0010] The corresponding sidewall angle is obtained based on the size of the simulated pattern at the bottom of the mask layer, the size of the simulated pattern at the top of the mask layer, and the design thickness.

[0011] Based on the size of the simulated pattern at the bottom of the mask layer, determine the size-angle reference data set corresponding to each edge segment; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle, the change in the wafer pattern size after lithography caused by adjusting the size of the simulated pattern at the bottom of the mask layer and the angle of the sidewall separately in the optical proximity effect simulation;

[0012] The angle offset is obtained by subtracting the sidewall angle of each edge segment from the corresponding reference angle.

[0013] Based on the included angle offset, the target size offset is determined in the corresponding size-included angle comparison data group; in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall included angle is the reference included angle, adjusting the simulated pattern size at the bottom of the mask layer by the target size offset can compensate for the change in the wafer pattern size after photolithography caused by adjusting the reference included angle by the included angle offset;

[0014] Based on the target size offset, adjust the position of the corresponding edge segment in the simulation pattern at the bottom of the mask layer to obtain the updated simulation pattern at the bottom of the mask layer.

[0015] Optionally, in the mask process correction method, the method for obtaining the process correction model of the top and bottom surfaces of the mask includes:

[0016] Obtain a modeling pattern set; the modeling pattern set includes multiple modeling sample patterns;

[0017] Based on the modeling pattern set, a mask manufacturing process is run to obtain the process production pattern for each of the modeling sample patterns;

[0018] The process production patterns are scanned using a scanning electron microscope to obtain production scan images corresponding to each process production pattern;

[0019] The top and bottom pattern contours of the production scan image are determined based on the local maxima of the image gradient of the production scan image.

[0020] Using the modeling sample pattern, the bottom pattern contour, and the top pattern contour, the first linear coefficient, the bottom etching model term and the corresponding second linear coefficient, and the top etching model term and the corresponding third linear coefficient in the mask process model to be trained are calibrated to obtain a mask top and bottom surface process correction model. The mask process model to be trained can obtain the corresponding electron beam energy distribution from the modeling sample pattern using the first linear coefficient; and can determine the corresponding training bottom pattern contour based on the electron beam energy distribution, the bottom etching model term, and the second linear coefficient, and can determine the corresponding training top pattern contour based on the electron beam energy distribution, the top etching model term, and the third linear coefficient.

[0021] Optionally, in the mask process correction method, the mask process model to be trained obtains the corresponding training bottom pattern contour and training top pattern contour from the modeling sample pattern using the following three formulas:

[0022] ;

[0023] ;

[0024] ;

[0025] Where EB(x,y) represents the electron beam energy distribution at (x,y), M(x,y) represents the rasterized modeling sample pattern at (x,y), and G... i Let i be the i-th Gaussian function term. Indicates the convolution operation, b i The first linear coefficient corresponding to the i-th Gaussian function term;

[0026] ET b (x,y) represents the training bottom pattern outline at (x,y), D j For the j-th bottom etching model term calculated based on EB(x,y), c j T represents the corresponding second linear coefficient. b For the bottom etched image threshold, use T b ET interception b The training bottom pattern outline can be obtained by (x,y);

[0027] ET t (x,y) represents the training top pattern profile at (x,y), D kFor the k-th top etched model term calculated based on EB(x,y), c k T represents the corresponding third linear coefficient. t Threshold the top etched image using T t ET interception t The training top pattern outline can be obtained by (x,y).

[0028] Optionally, in the masking process correction method, the method for obtaining the size-angle comparison data set includes:

[0029] Obtain the nominal pattern of mask manufacturing in multiple sizes and the corresponding design thickness;

[0030] The nominal pattern of mask manufacturing is input into the process correction model of the top and bottom surfaces of the mask to obtain the corresponding simulated bottom pattern outline and simulated top pattern outline.

[0031] The simulated bottom pattern contour and the simulated top pattern contour are input into a pre-trained optical proximity correction model for simulation to obtain the simulated photolithography wafer reference size corresponding to the nominal pattern of the mask manufacturing.

[0032] The size of the simulated pattern is determined based on the outline of the simulated bottom pattern, and the size of the simulated pattern is used as the reference pattern size for the size-angle comparison data set.

[0033] Based on the simulated bottom pattern outline, the simulated top pattern outline, and the design thickness, determine the reference angles corresponding to the dimensions of each reference pattern.

[0034] Multiple simulated angle offsets are preset to keep the simulated bottom pattern outline unchanged. The reference angle is adjusted sequentially according to the multiple simulated angle offsets to obtain the corresponding first simulated top pattern update outline.

[0035] The simulated bottom pattern outline and multiple first simulated top pattern update outlines are input into the optical proximity correction model for simulation to obtain the first simulated photolithography wafer pattern size corresponding to different combinations of the simulated bottom pattern outline and the first simulated top pattern update outline.

[0036] The dimensions of the multiple first simulated photolithography wafer patterns are respectively subtracted from the reference size of the simulated photolithography wafer to obtain the change in the wafer pattern size after first photolithography corresponding to each simulated angle offset.

[0037] Multiple simulated size offsets are preset, the reference angle is kept unchanged, and the size of the reference pattern is adjusted sequentially according to the multiple simulated size offsets to obtain the second simulated top pattern update outline and the second simulated bottom pattern update outline corresponding to each simulated size offset.

[0038] The second simulated top pattern update contour and the second simulated bottom pattern update contour corresponding to the same simulated size offset are input into the optical proximity correction model for simulation to obtain the second simulated lithography wafer pattern size corresponding to the simulated size offset.

[0039] The dimensions of the multiple second simulated photolithography wafer patterns are respectively subtracted from the reference size of the simulated photolithography wafer to obtain the change in the wafer pattern size after second lithography corresponding to each simulated size offset.

[0040] Within the same size-angle comparison data set, the direction of change of the wafer pattern size after the second photolithography is determined to be opposite to the direction of change of the wafer pattern size after the first photolithography of the simulated angle offset. The simulated size offset with the closest numerical value is the target size offset corresponding to the simulated angle offset.

[0041] Optionally, in the mask process correction method, determining the reference angles corresponding to each reference pattern size based on the simulated bottom pattern outline, the simulated top pattern outline, and the design thickness includes:

[0042] Based on the design thickness, calculate the included angle of each edge segment in the simulated bottom pattern outline and the simulated top pattern outline corresponding to the nominal pattern of mask manufacturing for each size;

[0043] Arrange the included angles of the edge segments corresponding to the nominal pattern manufactured by the same mask in order of size, and take the median value after the arrangement as the reference included angle corresponding to the size of the reference pattern.

[0044] Optionally, in the mask process correction method, the target mask pattern is used as an initial electron beam exposure pattern and input into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulated electron beam exposure pattern, including:

[0045] The target mask pattern is used as the initial electron beam exposure pattern and input into a pre-trained mask top and bottom surface process correction model. The mask top and bottom surface process correction model determines the corresponding simulated pattern outline of the bottom of the mask layer based on the initial electron beam exposure pattern. Then, the position of the edge segment of the initial electron beam exposure pattern is adjusted by the EPE between the simulated pattern outline of the bottom of the mask layer and the target mask pattern. After multiple iterations, a simulated electron beam exposure pattern is obtained. The EPE between the simulated pattern outline of the bottom of the mask layer and the target mask pattern is less than a preset qualified threshold.

[0046] Optionally, in the mask process correction method, in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the change in the wafer pattern size after photolithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset is opposite in direction and the same in magnitude as the change in the wafer pattern size after photolithography caused by adjusting the reference angle by the angle offset.

[0047] A mask process correction device, comprising:

[0048] The receiving module is used to receive the target mask pattern and the corresponding design thickness;

[0049] The first correction module is used to input the target mask pattern as the initial electron beam exposure pattern into the pre-trained mask top and bottom surface process correction model, and iteratively obtain the simulated electron beam exposure pattern.

[0050] The top and bottom simulation module is used to determine the size of the simulated pattern at the bottom of the mask layer and the size of the simulated pattern at the top of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern through the mask top and bottom surface process correction model;

[0051] Angle calculation module is used to obtain the corresponding sidewall angle based on the size of the simulated pattern at the bottom of the mask layer, the size of the simulated pattern at the top of the mask layer, and the design thickness;

[0052] The top and bottom simulation module is used to determine the size-angle reference data set corresponding to each edge segment based on the size of the simulated pattern at the bottom of the mask layer; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle, the change in the wafer pattern size after lithography caused by the optical proximity effect simulation induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle is adjusted separately.

[0053] The included angle subtraction module is used to subtract the included angle of each edge segment from the corresponding reference included angle to obtain the included angle offset.

[0054] The offset calculation module is used to determine the target size offset in the corresponding size-angle reference data group based on the included angle offset; in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall included angle is the reference included angle, the change in the wafer pattern size after photolithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset can compensate for the change in the wafer pattern size after photolithography caused by adjusting the reference included angle by the included angle offset;

[0055] The second correction module is used to adjust the position of the corresponding edge segment in the simulation pattern at the bottom of the mask layer according to the target size offset, so as to obtain the updated simulation pattern at the bottom of the mask layer.

[0056] A mask process calibration device, comprising:

[0057] Memory, used to store computer programs;

[0058] A processor is configured to implement the steps of any of the mask process correction methods described above when executing the computer program.

[0059] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the mask process correction methods described above.

[0060] The mask process correction method provided by this invention involves receiving a target mask pattern and its corresponding design thickness; inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulated electron beam exposure pattern; determining the simulated bottom and top surface pattern dimensions of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern using the mask top and bottom surface process correction model; obtaining the corresponding sidewall angles based on the simulated bottom and top surface pattern dimensions and the design thickness; and determining a size-angle reference data set for each edge segment based on the simulated bottom surface pattern dimensions. The size-angle reference data set includes the corresponding reference pattern dimensions, reference angles, and, based on the reference pattern dimensions and reference angles, [further details needed]. The changes in the post-lithographic wafer pattern size caused by the optical proximity effect induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle are adjusted individually. The sidewall angle of each edge segment is subtracted from the corresponding reference angle to obtain the angle offset. Based on the angle offset, a target size offset is determined in the corresponding size-angle comparison data set. In the edge segment where the size of the simulated pattern at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the changes in the post-lithographic wafer pattern size caused by adjusting the size of the simulated pattern at the bottom of the mask layer by the target size offset can compensate for the changes in the post-lithographic wafer pattern size caused by adjusting the reference angle by the angle offset. Based on the target size offset, the position of the corresponding edge segment in the simulated pattern at the bottom of the mask layer is adjusted to obtain the updated simulated pattern at the bottom of the mask layer.

[0061] In increasingly smaller photolithography processes, the mask layer thickness is no longer negligible compared to the wavelength of the light source. The three-dimensional morphology of the mask layer has a significant impact on the critical dimensions of the wafer after photolithography. In this invention, after simulating the top and bottom cross-sections of the mask layer using a model, the sidewall angles corresponding to each simulated edge segment are further calculated, and the angular offset between each sidewall angle and a preset reference angle is calculated. An offset between the sidewall angle and the reference angle means that the wafer pattern obtained after photolithography will also undergo unexpected dimensional changes. This dimensional change of the wafer pattern after photolithography due to the change in sidewall angle is compensated for in this invention by adjusting the size of the simulated pattern at the bottom of the mask layer. This greatly reduces the impact of the error caused by the sidewall angle on the subsequent wafer pattern size after photolithography, improving the overall accuracy of mask process correction. The similarity between the wafer pattern obtained by photolithography using a mask layer corrected by this invention and the photolithographic target pattern is greatly improved. This invention also provides a mask process correction device, equipment, and storage medium with the above-mentioned beneficial effects. Attached Figure Description

[0062] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 A flowchart illustrating a specific embodiment of the mask process correction method provided by the present invention;

[0064] Figure 2 A cross-sectional schematic diagram of the mask layer in a specific embodiment of the mask process correction method provided by the present invention;

[0065] Figure 3 A flowchart illustrating a method for obtaining a mask top and bottom surface process correction model according to a specific embodiment of the mask process correction method provided by the present invention;

[0066] Figure 4 A curve showing the variation of the image gradient value at different positions in a production scan image of a specific embodiment of the mask process correction method provided by the present invention;

[0067] Figure 5 A flowchart illustrating a specific embodiment of the mask process correction method provided by the present invention for obtaining a size-angle reference data set;

[0068] Figure 6This is a schematic diagram of a specific embodiment of the mask process correction device provided by the present invention.

[0069] Figure label:

[0070] 100 - Receiver module; 200 - First correction module; 300 - Top and bottom simulation module; 400 - Angle calculation module; 500 - Top and bottom simulation module; 600 - Angle difference module; 700 - Offset calculation module; 800 - Second correction module. Detailed Implementation

[0071] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0072] The critical dimensions of the pattern on the wafer after photolithography are determined by the bottom contour and sidewall angle of the mask layer. In this case, existing mask process correction techniques that only correct the bottom contour of the mask absorption layer will result in significant accuracy errors.

[0073] The core of this invention is to provide a mask process correction method, the flowchart of one specific embodiment of which is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:

[0074] S101: Receive the target mask pattern and the corresponding design thickness.

[0075] The target mask pattern is the pattern of the shape of the mask layer to be achieved. Without correction, it can be the same as the pattern to be finally etched on the wafer. That is, the target mask pattern is generally the same as the photolithography target pattern.

[0076] The design thickness is the thickness that needs to be achieved in the production of the mask layer. Of course, the design thickness may not be obtained at the same time as the target mask pattern, or it may be obtained later. This invention does not limit this.

[0077] S102: Input the target mask pattern as the initial electron beam exposure pattern into the pre-trained mask top and bottom surface process correction model, and iterate to obtain the simulated electron beam exposure pattern.

[0078] As one specific implementation method, this step includes:

[0079] The target mask pattern is used as the initial electron beam exposure pattern and input into a pre-trained mask top and bottom surface process correction model. The mask top and bottom surface process correction model determines the corresponding simulated pattern outline of the bottom of the mask layer based on the initial electron beam exposure pattern. Then, the position of the edge segment of the initial electron beam exposure pattern is adjusted by the EPE between the simulated pattern outline of the bottom of the mask layer and the target mask pattern. After multiple iterations, a simulated electron beam exposure pattern is obtained. The EPE between the simulated pattern outline of the bottom of the mask layer and the target mask pattern is less than a preset qualified threshold.

[0080] Currently, the mask process correction models in related technologies all output mask layer pattern contour information in a single plane. However, the mask layer actually has a thickness. Therefore, the mask process correction model in this step is a mask top and bottom surface process correction model. In other words, after inputting the target mask pattern, the final output is the top layer pattern contour information (i.e., the simulated top pattern contour of the mask layer) and the bottom layer pattern contour information (i.e., the simulated bottom pattern contour of the mask layer) of the mask layer under a given design thickness. With the pattern contour information of the two layers, the edge segment position of the initial electron beam exposure pattern can be adjusted based on the simulated bottom pattern contour of the mask layer and the EPE (edge ​​placement error) between the simulated bottom pattern contour of the mask layer and the target mask pattern. The adjustment method is similar to that in existing related technologies and will not be described in detail here. Of course, depending on the actual situation, the simulated top pattern contour of the mask layer can be used as the reference instead of the simulated bottom pattern contour of the mask layer. This invention does not limit this.

[0081] S103: Using the mask top and bottom surface process correction model, determine the size of the simulated pattern at the bottom of the mask layer and the size of the simulated pattern at the top of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern.

[0082] Please refer to Figure 2 , Figure 2 This is a schematic cross-sectional view of the mask layer, indicated by CD. t The size of the simulated pattern on the top of the mask layer is indicated by CD. b The dimensions of the simulated pattern at the bottom of the mask layer are indicated by the outlines of the simulated pattern at the top and bottom of the mask layer, respectively, and h represents the design thickness. This represents the included angle of the side walls.

[0083] S104: Based on the size of the simulated pattern at the bottom of the mask layer, the size of the simulated pattern at the top of the mask layer, and the design thickness, the corresponding sidewall angle is obtained.

[0084] Given the size of the simulated pattern at the top and bottom of the mask layer, simply subtracting the two will yield twice the projected length of the hypotenuse on the bottom surface. The designed thickness is the height of the hypotenuse, from which the tan value of the sidewall angle can be obtained, allowing the angle value of the sidewall angle to be deduced.

[0085] Specifically, the angle value of the sidewall included angle can be obtained by the following formula (4):

[0086] ; (4)

[0087] in, CD is the angle value of the included angle of the sidewalls. t The size of the simulated pattern on the top of the mask layer, CD b h represents the size of the simulated pattern at the bottom of the mask layer, and h represents the designed thickness.

[0088] S105: Based on the size of the simulated pattern at the bottom of the mask layer, determine the size-angle reference data set corresponding to each edge segment; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle, the change in the wafer pattern size after lithography caused by adjusting the size of the simulated pattern at the bottom of the mask layer and the sidewall angle separately in the optical proximity effect simulation.

[0089] The size-angle reference data set in this step includes a unique reference pattern size and reference angle. Therefore, a unique corresponding size-angle reference data set can be determined through the results of the simulated pattern (i.e., the size of the simulated pattern at the bottom of the mask layer). Based on this, the changes in the wafer pattern size after photolithography caused by individually changing the size of the simulated pattern at the bottom of the mask layer and the sidewall angle, with the size of the simulated pattern at the bottom of the mask layer being the reference pattern size and the sidewall angle being the reference angle, are also recorded.

[0090] For example, suppose there exists a size-angle reference data set with a reference pattern size of 10 nanometers and a reference angle of 83 degrees. The lithographically patterned wafer size is 11 nanometers. If the reference angle is adjusted by a decrease of 3 degrees, i.e., the sidewall angle becomes 80 degrees (while the simulated pattern size at the bottom of the mask layer remains unchanged at 10 nanometers), the lithographically patterned wafer size becomes 12 nanometers. This can be denoted as Δ in the size-angle reference data set. =-3°, corresponding to a change in wafer pattern size after photolithography, WCD=+1nm; as another example, if the size of the simulated pattern at the bottom of the mask layer is reduced by 0.5 nm to 9.5 nm, while the sidewall angle remains unchanged at 83 degrees, the corresponding wafer pattern size after photolithography is 10 nm. This can be recorded as ΔW=-0.5 nm in the size-angle comparison data set, corresponding to a change in wafer pattern size after photolithography, WCD=-1 nm. The positive or negative sign indicates whether the corresponding data has increased or decreased.

[0091] S106: Subtract the included angle of each edge segment from the corresponding reference angle to obtain the included angle offset.

[0092] That is, the difference between the sidewall angle mentioned above and the reference angle.

[0093] S107: Based on the included angle offset, determine the target size offset in the corresponding size-included angle comparison data group; in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall included angle is the reference included angle, the change in the wafer pattern size after photolithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset can compensate for the change in the wafer pattern size after photolithography caused by adjusting the reference included angle by the included angle offset.

[0094] In this step, "compensation" refers to the change in wafer pattern size after photolithography caused by the target size offset. This change should be in the opposite direction to the change in wafer pattern size after photolithography caused by the corresponding included angle offset, and the values ​​should be as close as possible. The closer the values ​​are, the better the compensation effect.

[0095] Preferably, in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the change in wafer pattern size after photolithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset is opposite in direction and the same in magnitude as the change in wafer pattern size after photolithography caused by adjusting the reference angle by the angle offset.

[0096] To facilitate understanding, an example is provided here. Continuing from the previous example, suppose the reference pattern size in the size-angle comparison data set is 40 nanometers and the reference angle is 83 degrees. Based on this, the size-angle comparison data set records Δ... =-3°, corresponding to WCD=+1nm; while ΔW=-0.5nm, corresponding to WCD=-1nm, it can be said that the size of the simulated pattern at the bottom of the mask layer, ΔW=-0.5nm, is the included angle offset Δ = -3° target size offset.

[0097] Of course, it cannot be guaranteed that there is a size offset that causes the same change in the size of the wafer pattern after photolithography as the corresponding angle offset, but in the opposite direction. In this case, the size offset that causes the closest change in the size of the wafer pattern after photolithography and in the opposite direction can be selected as the corresponding target size offset, so as to maximize the compensation effect mentioned in this step.

[0098] S108: Adjust the position of the corresponding edge segment in the simulation pattern at the bottom of the mask layer according to the target size offset to obtain the updated simulation pattern at the bottom of the mask layer.

[0099] Since the previous step revealed that the offset of the sidewall angle caused a change in the size of the corresponding wafer pattern after photolithography, this step involves adjusting the size of the simulated pattern at the bottom of the mask layer according to the target size offset to compensate for the change in the size of the wafer pattern after photolithography caused by the angle offset.

[0100] As one specific implementation method, the flowchart of the method for obtaining the process correction model of the top and bottom surfaces of the mask is as follows: Figure 3 As shown, it includes:

[0101] A1: Obtain the modeling pattern set; the modeling pattern set includes multiple modeling sample patterns.

[0102] The modeling sample pattern can refer to relevant technologies and is a commonly used pattern in training mask process models, including one-dimensional and two-dimensional patterns. The patterns are usually relatively simple and include a variety of different key dimensions.

[0103] A2: Based on the modeling pattern set, run the mask manufacturing process to obtain the process production pattern of each of the modeling sample patterns.

[0104] A3: Use a scanning electron microscope to scan the process production patterns to obtain production scan images corresponding to each process production pattern.

[0105] The process production pattern is a pattern obtained through production, which needs to be scanned to obtain its corresponding data (i.e., the production scan image).

[0106] A4: Determine the top and bottom pattern contours of the production scan image based on the local maxima of the image gradient of the production scan image.

[0107] You can refer to this. Figure 4 , Figure 4The figure shows the curves of the image gradient values ​​at different positions of the production scan image. It can be seen that local maxima of the image gradient appear at both the top and bottom pattern contours of the process production pattern. Since the top pattern contour of the process production pattern must be outside the bottom pattern contour, the position of the local maximum closest to the outer ends corresponds to the top pattern contour, while the positions of the two local maxima located inside correspond to the bottom pattern contour.

[0108] A5: Using the modeling sample pattern, the bottom pattern contour, and the top pattern contour, calibrate the first linear coefficient, the bottom etching model item and the corresponding second linear coefficient, and the top etching model item and the corresponding third linear coefficient in the mask process model to be trained, to obtain the mask top and bottom surface process correction model; wherein, the mask process model to be trained can obtain the corresponding electron beam energy distribution from the modeling sample pattern through the first linear coefficient; and can determine the corresponding training bottom pattern contour according to the electron beam energy distribution, the bottom etching model item, and the second linear coefficient, and can determine the corresponding training top pattern contour according to the electron beam energy distribution, the top etching model item, and the third linear coefficient.

[0109] Specifically, the mask process model to be trained obtains the corresponding training bottom pattern contour and training top pattern contour from the modeling sample pattern through the following methods (1), (2), and (3), including:

[0110] ; (1)

[0111] ; (2)

[0112] ; (3)

[0113] Where EB(x,y) represents the electron beam energy distribution at (x,y), M(x,y) represents the rasterized modeling sample pattern at (x,y), and G... i Let i be the i-th Gaussian function term. Indicates the convolution operation, b i The first linear coefficient corresponding to the i-th Gaussian function term;

[0114] ET b (x,y) represents the training bottom pattern outline at (x,y), D j For the j-th bottom etching model term calculated based on EB(x,y), c j T represents the corresponding second linear coefficient. b For the bottom etched image threshold, use Tb ET interception b The training bottom pattern outline can be obtained by (x,y);

[0115] ET t (x,y) represents the training top pattern profile at (x,y), D k For the k-th top etched model term calculated based on EB(x,y), c k T represents the corresponding third linear coefficient. t Threshold the top etched image using T t ET interception t The training top pattern outline can be obtained by (x,y).

[0116] According to the above formulas, it is easy to see that formula (2) is used to calculate the training bottom pattern contour, and formula (3) is used to calculate the training top pattern contour. During the model calibration process, it is necessary to continuously adjust the first linear coefficient, the bottom etching model term, the second linear coefficient, the top etching model term, and the third linear coefficient so that the training bottom pattern contour obtained by formula (2) through inputting the modeling sample pattern is as close as possible to the corresponding bottom pattern contour, and at the same time, the training top pattern contour obtained by formula (3) through inputting the modeling sample pattern is as close as possible to the corresponding top pattern contour. When the EPE between the training bottom pattern contour and the bottom pattern contour is less than the preset allowable threshold, and the EPE between the training top pattern contour and the top pattern contour is less than the preset allowable threshold, it is considered that the mask process model to be trained has been calibrated, or the calibration iteration exceeds the preset maximum number of times, it is also considered that the mask process model to be trained has been calibrated.

[0117] As a preferred embodiment, a flowchart illustrating a specific implementation of the method for obtaining the size-angle comparison data set is shown below. Figure 5 As shown, it includes:

[0118] B1: Obtain the nominal pattern of mask manufacturing in multiple sizes and the corresponding design thickness.

[0119] The nominal pattern for mask manufacturing is a one-dimensional periodic pattern with a fixed line width and spacing of W0. The design thickness is the design thickness of the nominal pattern for mask manufacturing. It should be noted that since the size-angle comparison data set will be applied to the mask process correction method described above, the design thickness of the nominal pattern for mask manufacturing in this step is preferably consistent with the design thickness of the target mask pattern in the mask process correction method.

[0120] B2: Input the nominal pattern of the mask manufacturing into the process correction model of the top and bottom surfaces of the mask to obtain the corresponding simulated bottom pattern outline and simulated top pattern outline.

[0121] Please refer to the previous text; this step will not be repeated here.

[0122] B3: Input the simulated bottom pattern contour and the simulated top pattern contour into the pre-trained optical proximity correction model for simulation to obtain the simulated photolithography wafer reference size corresponding to the nominal pattern of the mask manufacturing.

[0123] In this step, the mask layer composed of the simulated bottom pattern outline and the simulated top pattern outline is input into the optical proximity correction (OPC) model for simulation to see what the critical dimensions (i.e., the simulated photolithography wafer reference dimensions) of the pattern left on the wafer after photolithography with the mask layer as a mask are.

[0124] B4: Determine the corresponding simulated pattern size based on the simulated bottom pattern outline, and use the simulated pattern size as the reference pattern size corresponding to the size-angle reference data group.

[0125] In other words, in this step, the key dimensions of the bottom surface of the simulated mask layer need to be used as the standard, that is, the reference group size. Alternatively, it can be considered that a blank size-angle comparison data set is created in this step, and the corresponding reference pattern size is the simulated pattern size.

[0126] To further explain, the simulated pattern size is calculated from the simulated bottom pattern outline, which in turn is simulated from the mask manufacturing nominal pattern. Therefore, for a mask manufacturing nominal pattern of a single size, there should be a set of size-angle comparison data for a reference pattern size.

[0127] B5: Determine the reference angles corresponding to the dimensions of each reference pattern based on the simulated bottom pattern outline, the simulated top pattern outline, and the design thickness.

[0128] This step follows the previous one, determining the reference angle in the size-angle comparison data set. Up to this point, the reference pattern size and the reference angle in the size-angle comparison data set have been filled. It is still necessary to fill in the reference pattern size and the reference angle by separately adjusting the simulated pattern size (essentially the same object as the simulated pattern size at the bottom of the mask layer mentioned earlier, both being key dimensions of the bottom pattern of the mask layer in the simulation process, but due to different processes, this application uses different names) or the corresponding post-lithography wafer pattern size change in the simulation of the optical proximity effect caused by the sidewall angle.

[0129] B6: Preset multiple simulated angle offsets, keep the simulated bottom pattern outline unchanged, and adjust the reference angles sequentially according to the multiple simulated angle offsets to obtain the corresponding first simulated top pattern update outline.

[0130] The reference angle can be set as 0,m of the simulated included angle offsets are set as Δ 1. Δ 2. Δ 3、…、Δ m Then, "adjusting the reference angle sequentially according to the multiple simulated angle offsets" is... 0+Δ 1, 0+Δ 2, 0+Δ 3, ..., 0+Δ m .

[0131] Since the size of the reference pattern remains unchanged, the outline of the simulated bottom pattern remains unchanged, but the reference angle is changed. Therefore, the outline of the simulated top pattern will change, and the changed outline of the simulated top pattern is the updated outline of the first simulated top pattern.

[0132] B7: Input the simulated bottom pattern contour and multiple first simulated top pattern update contours into the optical proximity correction model for simulation to obtain the first simulated lithography wafer pattern size corresponding to different combinations of the simulated bottom pattern contour and the first simulated top pattern update contours.

[0133] The simulated bottom pattern outline is combined with different first simulated top pattern update outlines, plus the design thickness, to obtain the three-dimensional model of each mask layer after the reference angle is adjusted. Each three-dimensional model is input into the optical proximity correction model for simulation, and the lithographic size of the pattern on the lithographic wafer (i.e. the size of the first simulated lithographic wafer pattern) is obtained by OPC after the sidewall angle is offset from the reference angle by different simulated angle offsets.

[0134] B8: Subtract the dimensions of the multiple first simulated lithography wafer patterns from the reference dimensions of the simulated lithography wafers to obtain the changes in the wafer pattern dimensions after lithography corresponding to each simulated angle offset.

[0135] For example, if the reference size of the simulated lithography wafer is 10 nanometers and the reference angle of the sidewall is 85 degrees, and the simulated angle offset is -5 degrees, the corresponding size of the first simulated lithography wafer pattern is 12 nanometers, that is, the corresponding simulated angle offset Δ At -5°, the wafer pattern size change after the first photolithography is ΔWCD1 = +2nm.

[0136] B9: Preset multiple simulated size offsets, keep the reference angle unchanged, and adjust the reference pattern size sequentially according to the multiple simulated size offsets to obtain the second simulated top pattern update outline and the second simulated bottom pattern update outline corresponding to each simulated size offset.

[0137] Referring to the processing method in step B6, the reference pattern size is set to W0, and the n simulated size offsets are set to ΔW1, ΔW2, ΔW3, ..., ΔW n Then, "adjusting the dimensions of the reference pattern sequentially according to the multiple simulated dimension offsets" is W0+ΔW1, W0+ΔW2, W0+ΔW3, ..., W0+ΔW n .

[0138] Since adjusting the size of the reference pattern is essentially adjusting the size of the simulated pattern, that is, adjusting the outline of the simulated bottom pattern, and although the sidewall angle remains unchanged, the outline of the simulated bottom pattern changes, so the outline of the simulated top pattern must also change, thus obtaining the updated outlines of the second simulated top pattern and the second simulated bottom pattern respectively.

[0139] B10: Input the updated outlines of the second simulated top pattern and the second simulated bottom pattern corresponding to the same simulated size offset into the optical proximity correction model for simulation to obtain the size of the second simulated lithography wafer pattern corresponding to the simulated size offset.

[0140] Referring to step B7, the present invention will not be described in detail here.

[0141] B11: Subtract the dimensions of the multiple second simulated lithography wafer patterns from the reference dimensions of the simulated lithography wafer to obtain the changes in the wafer pattern dimensions after lithography corresponding to each simulated dimension offset.

[0142] Referring to step B8, the present invention will not be repeated here. For example, if the reference size of the simulated lithography wafer is 10 nanometers and the reference angle of the sidewall is 85 degrees, in the size-angle comparison data set, when the simulated size offset is -1 nanometer, the corresponding size of the first simulated lithography wafer pattern is 9 nanometers. That is, when the simulated size offset ΔW = -1 nm, the change in wafer pattern size after the second lithography is ΔWCD2 = -2 nm.

[0143] B12: Within the same size-angle comparison data group, determine that the change in wafer pattern size after the second photolithography is opposite to the change in wafer pattern size after the first photolithography of the simulated angle offset, and the simulated size offset with the closest numerical value is the target size offset corresponding to the simulated angle offset.

[0144] Continuing with the previous example, still using the simulated lithography wafer reference size of 10 nanometers and the reference sidewall angle of 85 degrees as an example, the simulated angle offset Δ When the angle is -5°, the wafer pattern size change after the first photolithography is ΔWCD1 = +2nm; when the simulated size offset is ΔW = -1nm, the wafer pattern size change after the second photolithography is ΔWCD2 = -2nm. It can be seen that the magnitude of the wafer pattern size change after photolithography is the same in both cases, but the direction is opposite. Therefore, it can be determined that the simulated size offset ΔW = -1nm is the simulated angle offset Δ = -5° target size offset.

[0145] Of course, in the example mentioned above, the simulated angle offset and the corresponding target size offset are exactly the same in terms of the change in wafer pattern size after photolithography. In actual operation, there are also cases where they are not exactly the same. In this case, it is necessary to find the simulated size offset that is closest to the change in wafer pattern size after photolithography of the second photolithography and has the opposite direction of change as the corresponding target size offset.

[0146] Furthermore, based on the simulated bottom pattern outline, the simulated top pattern outline, and the design thickness, the reference angles corresponding to each reference pattern size are determined as follows:

[0147] B01: Based on the design thickness, calculate the included angle of each edge segment in the simulated bottom pattern outline and the simulated top pattern outline corresponding to the nominal pattern of mask manufacturing for each size.

[0148] Of course, for the same mask manufacturing nominal pattern, the sidewall angles at different positions will also be different. Therefore, in this step, the simulated bottom pattern outline and the simulated top pattern outline corresponding to the mask manufacturing nominal pattern of the same size are divided into multiple edge segments, and the sidewall angles on each edge segment are calculated, that is, the edge segment angles.

[0149] B02: Arrange the included angles of the edge segments corresponding to the nominal pattern manufactured by the same mask in order of size, and take the median value after the arrangement as the reference included angle corresponding to the size of the reference pattern.

[0150] In this step, the median value of the included angles of the edge segments arranged in ascending order is taken as the corresponding reference angle. The included angles of the edge segments can be arranged from smallest to largest or from largest to smallest. This ensures the representativeness of the reference angle while greatly saving computing resources and improving processing efficiency. Of course, other methods can also be used, such as taking the average value of all the included angles of the edge segments corresponding to the nominal pattern manufactured by the same mask as the reference angle. This invention does not limit this.

[0151] The mask process correction method provided by this invention involves receiving a target mask pattern and its corresponding design thickness; inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulated electron beam exposure pattern; determining the simulated bottom and top surface pattern dimensions of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern using the mask top and bottom surface process correction model; obtaining the corresponding sidewall angles based on the simulated bottom and top surface pattern dimensions and the design thickness; and determining a size-angle reference data set for each edge segment based on the simulated bottom surface pattern dimensions. The size-angle reference data set includes the corresponding reference pattern dimensions, reference angles, and, based on the reference pattern dimensions and reference angles, [further details needed]. The changes in the post-lithographic wafer pattern size caused by the optical proximity effect induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle are adjusted individually. The sidewall angle of each edge segment is subtracted from the corresponding reference angle to obtain the angle offset. Based on the angle offset, a target size offset is determined in the corresponding size-angle comparison data set. In the edge segment where the size of the simulated pattern at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the changes in the post-lithographic wafer pattern size caused by adjusting the size of the simulated pattern at the bottom of the mask layer by the target size offset can compensate for the changes in the post-lithographic wafer pattern size caused by adjusting the reference angle by the angle offset. Based on the target size offset, the position of the corresponding edge segment in the simulated pattern at the bottom of the mask layer is adjusted to obtain the updated simulated pattern at the bottom of the mask layer. In the increasingly smaller photolithography processes, the thickness of the mask layer can no longer be ignored compared to the wavelength of the light source. The three-dimensional morphology of the mask layer has a significant impact on the critical dimensions of the wafer after photolithography. In this invention, after simulating the top and bottom cross-sections of the mask layer using a model, the sidewall angles corresponding to each simulated edge segment are further calculated, and the angular offset between each sidewall angle and the preset reference angle is calculated. An offset between the sidewall angle and the reference angle means that the wafer pattern obtained after photolithography will also undergo unexpected dimensional changes. This part of the wafer pattern size change after photolithography due to the change in sidewall angle is compensated by adjusting the size of the simulated pattern at the bottom of the mask layer in this invention. This greatly reduces the impact of the error caused by the sidewall angle on the wafer pattern size after photolithography, improves the overall accuracy of mask process correction, and greatly enhances the similarity between the wafer pattern obtained by photolithography using the mask layer corrected by this invention and the photolithographic target pattern.

[0152] The mask process correction device provided in the embodiments of the present invention will be described below. The mask process correction device described below can be referred to in correspondence with the mask process correction method described above.

[0153] Figure 6 This is a structural block diagram of the mask process correction device provided in an embodiment of the present invention. (Refer to...) Figure 6 The mask process correction device may include:

[0154] The receiving module 100 is used to receive the target mask pattern and the corresponding design thickness;

[0155] The first correction module 200 is used to input the target mask pattern as the initial electron beam exposure pattern into the pre-trained mask top and bottom surface process correction model, and iteratively obtain the simulated electron beam exposure pattern.

[0156] The top and bottom simulation module 300 is used to determine the size of the simulated pattern at the bottom of the mask layer and the size of the simulated pattern at the top of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern through the mask top and bottom surface process correction model.

[0157] Angle calculation module 400 is used to obtain the corresponding sidewall angle based on the size of the simulated pattern at the bottom of the mask layer, the size of the simulated pattern at the top of the mask layer, and the design thickness;

[0158] The top and bottom simulation module 500 is used to determine the size-angle reference data set corresponding to each edge segment based on the size of the simulated pattern at the bottom of the mask layer; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle, the change in the wafer pattern size after photolithography caused by the optical proximity effect simulation induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle is adjusted separately;

[0159] Angle subtraction module 600 is used to subtract the sidewall angle of each edge segment from the corresponding reference angle to obtain the angle offset.

[0160] The offset calculation module 700 is used to determine the target size offset in the corresponding size-angle reference data group based on the included angle offset; in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall included angle is the reference included angle, the change in the wafer pattern size after photolithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset can compensate for the change in the wafer pattern size after photolithography caused by adjusting the reference included angle by the included angle offset;

[0161] The second correction module 800 is used to adjust the position of the corresponding edge segment in the simulation pattern at the bottom of the mask layer according to the target size offset, so as to obtain the updated simulation pattern at the bottom of the mask layer.

[0162] In a preferred embodiment, the device for acquiring the process correction model of the top and bottom surfaces of the mask includes:

[0163] The sample acquisition module is used to acquire a modeling pattern set; the modeling pattern set includes multiple modeling sample patterns.

[0164] The sample production module is used to run a mask manufacturing process based on the modeling pattern set to obtain the process production pattern of each of the modeling sample patterns;

[0165] The scanning module is used to scan the process production patterns using a scanning electron microscope to obtain production scan images corresponding to each process production pattern;

[0166] The maximum contour module is used to determine the top and bottom pattern contours of the production scan image based on the local maxima of the image gradient of the production scan image.

[0167] The model training module is used to calibrate the first linear coefficient, the bottom etching model term and the corresponding second linear coefficient, and the top etching model term and the corresponding third linear coefficient in the mask process model to be trained using the modeling sample pattern, the bottom pattern contour, and the top pattern contour, to obtain a mask top and bottom surface process correction model; wherein, the mask process model to be trained can obtain the corresponding electron beam energy distribution from the modeling sample pattern through the first linear coefficient; and can determine the corresponding training bottom pattern contour according to the electron beam energy distribution, the bottom etching model term and the second linear coefficient, and can determine the corresponding training top pattern contour according to the electron beam energy distribution, the top etching model term and the third linear coefficient.

[0168] In one preferred embodiment, the model training module includes a model simulation unit;

[0169] The model simulation unit is used to enable the mask process model to be trained to obtain the corresponding training bottom pattern outline and training top pattern outline from the modeling sample pattern through the following methods (1), equations (2) and (3), including:

[0170] ; (1)

[0171] ; (2)

[0172] ; (3)

[0173] Where EB(x,y) represents the electron beam energy distribution at (x,y), M(x,y) represents the rasterized modeling sample pattern at (x,y), and G... iLet i be the i-th Gaussian function term. Indicates the convolution operation, b i The first linear coefficient corresponding to the i-th Gaussian function term;

[0174] ET b (x,y) represents the training bottom pattern outline at (x,y), D j For the j-th bottom etching model term calculated based on EB(x,y), c j T represents the corresponding second linear coefficient. b For the bottom etched image threshold, use T b ET interception b The training bottom pattern outline can be obtained by (x,y);

[0175] ET t (x,y) represents the training top pattern profile at (x,y), D k For the k-th top etched model term calculated based on EB(x,y), c k T represents the corresponding third linear coefficient. t Threshold the top etched image using T t ET interception t The training top pattern outline can be obtained by (x,y).

[0176] In a preferred embodiment, the apparatus for obtaining the size-angle comparison data set includes:

[0177] The nominal acquisition module is used to acquire the nominal patterns for mask manufacturing of multiple sizes and their corresponding design thicknesses;

[0178] The top and bottom calculation module is used to input the nominal pattern of mask manufacturing into the mask top and bottom surface process correction model to obtain the corresponding simulated bottom pattern outline and simulated top pattern outline.

[0179] The benchmark simulation module is used to input the simulated bottom pattern contour and the simulated top pattern contour into a pre-trained optical proximity correction model for simulation, and to obtain the simulated photolithography wafer reference size corresponding to the nominal pattern of the mask manufacturing.

[0180] The benchmark determination module is used to determine the corresponding simulated pattern size based on the simulated bottom pattern outline, and to use the simulated pattern size as the benchmark pattern size corresponding to the size-angle comparison data set.

[0181] Angle determination module is used to determine the reference angles corresponding to each reference pattern size based on the simulated bottom pattern outline, the simulated top pattern outline, and the design thickness.

[0182] The first bottom contour update module is used to preset multiple simulated angle offsets, keep the simulated bottom pattern contour unchanged, and adjust the reference angle sequentially according to the multiple simulated angle offsets to obtain the corresponding first simulated top pattern update contour.

[0183] The first lithography simulation module is used to input the simulated bottom pattern outline and multiple first simulated top pattern update outlines into the optical proximity correction model for simulation, and obtain the first simulated lithography wafer pattern size corresponding to the combination of the simulated bottom pattern outline and different first simulated top pattern update outlines.

[0184] The first lithography change module is used to subtract the dimensions of multiple first simulated lithography wafer patterns from the reference dimensions of the simulated lithography wafers to obtain the changes in the wafer pattern dimensions after first lithography corresponding to each simulated angle offset.

[0185] The second bottom contour update module is used to preset multiple simulated size offsets, keep the reference angle unchanged, and adjust the reference pattern size sequentially according to the multiple simulated size offsets to obtain the second simulated top pattern update contour and the second simulated bottom pattern update contour corresponding to each simulated size offset.

[0186] The second lithography simulation module is used to input the second simulated top pattern update contour and the second simulated bottom pattern update contour corresponding to the same simulated size offset into the optical proximity correction model for simulation, so as to obtain the second simulated lithography wafer pattern size corresponding to the simulated size offset.

[0187] The second lithography variation module is used to subtract the dimensions of multiple second simulated lithography wafer patterns from the reference dimension of the simulated lithography wafer to obtain the change in wafer pattern size after lithography corresponding to each simulated dimension offset.

[0188] The correspondence determination module is used to determine, within the same size-angle comparison data group, the direction of change of the wafer pattern size after the second photolithography is opposite to the direction of change of the wafer pattern size after the first photolithography of the simulated angle offset, and the simulated size offset with the closest numerical value is the target size offset corresponding to the simulated angle offset.

[0189] In a preferred embodiment, the included angle determination module includes:

[0190] The edge segment angle unit is used to calculate the edge segment angle corresponding to each edge segment in the simulated bottom pattern outline and the simulated top pattern outline of each size mask manufacturing nominal pattern, in combination with the design thickness.

[0191] The median determination unit is used to arrange the included angles of the edge segments corresponding to the nominal pattern of the same mask manufacturing in order of size, and take the median value after arrangement as the reference included angle corresponding to the size of the reference pattern.

[0192] In a preferred embodiment, the first calibration module 200 includes:

[0193] The EPE bottom surface iteration unit is used to input the target mask pattern as the initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model. The mask top and bottom surface process correction model determines the corresponding mask layer bottom simulation pattern outline based on the initial electron beam exposure pattern. Then, the position of the edge segment of the initial electron beam exposure pattern is adjusted by the EPE between the mask layer bottom simulation pattern outline and the target mask pattern. After multiple iterations, a simulated electron beam exposure pattern is obtained. The EPE between the mask layer bottom simulation pattern outline corresponding to the simulated electron beam exposure pattern and the target mask pattern is less than a preset qualified threshold.

[0194] The mask process correction device provided by this invention includes: a receiving module 100 for receiving a target mask pattern and its corresponding design thickness; a first correction module 200 for inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulated electron beam exposure pattern; a top and bottom simulation module 300 for determining the simulated bottom pattern size and the simulated top pattern size of each edge segment in the simulated electron beam exposure pattern using the mask top and bottom surface process correction model; an angle calculation module 400 for obtaining the corresponding sidewall angle based on the simulated bottom pattern size, the simulated top pattern size, and the design thickness; and a top and bottom simulation module 500 for determining the size-angle comparison data set corresponding to each edge segment based on the simulated bottom pattern size. The size-angle comparison data set includes the corresponding reference pattern size, the reference angle, and the size of the reference pattern size and the angle of the simulated top pattern. Based on the reference angle, the change in the wafer pattern size after lithography caused by the optical proximity effect simulation induced by the sidewall angle of the simulated pattern size at the bottom of the mask layer is adjusted separately; the angle subtraction module 600 is used to subtract the sidewall angle of each edge segment from the corresponding reference angle to obtain the angle offset; the offset calculation module 700 is used to determine the target size offset in the corresponding size-angle comparison data group according to the angle offset; in the edge segment where the simulated pattern size at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the change in the wafer pattern size after lithography caused by adjusting the simulated pattern size at the bottom of the mask layer by the target size offset can compensate for the change in the wafer pattern size after lithography caused by adjusting the reference angle by the angle offset; the second correction module 800 is used to adjust the position of the corresponding edge segment in the simulated pattern at the bottom of the mask layer according to the target size offset to obtain the updated simulated pattern at the bottom of the mask layer.In the increasingly smaller photolithography processes, the thickness of the mask layer can no longer be ignored compared to the wavelength of the light source. The three-dimensional morphology of the mask layer has a significant impact on the critical dimensions of the wafer after photolithography. In this invention, after simulating the top and bottom cross-sections of the mask layer using a model, the sidewall angles corresponding to each simulated edge segment are further calculated, and the angular offset between each sidewall angle and the preset reference angle is calculated. An offset between the sidewall angle and the reference angle means that the wafer pattern obtained after photolithography will also undergo unexpected dimensional changes. This part of the wafer pattern size change after photolithography due to the change in sidewall angle is compensated by adjusting the size of the simulated pattern at the bottom of the mask layer in this invention. This greatly reduces the impact of the error caused by the sidewall angle on the wafer pattern size after photolithography, improves the overall accuracy of mask process correction, and greatly enhances the similarity between the wafer pattern obtained by photolithography using the mask layer corrected by this invention and the photolithographic target pattern.

[0195] The mask process correction device of this embodiment is used to implement the aforementioned mask process correction method. Therefore, the specific implementation of the mask process correction device can be found in the embodiment section of the mask process correction method above. For example, the receiving module 100, the first correction module 200, the top and bottom simulation module 300, the included angle calculation module 400, the top and bottom simulation module 500, the included angle difference module 600, the offset calculation module 700, and the second correction module 800 are respectively used to implement steps S101, S102, S103, and S104 in the above-mentioned mask process correction method. Therefore, its specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0196] The present invention also provides a mask process correction device, comprising:

[0197] Memory, used to store computer programs;

[0198] A processor is configured to implement the steps of any of the mask process correction methods described above when executing the computer program. The mask process correction method provided by this invention involves: receiving a target mask pattern and its corresponding design thickness; inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model, iteratively obtaining a simulated electron beam exposure pattern; determining, through the mask top and bottom surface process correction model, the dimensions of the simulated bottom and top surfaces of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern; obtaining the corresponding sidewall angles based on the simulated bottom and top surface dimensions of the mask layer and the design thickness; determining a size-angle reference data set corresponding to each edge segment based on the simulated bottom surface dimensions of the mask layer; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle... The changes in the post-lithographic wafer pattern size caused by the optical proximity effect induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle are adjusted individually. The sidewall angle of each edge segment is subtracted from the corresponding reference angle to obtain the angle offset. Based on the angle offset, a target size offset is determined in the corresponding size-angle comparison data set. In the edge segment where the size of the simulated pattern at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the changes in the post-lithographic wafer pattern size caused by adjusting the size of the simulated pattern at the bottom of the mask layer by the target size offset can compensate for the changes in the post-lithographic wafer pattern size caused by adjusting the reference angle by the angle offset. Based on the target size offset, the position of the corresponding edge segment in the simulated pattern at the bottom of the mask layer is adjusted to obtain the updated simulated pattern at the bottom of the mask layer. In the increasingly smaller photolithography processes, the thickness of the mask layer can no longer be ignored compared to the wavelength of the light source. The three-dimensional morphology of the mask layer has a significant impact on the critical dimensions of the wafer after photolithography. In this invention, after simulating the top and bottom cross-sections of the mask layer using a model, the sidewall angles corresponding to each simulated edge segment are further calculated, and the angular offset between each sidewall angle and the preset reference angle is calculated. An offset between the sidewall angle and the reference angle means that the wafer pattern obtained after photolithography will also undergo unexpected dimensional changes. This part of the wafer pattern size change after photolithography due to the change in sidewall angle is compensated by adjusting the size of the simulated pattern at the bottom of the mask layer in this invention. This greatly reduces the impact of the error caused by the sidewall angle on the wafer pattern size after photolithography, improves the overall accuracy of mask process correction, and greatly enhances the similarity between the wafer pattern obtained by photolithography using the mask layer corrected by this invention and the photolithographic target pattern.

[0199] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the mask process correction methods described above. The mask process correction method provided by this invention involves: receiving a target mask pattern and its corresponding design thickness; inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulated electron beam exposure pattern; determining, through the mask top and bottom surface process correction model, the dimensions of the simulated bottom and top patterns of the mask layer corresponding to each edge segment in the simulated electron beam exposure pattern; obtaining the corresponding sidewall angles based on the simulated bottom and top patterns of the mask layer and the design thickness; determining a size-angle reference data set corresponding to each edge segment based on the simulated bottom pattern size of the mask layer; the size-angle reference data set includes the corresponding reference pattern size, reference angle, and, based on the reference pattern size and the reference angle... The changes in the post-lithographic wafer pattern size caused by the optical proximity effect induced by the size of the simulated pattern at the bottom of the mask layer and the sidewall angle are adjusted individually. The sidewall angle of each edge segment is subtracted from the corresponding reference angle to obtain the angle offset. Based on the angle offset, a target size offset is determined in the corresponding size-angle comparison data set. In the edge segment where the size of the simulated pattern at the bottom of the mask layer is the reference pattern size and the sidewall angle is the reference angle, the changes in the post-lithographic wafer pattern size caused by adjusting the size of the simulated pattern at the bottom of the mask layer by the target size offset can compensate for the changes in the post-lithographic wafer pattern size caused by adjusting the reference angle by the angle offset. Based on the target size offset, the position of the corresponding edge segment in the simulated pattern at the bottom of the mask layer is adjusted to obtain the updated simulated pattern at the bottom of the mask layer. In the increasingly smaller photolithography processes, the thickness of the mask layer can no longer be ignored compared to the wavelength of the light source. The three-dimensional morphology of the mask layer has a significant impact on the critical dimensions of the wafer after photolithography. In this invention, after simulating the top and bottom cross-sections of the mask layer using a model, the sidewall angles corresponding to each simulated edge segment are further calculated, and the angular offset between each sidewall angle and the preset reference angle is calculated. An offset between the sidewall angle and the reference angle means that the wafer pattern obtained after photolithography will also undergo unexpected dimensional changes. This part of the wafer pattern size change after photolithography due to the change in sidewall angle is compensated by adjusting the size of the simulated pattern at the bottom of the mask layer in this invention. This greatly reduces the impact of the error caused by the sidewall angle on the wafer pattern size after photolithography, improves the overall accuracy of mask process correction, and greatly enhances the similarity between the wafer pattern obtained by photolithography using the mask layer corrected by this invention and the photolithographic target pattern.

[0200] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0201] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0202] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0203] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0204] The mask process correction method, apparatus, equipment, and storage medium provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A mask process correction method, characterized by, The method comprises the following steps: receiving a target mask pattern and a corresponding design thickness; inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top-bottom process correction model to obtain a simulated electron beam exposure pattern through iteration; determining, by the mask top-bottom process correction model, a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge segment in the simulated electron beam exposure pattern; obtaining a corresponding sidewall included angle according to the mask layer bottom simulation pattern size, the mask layer top simulation pattern size and the design thickness; determining a size-included angle comparison data set corresponding to each edge segment according to the mask layer bottom simulation pattern size; the size-included angle comparison data set comprises a unique reference pattern size and a reference included angle, and records a corresponding post-lithography wafer pattern size change in an optical proximity effect simulation caused by an individual adjustment of the mask layer bottom simulation pattern size and the sidewall included angle on the basis that the mask layer bottom simulation pattern size is the reference pattern size and the sidewall included angle is the reference included angle; the mask layer bottom simulation pattern size of the edge segment is the same as the reference pattern size of the corresponding size-included angle comparison data set; obtaining an included angle offset by subtracting the corresponding reference included angle from the sidewall included angle of each edge segment; determining a target size offset in the corresponding size-included angle comparison data set according to the included angle offset; in the edge segment in which the mask layer bottom simulation pattern size is the reference pattern size and the sidewall included angle is the reference included angle, a post-lithography wafer pattern size change caused by an adjustment of the mask layer bottom simulation pattern size by the target size offset can compensate for a post-lithography wafer pattern size change caused by an adjustment of the reference included angle by the included angle offset; adjusting the position of the corresponding edge segment in the mask layer bottom simulation pattern according to the target size offset to obtain a mask layer bottom simulation updated pattern.

2. The mask process correction method of claim 1, wherein, The method for obtaining the mask top-bottom process correction model comprises the following steps: obtaining a modeling pattern set; the modeling pattern set comprises a plurality of modeling sample patterns; running a mask manufacturing process according to the modeling pattern set to obtain a process production pattern of each modeling sample pattern; scanning the process production pattern by using a scanning electron microscope to obtain a production scanning image corresponding to each process production pattern; determining a top pattern contour and a bottom pattern contour of the production scanning image according to local maxima of an image gradient of the production scanning image; Calibrating a first linear coefficient, a bottom etching model term and a second linear coefficient corresponding to the bottom etching model term, a top etching model term and a third linear coefficient corresponding to the top etching model term in a mask process model to be trained by using the modeling sample pattern, the bottom pattern profile and the top pattern profile, to obtain a mask top-bottom surface process correction model; wherein the mask process model to be trained can obtain a corresponding electron beam energy distribution from the modeling sample pattern through the first linear coefficient; and can determine a corresponding training bottom pattern profile according to the electron beam energy distribution, the bottom etching model term and the second linear coefficient, and can determine a corresponding training top pattern profile according to the electron beam energy distribution, the top etching model term and the third linear coefficient.

3. The mask process correction method of claim 2, wherein, The mask process model to be trained obtains corresponding training bottom pattern profiles and training top pattern profiles from the modeling sample pattern through the following three formulas: ； ； ； where EB(x, y) represents an electron beam energy distribution at (x, y), M(x, y) represents a rasterized modeled sample pattern at (x, y), G i is the i-th Gaussian function term, represents a convolution operation, b i is the first linear coefficient corresponding to the i-th Gaussian function term; ET b (x,y) represents a training bottom pattern profile at (x,y), D j is the jth bottom etch model term calculated based on EB(x,y), c j is the corresponding second linear coefficient, T b is a bottom etch image threshold, using T b truncates ET b (x,y) to obtain a training bottom pattern profile; ET t (x,y) represents the training top pattern profile at (x,y), D k is the kth top etch model term calculated based on EB(x,y), c k is the corresponding third linear coefficient, T t is the top etch image threshold, using T t truncates ET t (x,y) and the training top pattern profile is obtained.

4. The mask process correction method of claim 2, wherein, The method for obtaining the size-angle contrast data set comprises: Obtaining mask manufacturing nominal patterns of multiple sizes and corresponding design thicknesses; Inputting the mask manufacturing nominal patterns into the mask top-bottom surface process correction model to obtain corresponding simulated bottom pattern profiles and simulated top pattern profiles; Inputting the simulated bottom pattern profiles and the simulated top pattern profiles into a pre-trained optical proximity correction model for simulation to obtain simulated lithography wafer reference sizes corresponding to the mask manufacturing nominal patterns; Determining corresponding simulated pattern sizes according to the simulated bottom pattern profiles, and taking the simulated pattern sizes as reference pattern sizes corresponding to the size-angle contrast data set; Determining reference angles corresponding to each reference pattern size according to the simulated bottom pattern profiles, the simulated top pattern profiles and the design thicknesses; Pre-setting multiple simulated angle offset amounts, keeping the simulated bottom pattern profiles unchanged, adjusting the reference angles according to the multiple simulated angle offset amounts in turn to obtain corresponding first simulated top pattern update profiles; Inputting the simulated bottom pattern profiles and the multiple first simulated top pattern update profiles into the optical proximity correction model for simulation to obtain first simulated lithography wafer pattern sizes corresponding to combinations of the simulated bottom pattern profiles and different first simulated top pattern update profiles; Differencing multiple first simulated lithography wafer pattern sizes from the simulated lithography wafer reference sizes to obtain first post-lithography wafer pattern size changes corresponding to each simulated angle offset amount; Pre-setting multiple simulated size offset amounts, keeping the reference angles unchanged, adjusting the reference pattern sizes according to the multiple simulated size offset amounts in turn to obtain second simulated top pattern update profiles and second simulated bottom pattern update profiles corresponding to each simulated size offset amount; Inputting the second simulated top pattern update profiles and the second simulated bottom pattern update profiles corresponding to the same simulated size offset amount into the optical proximity correction model for simulation to obtain a second simulated lithography wafer pattern size corresponding to the simulated size offset amount; Subtracting the second simulation lithography wafer pattern size from the simulation lithography wafer reference size, a second wafer pattern size change corresponding to each simulation size offset is obtained; In the same size-angle contrast data set, the second wafer pattern size change and the change direction of the first wafer pattern size change direction of the simulation angle offset are determined to be opposite, and the simulation size offset closest to the numerical value is the target size offset corresponding to the simulation angle offset.

5. The mask process correction method of claim 4, wherein, According to the simulation bottom pattern profile, the simulation top pattern profile and the design thickness, the reference angle corresponding to each reference pattern size is determined, including: In combination with the design thickness, the edge segment angle corresponding to each edge segment in the simulation bottom pattern profile and the simulation top pattern profile of each size of mask manufacturing nominal pattern is calculated; The edge segment angles corresponding to the same mask manufacturing nominal pattern are arranged in order of size, and the median value after arrangement is taken as the reference angle corresponding to the reference pattern size.

6. The mask process correction method of claim 1, wherein, The target mask pattern is input as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulation electron beam exposure pattern, including: The target mask pattern is input as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model, so that the mask top and bottom surface process correction model determines a corresponding mask layer bottom simulation pattern profile according to the initial electron beam exposure pattern, and then adjusts the position of the edge segment of the initial electron beam exposure pattern through the EPE between the mask layer bottom simulation pattern profile and the target mask pattern. After multiple iterations, a simulation electron beam exposure pattern is obtained, and the EPE between the mask layer bottom simulation pattern profile corresponding to the simulation electron beam exposure pattern and the target mask pattern is less than a preset qualified threshold.

7. The mask process correction method of claim 1, wherein, In the edge segment where the mask layer bottom simulation pattern size is the reference pattern size and the side wall angle is the reference angle, the wafer pattern size change caused by adjusting the mask layer bottom simulation pattern size by the target size offset is opposite in change direction to the wafer pattern size change caused by adjusting the reference angle by the angle offset, and the numerical value is the same.

8. A mask process correction device, characterized by, Including: The receiving module is configured to receive a target mask pattern and a corresponding design thickness; The first correction module is configured to input the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model to iteratively obtain a simulation electron beam exposure pattern; The top and bottom simulation module is configured to determine a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge segment in the simulation electron beam exposure pattern through the mask top and bottom surface process correction model; The angle calculation module is configured to obtain a corresponding side wall angle according to the mask layer bottom simulation pattern size, the mask layer top simulation pattern size and the design thickness. a top-bottom simulation module, configured to determine a size-angle comparison data set corresponding to each of the edge sections according to the bottom simulation pattern size of the mask layer, wherein the size-angle comparison data set comprises a unique reference pattern size and a reference angle, and records a corresponding post-lithography wafer pattern size change caused by an optical proximity effect simulation of an individual adjustment of the bottom simulation pattern size of the mask layer and the side wall angle of the edge section, on the basis of the bottom simulation pattern size of the mask layer being the reference pattern size and the side wall angle being the reference angle; an angle difference module, configured to obtain an angle offset by subtracting the reference angle from the side wall angle of each of the edge sections; an offset calculation module, configured to determine a target size offset in the size-angle comparison data set corresponding to each of the edge sections according to the angle offset, wherein a post-lithography wafer pattern size change caused by an adjustment of the bottom simulation pattern size of the mask layer by the target size offset in the edge section with the bottom simulation pattern size of the mask layer being the reference pattern size and the side wall angle being the reference angle can compensate for a post-lithography wafer pattern size change caused by an adjustment of the reference angle by the angle offset; a second correction module, configured to obtain an updated bottom simulation pattern of the mask layer by adjusting a position of each of the edge sections in the bottom simulation pattern of the mask layer according to the target size offset.

9. A mask process correction apparatus, characterized by, comprise: a memory, configured to store a computer program; a processor, configured to execute the computer program to implement the steps of the mask process correction method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium and is executed by the processor to implement the steps of the mask process correction method according to any one of claims 1 to 7.

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