Method of manufacturing a semiconductor device and corresponding semiconductor device
By directly exposing the die surface in semiconductor devices using laser direct structuring technology, a conductive structure is formed and an electroplated metallization layer is formed on the back side. This solves the thermal performance bottleneck and cracking problems caused by packaging grinding in traditional packaging, achieving efficient heat dissipation and improved reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STMICROELECTRONICS SRL
- Filing Date
- 2022-06-08
- Publication Date
- 2026-06-23
AI Technical Summary
In high-heat-dissipation semiconductor devices, in traditional upward heat dissipation packaging configurations, the die attachment material between the back metallization of the semiconductor chip and the heat sink becomes a bottleneck in thermal performance, and the packaging and polishing process can easily lead to die cracks.
Laser direct structuring (LDS) technology is used to directly expose the die surface in the packaging design. A conductive structure is formed by laser beam processing, eliminating thermal interface materials and achieving high heat dissipation capacity. An electroplated metallization layer is formed on the back of the die to promote heat transfer.
It improves the heat dissipation capability of the package, avoids thermal failure, enhances device performance and reliability, reduces operating temperature, and achieves a small and compact package profile.
Smart Images
Figure CN115458415B_ABST
Abstract
Description
[0001] Cross-reference to related applications
[0002] This application claims priority to Italian patent application No. 102021000014906, filed on 8 June 2021, the contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field
[0003] This specification relates to the manufacture of semiconductor devices.
[0004] One or more embodiments may be applied to semiconductor devices in which high heat dissipation is a desired feature. Background Technology
[0005] In semiconductor devices where high heat dissipation is a desirable feature, a so-called "slug-up" configuration is currently used, such as a top-mounted quad flat no-lead or QFN package, which has a heat extractor (heat sink or heat fin) mounted on top of an exposed heat slug at the top of the package.
[0006] A common problem with this configuration is the die attachment material between the back metallization (BSM) of the semiconductor chip or die and the heatsink in the device.
[0007] This interface material may be a bottleneck in terms of heat dissipation.
[0008] One approach proposed to address this problem involves grinding an insulating package (molding) to expose the back side of a semiconductor chip or die. However, this method has been found to cause undesirable cracking, primarily when the semiconductor chip or die is significantly thinned due to grinding.
[0009] The field needs to contribute to solving these problems. Summary of the Invention
[0010] One or more embodiments relate to a method.
[0011] One or more embodiments relate to corresponding semiconductor devices.
[0012] One or more embodiments provide a semiconductor chip package design using laser direct structuring (LDS) technology, which has the ability to achieve high heat dissipation at the top of the package due to direct exposure of the die surface.
[0013] In one or more embodiments, the most critical thermal interface (for die attachment material) is virtually eliminated.
[0014] One or more embodiments can provide a small, compact package profile, which facilitates “tuning” from a simple leadframe design.
[0015] One or more embodiments may demonstrate a fully plated package top surface, in which the presence of an exposed die back can be identified. Attached Figure Description
[0016] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:
[0017] Figures 1 to 7 Examples of various steps in the embodiments of this specification, and
[0018] Figure 8 and Figure 9 This is a cross-sectional view of a possible mounting arrangement of a semiconductor device manufactured according to one or more embodiments of this specification. Detailed Implementation
[0019] The numbers and symbols corresponding to different figures generally refer to the corresponding parts, unless otherwise stated. These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the range of that feature.
[0020] In the following description, various specific details are shown to provide a thorough understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in such a way that various aspects of the embodiments are not obscured.
[0021] References to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., which may appear at various points in this specification, do not necessarily refer precisely to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.
[0022] The headings / references used herein are provided for convenience only and do not define the scope of protection or the scope of embodiments.
[0023] In this specification, laser direct structuring (LDS) will be used to refer to laser-based techniques currently used to manufacture semiconductor devices, in which conductive structures such as lines and vias can be formed in an insulating molding compound by activation or “structuring” (possibly followed by electroplating) with a laser beam.
[0024] For example, laser direct structuring (LDS) technology (also commonly referred to as direct copper interconnect (DCI) technology) is discussed in documents such as U.S. Patent Application Publication Nos. 2018 / 0342453, 2020 / 0203264, 2020 / 0321274, 2021 / 0050226, or 2021 / 0050299, all of which are incorporated herein by reference and assigned to the same assignee of this application.
[0025] Understanding and predicting thermal performance is useful before integrating semiconductor devices onto substrates such as printed circuit boards (PCBs) so that the devices can operate within defined temperature limits.
[0026] When a semiconductor device is in operation, the electrical energy it absorbs is converted into heat.
[0027] Adequate heat dissipation from the surface of a semiconductor chip or die to its immediate surrounding environment contributes to the efficient and reliable operation of semiconductor devices.
[0028] This is especially true for power packages integrated on a substrate, such as printed circuit boards (PCBs), where high currents are generated that produce heat during device operation.
[0029] By improving the heat dissipation capability of the package and avoiding thermal failure, device performance and reliability are improved.
[0030] In conventional devices, including semiconductor chips or dies attached to die pads, the thermal resistance at the interface between the die and the die-attachment material plays a crucial role in determining the device's thermal performance. To some extent, the thermal conductivity of the die-attachment material is essential for promoting the full performance of the device.
[0031] One approach proposed in the past to improve thermal performance involved using a so-called "upward heat dissipation" package, which has exposed pads on the front (top) side that facilitate the extraction of heat from the front or top surface of the semiconductor die using an external heat sink.
[0032] A somewhat similar approach involves encapsulating and grinding the die to expose the back of the die, thereby facilitating heat transfer to the heatsink.
[0033] Even setting aside other issues, it is worth noting that conventional upward heat dissipation packages cannot fully utilize the top surface for heat extraction, and the die attachment material is still found to be the bottleneck determining the thermal performance of the device.
[0034] Furthermore, the proposed encapsulation and polishing process has been found to cause die strength issues, which may lead to unwanted die cracks.
[0035] One or more embodiments may involve starting with a (planar) substrate 10 that can be substantially similar to a so-called “pre-molded” lead frame.
[0036] The term “leadframe” (or “lead frame”) is currently used (see, for example, the USPC Comprehensive Glossary) to refer to the metal frame that supports an integrated circuit chip or die, and the electrical leads that interconnect the integrated circuit in the die or chip to other electrical components or contacts.
[0037] Leadframes are typically created using techniques such as photolithography. This technique involves etching foils or tapes of metallic (e.g., copper) material onto the top and bottom sides to create various pads and leads.
[0038] Currently used pre-molded leadframes include electrically insulating resins, such as epoxy resin, which are molded onto an engraved (e.g., photolithographic) leadframe using a planar molding tool. The space left in the etched metal material is filled with the pre-molded resin, and the total thickness of the resulting leadframe is the same as the thickness of the original etched leadframe.
[0039] Basically, the substrate 10 shown in the figure can be considered as a pre-molded lead frame, wherein (only) conductive connecting rods 12 provide engraved (e.g., etched) conductive structures on which insulating materials such as LDS material 14 are molded.
[0040] Providing such a substrate 10 involves other conventional processes (e.g., using flat molding tools), which makes it unnecessary to provide a more detailed description here.
[0041] As described below, it is beneficial for the insulating material 14 between the connecting rods 12 to be LDS material, provided that electroplating can be applied to it.
[0042] Figure 2 It is an insulating film 16 layers pressed on Figure 1 An example of a structure on one (here, the front or top) surface.
[0043] For example, Ajinomoto stacked film (ABF) from Ajinomoto is an example of an insulating film that can be advantageously used in the arrangements discussed herein.
[0044] Figure 3 This is an example of a semiconductor chip or die 18 being placed on an insulating film 16, the semiconductor chip or die 18 being located on a molded compound portion 14 between connecting rods 12 of the structure shown in the foregoing figure.
[0045] like Figure 2As shown on the right (one of the dies 18 is reproduced at an enlarged scale), the dies 12 are placed on an inverted membrane 16, that is, their active regions 18A are located on the front or top surface of the die 12, facing downwards near the insulating membrane 16, and the back metallized BSN layer 18B of the die 18 faces upwards away from the insulating membrane 16.
[0046] Note that here Figures 1 to 7 This refers to the simultaneous production of multiple semiconductor devices, which are ultimately separated in the "monomerization" step (see [link to documentation]). Figure 7 ).
[0047] Figure 4 The encapsulation (cap) of LDS molding compound 20 is formed (in a manner known to those skilled in the art) into... Figure 3 The structural example allows device 18 to be embedded in package 20.
[0048] Figure 5 It is applied to Figure 4 An example of laser beam processing on both sides of a structure (usually denoted as LB).
[0049] This laser beam processing can be performed using laser beam sources currently used for dual-purpose LDS technology.
[0050] First, the laser beam treatment LB is applied to the LDS package or cap 20 to ablate the package or cap down to the level of the back metallization layer 18B of the semiconductor die 18, so that the metallization layer 18B is exposed on the (ablated) surface of the LDS package or cap 20.
[0051] Secondly, laser beam processing of LB results in vias through the LDS material in portion 14 of substrate 10 and in the LDS package or cap 20.
[0052] Specifically: a first via 140 is constructed (drilled) together with a pattern of line 142 on the outer (here, lower) surface of the substrate 10, the first via 140 extending from the outer (here, lower) surface of portion 14 of the substrate 10 to the active region 18A of the die 18; a second via 200 is constructed (drilled) extending downward from the outer (here, upper) surface of the package or cover 20 to the connecting rod 12 in the substrate 10.
[0053] As shown in the figure, vias 140 and 200 both extend through the insulating layer 16.
[0054] Figure 6 This is an example of an electroplating process applied to vias 140 and 200 (as is otherwise conventional in the art), vias 140 and 200 being previously bonded. Figure 5 The structure is constructed based on the applied laser beam energy LB discussed.
[0055] First, the purpose of this electroplating is to promote conductivity of vias 140 and 200.
[0056] Second, regarding the via 140 provided through the substrate 10, the purpose of electroplating is to create a pattern of conductive lines 142 on the outer (here, lower) surface of the substrate 10, which in turn cooperate with the via 140 to provide electrical connection for the active region 18A of the die 18; for the LDS molded compound package or cap 20, electroplating is performed in such a way as to form a back metallization layer 220 extending on the (entire) outer (here, upper) surface of the package or cap 20.
[0057] The conductive path provided by the via 200 and the connecting rod 12 in the substrate 10 facilitates the electroplating of the metallization layer 220.
[0058] In one or more embodiments, the metallization layer 220 is further facilitated by providing a pre-molded lead frame substrate 10, wherein the connecting rods 12 form a mesh pattern, such as a rectangular mesh pattern, that electrically connects the conductive material regions 12.
[0059] like Figure 6 The structure shown can then be used as follows Figure 7 The illustrated saw blade B is individualized, thereby providing a separate semiconductor device 100.
[0060] Then, devices such as 100 can be arranged (in a manner known to those skilled in the art) on a support substrate S such as a printed circuit board or PCB, as Figure 8 and Figure 9 As shown, the conductive line 142 faces the substrate S and provides the required electrical connection wiring pattern for the semiconductor die or multiple dies 18.
[0061] The external heat extractor (heat sink) HE can be coupled (e.g., soldered at solder layer 222) to the (metal) plating layer 220 formed on the exposed back metallization 18b of the die or multiple dies 18 via a heat transfer relationship.
[0062] Figure 8 An arrangement is shown as an example, in which each individual thermal extractor HE is coupled to a single device 100.
[0063] Figure 9 Again, the arrangement in which the thermal extractor HE is coupled to multiple (e.g., two) devices 100 is illustrated by way of example.
[0064] Figure 7This is an example of a blade B used to cut a layered substrate 10 in a region 12 of conductive material. The layered substrate 10 has a plurality of semiconductor chips 18 disposed thereon, an LDS material package 20 is formed on the layered substrate 10, and a laser direct structuring process LB is applied thereon for processing.
[0065] like Figure 7 As shown, cutting (single-cutting) at region 12 removes region 12 and (second) vias 200 extending through the LDS material package 20, and produces a plurality of single-cut semiconductor devices 100, each semiconductor device 100 including a corresponding portion of thermally conductive layer 220.
[0066] therefore, Figure 8 This is an example of coupling the heat extractor body HE of the heat-conducting material with the heat-conducting layer 220 (such a corresponding part) in a heat transfer relationship.
[0067] on the contrary, Figure 9 This is an example of coupling a heat extractor body HE of a single (common) thermally conductive material to corresponding portions of the thermally conductive layers 220 in two (or more) semiconductor devices 100 in a thermal transfer relationship.
[0068] For example, to improve heat dissipation by promoting convection flow, methods such as... Figure 9 The thermal extractor shared by the multiple devices 100 shown may be beneficial.
[0069] A back metallization layer, such as layer 220, is plated on the exposed back metallization 18B of the die or multiple dies 18, which helps to dissipate heat to the heat extractor 104 by avoiding conventional die attachment materials and provides effective heat dissipation across the entire surface of the package.
[0070] Because traditional lead frames are no longer used, the resulting profile is small and compact.
[0071] Simulation experiments have shown that the arrangement disclosed herein can provide a significant reduction (e.g., -27%) in the temperature reached during operation in power semiconductor devices.
[0072] Without prejudice to the fundamental principles, details and embodiments may be changed, even significantly changed, by way of example only, relative to what is described herein without departing from the scope of protection.
[0073] The claims are an integral part of the technical teachings provided herein regarding the embodiments.
[0074] The scope of protection is determined by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, comprising: A layered substrate is provided, wherein the layered substrate has alternating regions of conductive material and laser-directly structured LDS material; A semiconductor chip is disposed on a region of LDS material in the layered substrate, the semiconductor chip having a front active region facing the layered substrate and a metallized post-surface facing away from the layered substrate; An LDS material package is formed on the layered substrate to encapsulate the semiconductor chip, wherein the LDS material package has an outer surface facing away from the layered substrate, and wherein the metallized surface of the semiconductor chip is exposed at the outer surface. Laser direct structuring is applied to the region of LDS material in the layered substrate to provide a first conductive line toward the front active region of the semiconductor chip, the first conductive line including at least one first via extending through the region of LDS material in the layered substrate to the front active region of the semiconductor chip; as well as Laser direct structuring is applied to the LDS material package to provide at least one second via extending through the LDS material package to a region of conductive material in the layered substrate and a thermally conductive layer plated on the outer surface of the LDS material package, wherein the thermally conductive layer extends above the metallized surface of the semiconductor chip exposed on the outer surface of the LDS material package.
2. The method of claim 1, further comprising removing the at least one second via extending through the LDS material of the package and the region of the conductive material in the layered substrate.
3. The method according to claim 1 further includes coupling the thermal extractor body of the thermally conductive material to the thermally conductive layer in a heat transfer relationship.
4. The method of claim 1, further comprising laminating an insulating layer onto the layered substrate before arranging the semiconductor chip on the layered substrate, wherein the insulating layer is located between the layered substrate and the active region of the semiconductor chip.
5. The method of claim 1, wherein forming the package of LDS material on the layered substrate to encapsulate the semiconductor chip comprises: LDS material is applied to the layered substrate on which the semiconductor chip is disposed, wherein the semiconductor chip is embedded in the LDS material; as well as The LDS material applied to the layered substrate is partially removed to provide the outer surface of the LDS material package, whereby the metallized surface of the semiconductor chip is exposed at the outer surface of the LDS material package.
6. The method of claim 1, wherein the first conductive line toward the front active region of the semiconductor chip comprises a conductive line extending on the surface of the layered substrate opposite to the semiconductor chip.
7. A method for manufacturing a semiconductor device, comprising: A layered substrate is provided, wherein the layered substrate has alternating regions of conductive material and laser-directly structured LDS material; Multiple semiconductor chips are arranged on corresponding multiple regions of LDS material in the layered substrate, each semiconductor chip having a front active region facing the layered substrate and a metallized post-surface facing away from the layered substrate; An LDS material package is formed on the layered substrate to encapsulate the plurality of semiconductor chips, wherein the LDS material package has an outer surface facing away from the layered substrate, and wherein the metallized surface of each of the plurality of semiconductor chips is exposed at the outer surface. Laser direct structuring is applied to the region of LDS material in the layered substrate to provide a first conductive line toward the front active region of each of the plurality of semiconductor chips, the first conductive line including a plurality of first vias extending through the region of LDS material in the layered substrate to the front active region of the plurality of semiconductor chips; Laser direct structuring is applied to the LDS material package to provide a plurality of second vias extending through the LDS material package to a region of conductive material in the layered substrate and a thermally conductive layer plated on the outer surface of the LDS material package, wherein the thermally conductive layer extends above the metallized surfaces of the plurality of semiconductor chips exposed on the outer surface of the LDS material package. as well as The package is cut through the layered substrate and the LDS material formed on the layered substrate at the region of the conductive material, wherein the cut removes the plurality of second vias extending through the LDS material of the package and produces a plurality of individual semiconductor devices, each individual semiconductor device including a corresponding portion of the thermally conductive layer.
8. The method of claim 7 further comprises coupling the thermal extractor body of the thermally conductive material to the corresponding portion of the thermally conductive layer in a heat transfer relationship.
9. The method of claim 7, further comprising coupling a single thermal extractor body of thermally conductive material to a plurality of corresponding portions of the thermally conductive layer in at least two of the plurality of individualized semiconductor devices in a thermal transfer relationship.
10. The method of claim 7, further comprising laminating an insulating layer onto the layered substrate prior to arranging the plurality of semiconductor chips on the layered substrate, wherein the insulating layer is located between the layered substrate and the active region of each semiconductor chip.
11. The method of claim 7, wherein forming the package of LDS material on the layered substrate to encapsulate the plurality of semiconductor chips comprises: LDS material is applied to the layered substrate on which the plurality of semiconductor chips are disposed, wherein the plurality of semiconductor chips are embedded in the LDS material applied to the layered substrate; as well as Partial removal of the LDS material applied to the layered substrate is used to provide the outer surface of the LDS material package, whereby the metallized surfaces of the plurality of semiconductor chips are exposed at the outer surface of the LDS material package.
12. The method of claim 7, wherein the first conductive line toward the front active region of at least one of the semiconductor chips comprises a conductive line extending on the surface of the layered substrate opposite to the plurality of semiconductor chips.
13. A semiconductor device, comprising: Layered substrate, including regions of laser-directly structured LDS material; A semiconductor chip is disposed on the region of LDS material, the semiconductor chip having a front active region facing the layered substrate and a metallized post-surface facing away from the layered substrate; An LDS material package is placed on the layered substrate and encapsulates the semiconductor chip, wherein the LDS material package has an outer surface facing away from the layered substrate, and the metallized surface of the semiconductor chip is exposed at the outer surface of the LDS material package. A first conductive line is directed toward the front active region of the semiconductor chip. The first conductive line is constructed in the region of the LDS material. The first conductive line includes a first via extending through the region of the LDS material to the front active region of the semiconductor chip. as well as A thermally conductive layer is deposited on the outer surface of the package made of LDS material, and the thermally conductive layer extends on the metallized surface of the semiconductor chip exposed on the outer surface of the package made of LDS material. The layered substrate further includes a region of conductive material adjacent to the region of LDS material, and also includes a second via extending through the package of LDS material between the thermally conductive layer and the region of conductive material in the layered substrate.
14. The device according to claim 13 further includes a heat extractor body made of a thermally conductive material, the heat extractor body being coupled to the thermally conductive layer in a heat transfer relationship.
15. The device of claim 13, further comprising an insulating layer located between the layered substrate and the active region of the semiconductor chip.