Region of interest localization for laser-assisted bonding

Abstract

The present disclosure relates to region of interest positioning for laser assisted bonding. A semiconductor device is formed by providing a semiconductor die. A laser assisted bonding (LAB) assembly is disposed on the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify a corner of the semiconductor die. A region of interest (ROI) is identified in the image relative to the corner of the semiconductor die. Parameters may be used to control the size of the ROI and the position of the ROI relative to the corresponding corner. While performing LAB, the ROI is monitored for temperature using the IR camera.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and, more particularly, to methods and devices for locating regions of interest during laser assisted bonding. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and producing visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for a smaller end product. Smaller semiconductor die sizes can be achieved through improvements in front-end processes, resulting in semiconductor dies with smaller, higher density active and passive components. Back-end processes can produce semiconductor device packages with smaller footprints through improvements in electrical interconnects and packaging materials.

[0004] As semiconductor devices decrease in size, many aspects of the manufacturing process become problematic and must be improved or replaced. Semiconductor dies are typically mounted to a substrate by placing solder bumps of the semiconductor die in contact with contact pads of the substrate. The assembly is heated in an oven to reflow the solder bumps, thereby attaching the semiconductor die to the substrate.

[0005] As semiconductor dies and the accompanying interconnect structures are made smaller and thinner, the effects of the reflow oven process are more damaging to electrical components. Laser assisted bonding (LAB) has been adopted as an improved solution. LAB uses a laser to apply energy directly to the back side of the die being mounted, which is converted into thermal energy to reflow the solder bumps on the front side of the die. LAB provides more localized heat than a reflow oven and is able to reflow the bumps with a shorter cycle time. The result is that LAB can be used to mount the die to the substrate with a reduced likelihood of damaging the thin die and interconnect layers.

[0006] An important aspect of LAB is the use of an infrared (IR) camera to monitor the temperature of the die in real time. The temperature is monitored in a specific area of ​​the die called the region of interest (ROI). Currently, the IR camera is manually positioned by an engineer, and then specific pixels on the IR camera are monitored as the ROI to maintain an acceptable temperature. Manual IR camera placement is subject to human error that can cause the ROI position to be misplaced. Reliably replicating the ROI positioning is difficult. Therefore, there is a need for an improved method and system for aligning an IR camera to the region of interest during laser assisted bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1a-1c A semiconductor wafer having a plurality of semiconductor dies separated by dicing streets is shown;

[0008] Figure 2a-2h Region of interest (ROI) alignment is shown;

[0009] Figure 3a-3e Automatic ROI alignment is shown;

[0010] Figure 4a-4c An example of ROI alignment is shown;

[0011] Figure 5a-5c Another ROI alignment example is shown;

[0012] Figure 6a-6c shows the completion of the semiconductor package after laser assisted bonding; and

[0013] Figure 7 An electronic device with a laser assisted bonding device is shown. DETAILED DESCRIPTION

[0014] In the following description, the present invention is described in one or more embodiments with reference to the accompanying drawings, in which like numbers represent the same or similar elements. Although the present invention is described according to the best mode for carrying out the purposes of the present invention, it will be understood by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents supported by the following disclosure and drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0015] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current required to perform the circuit function.

[0016] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnection and environmental protection. In order to singulate the semiconductor die, the wafer is scribed and disconnected along the non-functional area of ​​the wafer called the cut or scribing. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die is mounted to a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contacts within the package. Electrical connections can be made with conductive layers, bumps, columnar bumps, conductive pastes, bonding wires or other suitable interconnect structures. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device can be used for other system components.

[0017] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by passive, inter-die wafer regions or streets 106. The streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0018] Figure 1bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or passive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits may include: one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), power amplifiers, application specific integrated circuits (ASICs), memory, or other signal processing circuits. Semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0019] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, chemical plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0020] Conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, chemical plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, a combination thereof, or other suitable conductive material with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, the bump 114 is formed on an under-bump metallization layer (UBM) having a wetting layer, a barrier layer and an adhesion layer. The bump 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bump 114 represents a type of interconnect structure that can be formed on the conductive layer 112. The interconnect structure can also use bonding wires, conductive pastes, pillar bumps, micro bumps or other electrical interconnects.

[0021] exist Figure 1c In the process, semiconductor wafer 100 is singulated through scribe lines 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested to identify known good dies (KGDs) after singulation.

[0022] To incorporate semiconductor die 104 into an electronic device, bumps 114 are typically reflowed onto contact pads 124 of a larger substrate 120, such as Figure 2aAs shown. The semiconductor die 104 is placed at a desired location on the substrate 120 using a pick and place machine, and then the bumps 114 are reflowed onto the contact pads 124 using laser assisted bonding (LAB). Flux is optionally added to the bumps 114 to improve the reflow of the solder material onto the surface of the contact pads 124. Non-conductive pastes, non-conductive films, anisotropic conductive pastes, and other suitable materials may be used instead of flux 126.

[0023] Figure 2a A partial cross-sectional view of a carrier 122 with a substrate 120 disposed thereon is shown. The carrier 122 is a flat sheet of organic material, glass, silicon, polymer, or any other material suitable for providing physical support for the substrate 120 during the manufacturing process. An optional double-sided tape, thermal release layer, UV release layer, or other suitable interface layer may be disposed between the carrier 122 and the substrate 120.

[0024] The substrate 120 is formed of a base insulating material, wherein a conductive layer 124 is formed on the top and bottom surfaces of the interposer and interlaced between layers of insulating material. The conductive layer 124 includes: contact pads, conductive traces, and conductive vias, which are configured to achieve desired signal routing as needed. Portions of the conductive layer 124 are electrically shared or electrically isolated, depending on the design and function of the device formed. The conductive layer 124 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. In some embodiments, a passivation or solder mask is formed on the top and bottom surfaces of the substrate 120, which has an opening to expose the contact pads of the conductive layer 124.

[0025] Substrate 120 may also be any suitable laminate interposer, PCB, wafer form, strip interposer, lead frame or other type of substrate. Substrate 120 may include one or more laminate layers of pre-impregnated (pre-impregnated) polytetrafluoroethylene (PTFE), FR-4, FR-1, CEM-1 or CEM-3 in combination with phenolic cotton paper, epoxy resin, resin, glass fabric, matte glass, polyester and other reinforcing fibers or fabrics. The insulating material of substrate 120 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials with similar insulating and structural properties. Substrate 120 may also be a multi-layer flexible laminate, ceramic, copper-clad laminate, glass or semiconductor wafer, which includes an active surface including one or more transistors, diodes and other circuit elements to implement analog or digital circuits. The substrate 120 may be any suitable substrate for semiconductor packaging or electronic devices.

[0026] In laser assisted bonding, LAB assembly 130 is disposed on semiconductor die 104, where the semiconductor die is located on substrate 120. LAB assembly 130 is mounted on a stage that allows the XY position of the LAB assembly to be controlled. XY position means that the position can be controlled along the X and Y axes but not necessarily along the Z axis. The XY plane is oriented parallel to the major surface of substrate 120. The X axis is Figure 2a The y-axis extends from left to right, while the y-axis extends into and out of Figure 2a The axis of the page. The Z axis is Figure 2a oriented up and down, perpendicular to the major surface of substrate 120. If desired, in some embodiments, the frame to which LAB assembly 130 is attached can allow for Z-axis (vertical) movement.

[0027] The LAB assembly 130 includes a laser homogenizer 132. The homogenizer 132 receives a laser beam input via a fiber optic cable, a waveguide, or other suitable mechanism, and outputs a homogenized laser beam 134 on the semiconductor die 104. A beam homogenizer is a device that eliminates irregularities in the laser beam profile and produces a more uniform profile. Most beam homogenizers use a multi-faceted mirror with square facets. The mirror reflects light at different angles to produce a beam with substantially uniform power across the entire profile of the beam 134.

[0028] The energy of the beam 134 is absorbed by the semiconductor die 104 and converted into heat energy to reflow the bumps 114. In some embodiments, the back surface 108 includes a conductive layer formed on the semiconductor die 104 as an electromagnetic interference (EMI) shielding layer. The conductive layer also improves the conversion efficiency from laser energy to heat energy during LAB. The back surface 108 may also have other types of laser absorption layers formed of any material that increases the absorption of the laser energy.

[0029] Multiple substrates 120 and semiconductor dies 104 are placed on a carrier 122 at the same time, and the LAB assembly 130 is moved by the stage to perform LAB on each die one at a time. After processing one semiconductor die 104, a vision camera 138 is used to align the LAB assembly 130 on the next die by finding a fiducial mark on the substrate 120 or by identifying the corner of the die. The stage moves the LAB assembly 130 until the laser homogenizer 132 is aligned with the next semiconductor die 104 as reported by the vision camera 138.

[0030] An infrared (IR) camera 136 is attached to the LAB assembly 130 and is located outside the side of the laser homogenizer 132. Due to the positioning of the IR camera 136, the IR camera typically needs to be tilted at an angle θ to properly view the die 104. The angle θ is typically about 70 degrees, but can vary. The IR camera 136 provides a thermal image of the semiconductor die 104 during the LAB process. The thermal image is used to monitor the temperature of the semiconductor die 104 in real time while performing the LAB.

[0031] Figure 2b A number of regions of interest (ROIs) 150 are shown where the temperature is monitored. Five ROIs 150 are typically used: one ROI 150a at the center of the die 104 and ROIs 150b-150e at each of the four corners. Figure 2c and 2d Details of ROI 150 are shown. Figure 2c ROI 150b in is formed to be a distance 152 from a corner 153b of semiconductor die 104 along the X-axis and a distance 154 from the corner along the Y-axis. Each corner ROI 150b-150e is positioned at the same distance (152, 154) from the corresponding corner 153b-153e, so that only two distance parameters need to be configured. In other embodiments, ROIs 150b-150e can be positioned independently.

[0032] like Figure 2d As shown, ROI 150a at the center of die 104 is positioned equidistant between each pair of opposing sides of the die. ROI 150a is positioned the same distance 162 from each corner 153b-153e along the X-axis and the same distance 164 from each corner along the Y-direction. ROI 150a is centered on die 104.

[0033] Each ROI 150a-150e is typically the same size, i.e., size 156 along the X-axis and size 158 along the Y-axis. If sizes 156 and 158 are different, ROI 150 is a rectangle. If size 156 is equal to size 158, ROI 150 is a square. In other embodiments, ROIs 150 are shaped differently from one another or irregularly.

[0034] Distances 152, 154, 162, and 164 and sizes 156 and 158 are all measured in numbers of pixels on the image captured by IR camera 136. The goal during LAB is to monitor the temperature at a fixed pixel of IR camera 136 relative to the corner of semiconductor die 104. Due to the reality that manufacturing equipment has moving mechanical parts, during the manufacturing process, IR camera 136 may move slightly relative to the rest of LAB assembly 130. If IR camera 136 is moved slightly, the pixel of IR camera 136 being monitored will no longer be in the correct position relative to the corner of semiconductor die 104.

[0035] Figure 2e and 2f This misplacement of ROI 150 is shown. An exemplary image from IR camera 136 is superimposed onto substrate 120. ROI 150a is placed in area 170 of the IR camera's view, while ROIs 150b-150e are appropriately placed in the image to be the desired number of pixels from the corner of die 104. Figure 2e , region 170, and therefore ROI 150a, is aligned with the center of semiconductor die 104. Due to the alignment, ROIs 150b-150e are each equidistant from their respective corners 153 as expected.

[0036] Figure 2f 1 shows misalignment that can be caused by a variety of factors. The most common is a bad machine switch between different ROI locations when different devices are working, or a change in camera tilt during movement that results in an angular offset 172. Angular offset 172 can easily occur when moving LAB assembly 130 between units on carrier 122 or when loading a new batch of units. Instead of having an angle of exactly 70 degrees, for example, the angle will accidentally deviate by a fraction of a degree.

[0037] Angular offset 172 is sufficient to significantly move ROI 150 within the footprint of semiconductor die 104, such as Figure 2f 104. With offset 172, ROI 150 moves in the Y direction until ROIs 150b and 150c are just on the edge of semiconductor die 104 and ROIs 150d and 150e move a significant distance toward the center of the die. The LAB process will continue with area 170 relative to the IR camera's view being monitored for the same ROI 150 pixels. However, because area 170 has moved, the pixels being monitored are no longer located at the actual point of interest on semiconductor 104. ROI 150 in the IR camera 136 image is no longer aligned with the actual area of ​​interest on semiconductor die 104.

[0038] Figure 2g Detail of misplaced ROI 150b is shown. IR camera 136 has been moved so that the distance 182 between ROI 150b and corner 153b in the X direction is significantly greater than the distance 184 between the corner and ROI in the Y direction. The location actually being monitored by IR camera 136 is not the expected location of ROI 150b.

[0039] Similarly, Figure 2h 150a is shown misplaced. ROI 150b should be centered on semiconductor die 104. However, movement of IR camera 136 has moved ROI 150a in both the X and Y axes. Distance 186 between ROI 150a and corner 153b in the X direction is different from distance 187 between ROI and corner 153c in the X direction, although these distances should be the same. Distance 188 between ROI 150a and corner 153b in the Y direction is different from distance 189 between ROI and corner 153d in the Y direction, although these distances should be the same. The location that is actually being monitored by IR camera 136 as ROI 150a is not centered on semiconductor die 104 as expected.

[0040] Figure 3a-3e A method and system for automatic ROI positioning are presented. Figure 3a-3e The image in is from the viewpoint of IR camera 136. Figure 3a The IR image 190 in FIG. 1 is the raw image captured by the IR camera 136. Computer image processing is used to take the IR image 190 as input and then output a pixel map 192 showing Figure 3b The image processing used to generate pixel map 192 involves any combination of filtering, increasing contrast, sharpening, smoothing, binarization (i.e., converting pixels into one of two possible values, such as 1 or 0), etc. suitable for positively identifying boundary 200. Based on the known approximate shape and position of the semiconductor die, other visual features (such as components disposed on substrate 120 adjacent to semiconductor die 104) can be eliminated.

[0041] After image processing, Figure 3b The composite image in shows the occupied area of ​​the die 104 as white and the substrate 120 outside the die as black. Black and white are used because those colors are highly contrasting to the human eye. However, any two values ​​can be used to distinguish the area of ​​the die 104 from the substrate 120. The computer processed image can be used by a computer algorithm to identify the boundary 200 by finding the boundary between black pixels and white pixels.

[0042] like Figure 3cAs shown, using the bitmap 192, the exact pixel locations of the die center 153a and corners 153b-153e can be easily identified. The corners 153b-153e are identified as the farthest white pixels in each direction. The center 153a is identified as the average location between the four corners. The conversion from the corners 153b-153e to the location of the ROI 150b-150e is a simple matter of adding or subtracting the distances 152 and 154 from each corner pixel 153b-153e to find the location of the corresponding ROI.

[0043] Figure 3d The ROI 150 is shown superimposed onto the IR image 190 along with markers 153 of the center and corners determined from the bitmap 192 . Figure 3e Only the resulting ROI 150 is shown. In one embodiment, the image processing software used to generate the bitmap 192 also outputs a list of coordinates of the center 153a and corners 153b-153e. In one embodiment, the user inputs a list of values ​​for the ROI size 156-158 and the ROI distance from the die edge 152-154, and the image processing software outputs a list of coordinates for the ROI 150, as shown in Table 1 below:

[0044] Coordinates of ROI 150a: X axis = 160 | Y axis = 109

[0045] Coordinates of ROI 150b: X axis = 145 | Y axis = 93

[0046] Coordinates of ROI 150c: X-axis = 175 | Y-axis = 94

[0047] Coordinates of ROI 150d: X axis = 145 | Y axis = 125

[0048] Coordinates of ROI 150e: X-axis = 174 | Y-axis = 125

[0049] Table 1

[0050] The list of ROI coordinates from Table 1, along with the ROI size, can be manually entered or automatically imported into the LAB software that actually does the temperature monitoring of the ROIs 150. The coordinates indicate the corner pixels of each ROI 150, which, along with the ROI size, tells the LAB software specifically which pixels of the IR image 190 to monitor. The ROI pixels can be recalculated for each die 104 being bonded, or the same pixels can be reused for each die 104 being processed, for the entire carrier 122, or for different units of the same die 104 and substrate 120 as long as they are being processed. The coordinates can optionally be reused until the LAB assembly 130 is manually touched, until a positioning error is detected, or automatically recalculated periodically (e.g., daily or hourly).

[0051] Figure 4a-4c An example is shown where the distance to each corner is 4 pixels and the ROI size is 4 pixels in each direction. Figure 4a The substrate 120 is shown with a ROI 210 and position markers 212 as seen by the IR camera 136 . Figure 4b is a close-up view of corner 153b. Figure 4c This is a magnified view of the die 104. First, the user inputs distance and size parameters into the image processing system. Figure 4a-4c , the same 4 pixel values ​​are input for each parameter 214.

[0052] The image processing software generates a bitmap showing the exact location of the die 104 in the IR image, and then automatically accurately locates the exact pixel for the corners indicated by the markers 212b-212e and the center indicated by the marker 212a. The image processing software then places the ROI 150a-150e based on the pixels identified by the markers. The ROI 210b-210e is placed so that one corner is four pixels inward from the marker 212b-212e in both the X and Y directions, respectively. The opposite corner of each corner ROI 210b-210e is placed four additional pixels inward in both the X and Y directions.

[0053] Center mark 212a is placed at the average location of all four corner marks 212b-212e. Center ROI 210a is placed at center mark 212a with a size of four pixels by four pixels. Distance 216 in the Y direction is the same between the edges of semiconductor die 104 in both directions. Distance 218 in the X direction is the same between the edges of semiconductor die 104 in both directions. The square representations of ROIs 210a-210e show the pixels of the image that will be monitored during LAB.

[0054] Figure 5a-5cAnother example is shown where the distance from each corner is 8 pixels and the ROI size is 8 pixels in each direction. Figure 5a The substrate 120 is shown with a ROI 220 and position markers 222 as seen by the IR camera 136 . Figure 5b is a close-up view of corner 153b. Figure 5c is an enlarged view of the tube core 104. Figure 5a-5c , the user begins by entering eight pixels for all distance parameters 224 .

[0055] The image processing software generates a bitmap showing the exact location of the die 104 in the IR image, and then accurately locates the exact pixel for the corner indicated by the marker 222b-222e. The image processing software places one corner of the corner ROI 220b-220e eight pixels inward from the marker 222b-222e in both the X and Y directions, respectively. The opposite corner of each corner ROI 220b-220e is placed eight additional pixels inward in both the X and Y directions.

[0056] The center mark 222a is placed at the average position of all four corner marks 222b-222e. The center ROI 220a is placed at the center mark 222a with a size of eight pixels by eight pixels. The distance 226 in the Y direction is the same between the edges of the semiconductor die 104 in both directions. The distance 228 in the X direction is the same between the edges of the semiconductor die 104 in both directions. The squares of the ROIs 220a-220e represent pixels corresponding to the image to be monitored during the LAB. The LAB proceeds with the pixels identified as the ROI being monitored to keep the temperature of the semiconductor die 104 within acceptable limits.

[0057] Once all of the dies 104 on the substrate 120 are bonded via LAB, fabrication continues with other desired steps.Any type of package may be formed. Figure 6a FIG. 1 is just one example of many possibilities in which multiple dies 104 are bonded to substrate 120. Figure 6b In the process, encapsulant or molding compound 230 is deposited on substrate 120 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. Encapsulant 230 can be a polymer composite material, such as a polymer with or without fillers, epoxy resin, or epoxy acrylate. Encapsulant 230 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0058] exist Figure 6cIn the process, a saw blade, a water jet cutting tool, or a laser cutting tool 232 is used to singulate the panel formed by the substrate 120 and the encapsulant 230 into individual semiconductor packages 234. The packages 234 are typically stored in tape-and-reel after singulation for distribution to electronic device manufacturers who will integrate the devices into their products. The substrate 120 includes: conductive layers and other interconnect structures for routing signals through the substrate. The bottom surface of the substrate 120 opposite the tube core 104 will typically have a ball grid array, a contact grid array, or other types of interconnect structures for electrically connecting to larger electronic devices. Figure 6a-6c It is intended to illustrate only one of many different ways that a package can be completed after laser assisted bonding. Any type of substrate can have a semiconductor die bonded to the substrate using laser assisted bonding, and any desired processing can be performed after laser assisted bonding to form any kind of final package. The disclosed ROI placement method can work for any situation where a LAB is used.

[0059] Figure 7 An electronic device 350 is shown including a PCB 300 with multiple semiconductor packages mounted on a surface of the PCB, including package 234 and die 104. Electronic device 350 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Die 104 mounted directly to PCB 300 illustrates that the die-beam alignment process may be used to mount the die directly to a device substrate 300 in addition to a package substrate 120.

[0060] Electronic device 350 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 350 may be a subcomponent of a larger system. For example, electronic device 350 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Electronic device 350 may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete active or passive device, or other semiconductor die or electronic component.

[0061] PCB 300 provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 302 are formed on the surface of PCB 300 or within the layers of PCB 300 using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 302 provide electrical communication between semiconductor packages, mounted components and other external systems or components. Traces 302 also provide power and ground connections to the semiconductor package as needed.

[0062] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to the PCB 300. In other embodiments, the semiconductor device may have only the first level of packaging, where the die is mechanically and electrically mounted directly to the PCB 300.

[0063] For purposes of illustration, several types of first level packages are shown on PCB 300, including bond wire package 356 and flip chip 358. Additionally, several types of second level packages, including ball grid array (BGA) 360, bump chip carrier (BCC) 362, land grid array (LGA) 366, multi-chip module (MCM) 368, quad flat no-lead package (QFN) 370, and quad flat package 372, are shown mounted on PCB 300 along with die 104 and package 234. Conductive traces 302 electrically couple the various packages and components disposed on PCB 300.

[0064] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electronic components can be connected to the PCB 300. In some embodiments, the electronic device 350 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and assembly line manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0065] While one or more embodiments of the present invention have been shown in detail, those skilled in the art will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing semiconductor dies; disposing a laser assisted bonding assembly including an infrared camera on the semiconductor die; capturing an image of the semiconductor die using the infrared camera; performing image processing on the image to identify corners of the semiconductor die; identifying a region of interest in the image relative to the corners of the semiconductor die; as well as When performing laser-assisted bonding with the laser-assisted bonding assembly, the camera is used to monitor the temperature of the area of ​​interest without monitoring the temperature outside the area of ​​interest. 2 . The method of claim 1 , further comprising identifying the region of interest using an input parameter of a distance of the region of interest from a corresponding corner of the semiconductor die. The method of claim 2 , further comprising identifying the region of interest using an input parameter of a size of the region of interest.

4. The method according to claim 1, further comprising: providing a plurality of semiconductor dies; moving the laser assisted bonding assembly over each semiconductor die to individually perform laser assisted bonding; as well as A region of interest for each semiconductor die is automatically identified after moving the laser assisted bonding assembly to the corresponding semiconductor die. 5 . The method of claim 1 , further comprising monitoring a temperature of the region of interest using the infrared camera while performing laser assisted bonding with the laser assisted bonding assembly.

6. The method according to claim 1, wherein: Perform image processing including binarization.

7. A method for manufacturing a semiconductor device, comprising: providing semiconductor dies; capturing an image of the semiconductor die; identifying corners of the semiconductor die in the image; as well as Regions of interest in the image are identified relative to the corners of the semiconductor die by adding or subtracting a predetermined number of pixels from the corners. 8 . The method of claim 7 , further comprising identifying the region of interest using an input parameter of a distance of the region of interest from the corner of the semiconductor die.

9. The method of claim 7, further comprising identifying the region of interest using an input parameter of a size of the region of interest.

10. The method of claim 7, further comprising periodically capturing the image and identifying the region of interest.

11. The method of claim 7, further comprising monitoring a temperature of the region of interest while performing laser assisted bonding on the semiconductor die. 12 . The method of claim 11 , further comprising depositing an encapsulant on the semiconductor die after performing laser assisted bonding.

13. The method of claim 7, further comprising identifying corners of the semiconductor die by performing image processing on the image.

14. A semiconductor manufacturing system comprising: Laser-assisted joining of components; an infrared camera attached to the laser assisted bonding assembly; as well as A computer configured to: finding the corners of the semiconductor die in the image captured by the infrared camera, and Regions of interest in the image are identified relative to the corners of the semiconductor die by adding or subtracting a predetermined number of pixels from the corners.

15. The semiconductor manufacturing system of claim 14, further comprising a parameter defining a position of the region of interest relative to the corner.

16. The semiconductor manufacturing system of claim 15, further comprising a parameter defining a size of the region of interest.

17. The semiconductor manufacturing system of claim 14, further comprising a semiconductor die disposed beneath the laser assisted bonding assembly.

18. A method for manufacturing a semiconductor device, comprising: providing semiconductor dies; capturing an infrared image of the semiconductor die using an infrared camera; performing image processing on the infrared image to identify corners of the semiconductor die; identifying a region of interest in the infrared image relative to the corner of the semiconductor die; performing laser assisted bonding on the semiconductor die; as well as When performing laser assisted bonding, the temperature of only the area of ​​interest is monitored with the infrared camera.

19. The method of claim 18, further comprising performing laser assisted bonding on the semiconductor die while monitoring the temperature of the region of interest with the infrared camera.

20. The method of claim 19, further comprising depositing an encapsulant on the semiconductor die after performing laser assisted bonding.

21. The method of claim 18, further comprising periodically capturing the infrared image and identifying the region of interest.

22. The method of claim 18, wherein performing image processing comprises binarization.

23. The method of claim 18, further comprising identifying the region of interest using an input parameter of a distance of the region of interest from a corresponding corner of the semiconductor die.

24. The method of claim 18, further comprising identifying the region of interest using an input parameter of a size of the region of interest.

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