Display panel, control method thereof, and display device

Abstract

Embodiments of the present application provide a display panel, a control method thereof and a display device. In the display panel provided by the embodiments of the present application, the storage capacitor includes the first capacitor and the second capacitor in parallel, and the capacitance value of the second capacitor in the charging stage is smaller than that in the maintaining stage in one display cycle, so that the capacitance value of the storage capacitor can be reduced in the charging stage, the charging rate of the pixel can be improved, and the refresh rate of the display panel can be improved. Meanwhile, the capacitance value of the storage capacitor can be increased in the maintaining stage, so that the maintaining capability of the pixel voltage can be improved, the requirements of the display panel at low refresh can be supported, and the power consumption of the display panel can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and its control method, and a display device. Background Technology

[0002] With the development of display technology, consumers have increasingly higher requirements for the display quality of display panels. Currently, increasing the refresh rate is an important means to improve the display quality. However, with the increase in refresh rate, the power consumption of the display panel also increases significantly, which seriously affects the battery life of portable mobile display devices.

[0003] Currently, for the pixel circuit of the display panel, in the high refresh rate mode, it is necessary to ensure the charging rate of the pixel, that is, to ensure that the storage capacitor in the pixel circuit has a small capacitance value. In the low refresh rate mode, it is necessary to ensure the pixel voltage is maintained, that is, to ensure that the storage capacitor has a large capacitance value. These two modes have conflicting requirements for the capacitance value of the storage capacitor, making it difficult for existing display panels to achieve both high refresh rate and low power consumption. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a display panel, its control method, and a display device to solve the technical problem that display panels in the prior art cannot simultaneously achieve high refresh rates and low power consumption.

[0005] In a first aspect, embodiments of this application provide a display panel, including:

[0006] Thin-film transistors;

[0007] The storage capacitor is electrically connected to the thin-film transistor. The storage capacitor includes a first capacitor and a second capacitor connected in parallel. During one display cycle, the capacitance value of the second capacitor changes with the applied adjustment signal, such that the capacitance value of the second capacitor during the charging phase is less than the capacitance value during the maintenance phase.

[0008] Secondly, embodiments of this application provide a display device, including: the display panel provided in the first aspect.

[0009] Thirdly, embodiments of this application provide a method for controlling a display panel, including:

[0010] An adjustment signal is applied to a second capacitor that stores capacitance in the display panel, such that the capacitance value of the second capacitor during the charging phase is less than the capacitance value during the maintenance phase within one display cycle.

[0011] The beneficial technical effects of the technical solutions provided in this application include:

[0012] In the display panel provided in this application embodiment, by setting the storage capacitor to include a first capacitor and a second capacitor connected in parallel, and by ensuring that the capacitance value of the second capacitor is less during the charging phase than during the maintenance phase within a display cycle, the capacitance value of the storage capacitor can be reduced during the charging phase, thereby improving the pixel charging rate and supporting the increase of the display panel refresh rate. Simultaneously, the capacitance value of the storage capacitor can be increased during the maintenance phase, thereby improving the pixel voltage maintenance capability, supporting the display panel requirements at low refresh rates, and reducing the power consumption of the display panel.

[0013] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0015] Figure 1 This is a top view schematic diagram of a display panel structure provided in an embodiment of this application;

[0016] Figure 2 Provided for the embodiments of this application Figure 1 A schematic cross-sectional view of the AA structure of the display panel shown.

[0017] Figure 3 The capacitance-voltage characteristic curve of a second capacitor in a display panel provided in the embodiments of this application;

[0018] Figure 4 This is a schematic diagram of the structural framework of a display device provided in an embodiment of this application;

[0019] Figure 5 This is a schematic diagram of the structural framework of another display device provided in an embodiment of this application.

[0020] Explanation of reference numerals in the attached figures:

[0021] 100 - Display panel; 101 - Display area; 102 - Peripheral area;

[0022] 10-Thin Film Transistor;

[0023] 20 - Storage capacitor;

[0024] 21-First capacitor; 211-Third electrode; 212-Fourth electrode;

[0025] 22-Second capacitor; 221-First electrode; 222-Dielectric layer; 223-Semiconductor layer; 224-Second electrode;

[0026] 30 - Substrate; 301 - First insulating layer; 302 - Second insulating layer; 303 - Third insulating layer; 304 - Fourth insulating layer; 40 - First signal trace; 50 - Second signal trace;

[0027] 201 - First control unit; 202 - GOA circuit. Detailed Implementation

[0028] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0029] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in this application's specification means the presence of the stated features, integers, steps, and / or operations, but does not exclude implementation as supported by this art, other features, information, data, steps, operations, and / or combinations thereof. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] First, the relevant technologies involved in this application will be explained:

[0032] Refresh rate refers to the number of times the screen image is repeatedly scanned. A higher refresh rate means that the image is displayed more frequently per unit of time, which helps to improve the stability of the screen image.

[0033] For portable mobile display devices, battery life is an important metric. However, the higher the refresh rate, the greater the power consumption, which greatly limits the improvement of the refresh rate of portable mobile display devices.

[0034] Currently, the pixel circuit of a display panel includes a storage capacitor. If the display panel needs to support a high refresh rate, the storage capacitor needs to have a small capacitance value to ensure that the pixel circuit has a high charging rate. If the display panel needs to support a low refresh rate, the storage capacitor needs to have a large capacitance value to ensure the pixel voltage maintenance capability and reduce leakage.

[0035] In other words, increasing the pixel charging rate requires decreasing the capacitance of the storage capacitor in the pixel circuit, while maintaining the pixel voltage requires increasing the capacitance of the storage capacitor. This contradicts the requirements for the storage capacitor's capacitance, preventing existing display panels from simultaneously achieving high refresh rates and low power consumption. Consequently, these display panels struggle to support both high and low refresh rate modes, making it difficult for portable mobile display devices to achieve both.

[0036] The display panel, control method, and display device provided in this application are intended to address the aforementioned technical problems of the prior art.

[0037] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0038] This application provides a display panel, the structural schematic diagram of which is shown below. Figure 1 As shown, it includes: a thin-film transistor 10 and a storage capacitor 20.

[0039] In this embodiment, the storage capacitor 20 is electrically connected to the thin-film transistor 10. The storage capacitor 20 includes a first capacitor 21 and a second capacitor 22 connected in parallel. During one display cycle, the capacitance value of the second capacitor 22 changes with the applied adjustment signal, such that the capacitance value of the second capacitor 22 during the charging phase is less than the capacitance value during the maintenance phase.

[0040] In the display panel 100 provided in this embodiment, by configuring the storage capacitor 20 to include a first capacitor 21 and a second capacitor 22 connected in parallel, and by ensuring that the capacitance value of the second capacitor 22 is lower during the charging phase than during the maintenance phase within a display cycle, the capacitance value of the storage capacitor 20 can be reduced during the charging phase, thereby improving the pixel charging rate and supporting an increase in the refresh rate of the display panel 100. Simultaneously, the capacitance value of the storage capacitor 20 can be increased during the maintenance phase, thereby improving the pixel voltage maintenance capability, supporting the requirements of the display panel 100 at low refresh rates, and reducing the power consumption of the display panel 100.

[0041] In this embodiment of the application, the pixel circuit of the display panel 100 includes a storage capacitor 20 electrically connected to the thin film transistor 10. The storage capacitor 20 includes a first capacitor 21 and a second capacitor 22 connected in parallel, that is, the sum of the capacitance value of the first capacitor 21 and the capacitance value of the second capacitor 22 is the capacitance value of the storage capacitor 20.

[0042] In this embodiment, within a display cycle, the capacitance value of the second capacitor 22 changes with the applied adjustment signal, such that the capacitance value of the second capacitor 22 in the charging phase is less than the capacitance value in the maintenance phase. This results in the capacitance value of the storage capacitor 20 in the charging phase being less than the capacitance value in the maintenance phase, thereby improving the charging rate in the charging phase and the pixel voltage maintenance capability in the maintenance phase. This allows the display panel 100 to support not only higher refresh rates but also lower refresh rates, thus enabling the display panel 100 to have both high refresh rate and low power consumption characteristics.

[0043] Because the capacitance value of the storage capacitor 20 is smaller during the charging phase than during the maintenance phase, the charging rate can be effectively improved, thereby shortening the charging time and supporting an increase in the refresh rate of the display panel 100. Optionally, the refresh rate of the display panel 100 can be 90Hz, 120Hz, or even higher than 180Hz to meet the requirements of displaying higher image quality. Simultaneously, by increasing the capacitance value of the storage capacitor 20 during the maintenance phase, the energy storage capacity of the storage capacitor 20 can be increased, thereby improving the pixel voltage holding capability, effectively reducing leakage current, and enabling the display panel 100 to operate at a lower refresh rate. Optionally, the refresh rate of the display panel 100 can be 60Hz, 30Hz, or even below 10Hz, thereby reducing the power consumption of the display panel 100 and improving the battery life of applications using the display panel 100.

[0044] In the display panel 100 provided in this application embodiment, by setting a second capacitor 22 whose capacitance value can be changed, the capacitance value of the storage capacitor in the pixel circuit can be adjusted, so that the display panel 100 can support both high refresh rates and low refresh rates. This widens the range of refresh rates that the display panel 100 can adjust, allowing the display panel 100 to adjust its own refresh rate according to actual operating conditions. It can use a high refresh rate when high image quality is required, and use a lower refresh rate to reduce power consumption when high image quality is not required, thereby ensuring battery life while maintaining high-frequency image quality.

[0045] Optionally, such as Figure 2 As shown, in one embodiment of this application, the second capacitor 22 includes a first electrode 221, a dielectric layer 222, a semiconductor layer 223, and a second electrode 224, which are sequentially stacked on one side of the substrate 30.

[0046] In the embodiments of this application, such as Figure 2As shown, the first electrode 221, the dielectric layer 222, the semiconductor layer 223, and the second electrode 224 are stacked sequentially on one side of the substrate 30. The dielectric layer 222 and the semiconductor layer 223 are sandwiched between the first electrode 221 and the second electrode 224. Since the conductivity of the semiconductor layer 223 changes with the change of the external electric field, the actual distance between the two electrode plates of the second capacitor 22 can be changed by changing the conductivity of the semiconductor layer 223, thereby changing the capacitance value of the second capacitor 22.

[0047] In this embodiment, since the second capacitor 22 includes a semiconductor layer 223, the second capacitor 22 forms a MIS (Metal Insulator Semiconductor) structure. Since the electrical properties of the semiconductor layer 223 can be changed under the action of an electric field, the capacitance value of the second capacitor 22 can be changed.

[0048] like Figure 3 The figure shows the capacitance versus voltage characteristic curve of the second capacitor 22 (hereinafter referred to as the P-type second capacitor 22), which includes the P-type semiconductor layer 223. Figure 3 The horizontal axis represents voltage (V), and the vertical axis represents capacitance (C). Figure 3 As shown by line segment BCD, when the voltage varies around 0V, the capacitance of the second capacitor 22 is negatively correlated with the voltage, meaning that the capacitance gradually decreases as the voltage increases. Optionally, for the second capacitor 22 including the N-type semiconductor layer 223 (hereinafter referred to as the N-type second capacitor 22), its capacitance value changes in the opposite way to that of the P-type second capacitor 22. When the voltage varies around 0V, the capacitance of the second capacitor 22 is positively correlated with the voltage, meaning that the capacitance gradually increases as the voltage increases.

[0049] It should be noted that, as Figure 3 As shown, when the absolute value of the voltage is greater than the threshold, the capacitance value of the second capacitor 22 will remain constant and will not change with the voltage, as shown by line segments AB and DGH.

[0050] Optionally, in this embodiment, the second capacitor 22 can be a high-frequency capacitor or a low-frequency capacitor, such as... Figure 3 As shown, line segment ABCDGH represents the characteristic curve of a high-frequency capacitor, and line segment ABCDEF represents the characteristic curve of a low-frequency capacitor.

[0051] Optionally, in this embodiment, the first electrode 221 is used to receive an adjustment signal, causing the semiconductor layer 223 to switch between a semiconductor state and a conductor state.

[0052] In this embodiment of the application, when the first electrode 221 is connected to the adjustment signal, the electrical characteristics of the semiconductor layer 223 change under the excitation of the electric field formed by the adjustment signal.

[0053] Optionally, for the P-type second capacitor 22, during the charging phase, the adjustment signal is at a high level. As the adjustment signal gradually increases, the electrical characteristics of the semiconductor layer 223 gradually change, and the semiconductor layer 223 gradually transitions to a semiconductor state, which is equivalent to the effective thickness of the dielectric layer 222 gradually increasing. Figure 3 It can be seen that the capacitance value of the P-type second capacitor 22 gradually decreases, thereby causing the capacitance value of the storage capacitor 20 to gradually decrease.

[0054] During the maintenance phase, the adjustment signal is at a low level. As the adjustment signal gradually decreases, the electrical characteristics of the semiconductor layer 223 gradually change, and the semiconductor layer 223 gradually transitions to a conductor state. This is equivalent to a gradual decrease in the effective thickness of the dielectric layer 222. Figure 3 It can be seen that the capacitance value of the P-type second capacitor 22 gradually increases, thereby causing the capacitance value of the storage capacitor 20 to gradually increase.

[0055] Optionally, for the N-type second capacitor 22, during the charging phase, the adjustment signal is at a low level. As the adjustment signal gradually increases, the electrical characteristics of the semiconductor layer 223 gradually change, and the semiconductor layer 223 gradually transforms into a semiconductor state. This is equivalent to the effective thickness of the dielectric layer 222 gradually increasing, and the capacitance value of the N-type second capacitor 22 gradually decreasing, thereby causing the capacitance value of the storage capacitor 20 to gradually decrease.

[0056] During the maintenance phase, the adjustment signal is at a high level. As the adjustment signal gradually decreases, the electrical characteristics of the semiconductor layer 223 gradually change, and the semiconductor layer 223 gradually transforms into a conductor state. This is equivalent to the effective thickness of the dielectric layer 222 gradually decreasing, and the capacitance value of the N-type second capacitor 22 gradually increasing, thereby causing the capacitance value of the storage capacitor 20 to gradually increase.

[0057] Optionally, a second electrode 224 may be provided to receive an adjustment signal, so that the semiconductor layer 223 switches between a semiconductor state and a conductor state.

[0058] In the display panel 100 provided in this application embodiment, by adding a second capacitor 22 and an adjustment signal for controlling the change of the capacitance value of the second capacitor 22, the charging rate can be guaranteed in high refresh rate mode and the pixel voltage can be maintained in low refresh rate mode, so that the display panel 100 can have both high refresh rate and low power consumption.

[0059] Optionally, such as Figure 1As shown, in one embodiment of this application, the first electrode 221 is electrically connected to one end of the first signal line 40, and the other end of the first signal line 40 is used to receive the adjustment signal.

[0060] In this embodiment, by setting a first signal trace 40 that is separately connected to the adjustment signal, it is possible to avoid other signals affecting the capacitance value of the second capacitor 22. Thus, during the operation of the display panel 100, the control accuracy of the capacitance value of the second capacitor 22 in the display panel 100 can be guaranteed, thereby ensuring the display effect.

[0061] Optionally, in one embodiment of this application, the first electrode 221 is disposed on the same layer as the gate of the thin film transistor 10; the second electrode 224 is disposed on the same layer as the source and drain of the thin film transistor 10, and the second electrode 224 and one electrode of the first capacitor 21 are both electrically connected to the source and drain of the thin film transistor 10.

[0062] In this embodiment, the second capacitor 22 and the thin film transistor 10 are disposed on the same layer. During the manufacturing process of the display panel 100, the second capacitor 22 and the thin film transistor 10 can be formed simultaneously, thereby improving the manufacturing efficiency of the display panel 100 and helping to reduce the manufacturing cost of the display panel 100.

[0063] Optionally, in this embodiment, the first electrode 221 is disposed on the same layer as the gate of the thin film transistor 10, the second electrode 224 is disposed on the same layer as the source and drain of the thin film transistor 10, the insulating layer 2221 is disposed on the same layer as the insulating layer of the thin film transistor 10, and the semiconductor layer 223 is disposed on the same layer as the active layer of the thin film transistor 10.

[0064] Optionally, in the embodiments of this application, during the manufacturing process of the gate and the first electrode 221 of the thin film transistor 10, the first signal trace 40 electrically connected to the first electrode 221 can be manufactured simultaneously, so that the first electrode 221 and the first signal trace 40 are disposed on the same layer, thereby further improving the manufacturing efficiency of the display panel 100 and helping to reduce the manufacturing cost of the display panel 100.

[0065] In this embodiment, the first capacitor 21 may include a pixel electrode, a common electrode, and a dielectric film layer sandwiched between the pixel electrode and the common electrode. For the liquid crystal display panel 100, since the pixel electrode and the common electrode are located on the side of the thin-film transistor 10 away from the substrate 30, in this embodiment, the first capacitor 21 is disposed on the side of the second capacitor 22 away from the substrate 30.

[0066] Optionally, in the embodiments of this application, such as Figure 2As shown, the first capacitor 21 includes a third electrode 211 and a fourth electrode 212. The second electrode 224 and the third electrode 211 are both electrically connected to the source and drain of the thin-film transistor 10, thereby realizing the parallel connection of the first capacitor 21 and the second capacitor 22.

[0067] Optionally, such as Figure 2 As shown, a first insulating layer 301, a second insulating layer 302, a third insulating layer 303, and a fourth insulating layer 304 are disposed on one side of the substrate 30. The first insulating layer 301 can be disposed in the same layer as the gate insulating layer of the thin film transistor 10, the second insulating layer 302 can be a passivation layer, part of the third insulating layer 303 serves as the dielectric layer of the first capacitor 21, and the fourth insulating layer 304 serves as an isolation layer.

[0068] Optionally, in one embodiment of this application, the gate of the thin-film transistor 10 is electrically connected to the second signal line 50, and the second signal line 50, the first electrode 221, and the first signal line 40 are disposed on the same layer.

[0069] In this embodiment, the second signal line 50 is a scan line, electrically connected to the gate of the thin-film transistor 10, and used to control the switching on and off of the thin-film transistor 10. In this embodiment, during the manufacturing process of the gate and the first electrode 221 of the thin-film transistor 10, the first signal line 40 electrically connected to the first electrode 221 and the second signal line 50 electrically connected to the gate can be manufactured simultaneously, thereby further improving the manufacturing efficiency of the display panel 100 and helping to reduce the manufacturing cost of the display panel 100.

[0070] Optionally, in the embodiments of this application, the display panel 100 is a liquid crystal display panel 100, and the display panel 100 provided in the above embodiments is an array substrate of the liquid crystal display panel 100. The liquid crystal display panel 100 also includes a color filter substrate disposed opposite to the array substrate.

[0071] Based on the same inventive concept, this application provides a display device, including: any of the display panels 100 provided in the above embodiments.

[0072] In this embodiment, since the display device uses any of the display panels 100 provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0073] Optionally, in this embodiment, the display device is a mobile phone, tablet computer, laptop computer, or smart TV, etc.

[0074] In this embodiment, the adjustment signal can be generated by the unit's control unit, or it can reuse a signal from a GOA (Gate Driven on Array) circuit in an existing display device.

[0075] Optionally, such as Figure 4 As shown, in one embodiment of this application, the display device further includes: a first control unit 201, electrically connected to the second capacitor 22 of the display panel 100, for outputting an adjustment signal to the second capacitor 22. The adjustment signal includes a high-level signal and a low-level signal.

[0076] In this embodiment, the first control unit 201 is used to generate an adjustment signal and send it to the second capacitor 22, such as... Figure 4 As shown, the first control unit 201 is connected to the first signal line 40 so that the adjustment signal can be transmitted to the second capacitor 22 through the first signal line 40.

[0077] Optionally, the first control unit 201 and the data driving unit in the GOA circuit 202 are coordinated in timing to control the capacitance value of the second capacitor 22 by outputting a high-level signal or a low-level signal to the corresponding row. During the charging phase, the adjustment signal output by the first control unit 201 controls the capacitance value of the second capacitor 22 to decrease, and at the same time, the data driving unit outputs a data signal to the pixel corresponding to the second capacitor 22.

[0078] Optionally, such as Figure 5 As shown, in one embodiment of this application, the display device further includes: a GOA circuit 202, electrically connected to the second capacitor 22 of the display panel 100, for outputting an adjustment signal to the second capacitor 22; the adjustment signal includes a scan signal or a reset signal of the thin-film transistor 10.

[0079] In this embodiment, the GOA circuit 202 is used to generate an adjustment signal and send it to the second capacitor 22, such as... Figure 5 As shown, the GOA circuit 202 is connected to the first signal trace 40 so that the generated adjustment signal can be transmitted to the second capacitor 22 through the first signal trace 40. Optionally, the GOA circuit 202 is disposed in the peripheral area 102 surrounding the display area 101 in the display panel 100. Optionally, to facilitate a visual understanding of the positional relationship between the display area 101 and the peripheral area 102, Figure 5 The dashed line in the middle represents the display area 101, but the dashed line does not exist in the actual product.

[0080] Optionally, for the P-type second capacitor 22, the adjustment signal includes a scan signal generated by the GOA circuit 202 for controlling the turning on or off of the thin-film transistor 10. When the thin-film transistor 10 needs to be turned on, the scan signal includes a high-level signal. During the turning-on process of the thin-film transistor 10, the pixel circuit enters the charging stage, and the high-level signal of the scan signal can reduce the capacitance value of the P-type second capacitor 22. When the thin-film transistor 10 needs to be turned off, the scan signal includes a low-level signal. During the turning-off process of the thin-film transistor 10, the pixel circuit enters the maintenance stage, and the low-level signal of the scan signal can increase the capacitance value of the P-type second capacitor 22. Therefore, the adjustment signal can reuse the scan signal, thereby avoiding the need for a separate control unit for generating the adjustment signal and reducing the manufacturing cost of the display device.

[0081] Optionally, a terminal for electrical connection with the first signal trace 40 may be provided in the GOA circuit 202 to transmit an adjustment signal to the second capacitor 22.

[0082] Optionally, for the P-type second capacitor 22, since the adjustment signal can reuse the scan signal, the first signal trace 40 can be connected to the second signal trace 50, thus avoiding the need to set a terminal in the GOA circuit 202 for electrical connection with the first signal trace 40.

[0083] Optionally, for the N-type second capacitor 22, the adjustment signal includes a reset signal generated by the GOA circuit 202. During the charging phase of the pixel circuit, the reset signal includes a low-level signal, which reduces the capacitance value of the N-type second capacitor 22. During the maintenance phase of the pixel circuit, the reset signal includes a high-level signal, which increases the capacitance value of the N-type second capacitor 22. Therefore, the adjustment signal can reuse the reset signal, thereby avoiding the need for a separate control unit to generate the adjustment signal and reducing the manufacturing cost of the display device.

[0084] Optionally, the first signal trace 40 is electrically connected to the PD node of the GOA circuit 202 so that the reset signal can be transmitted to the second capacitor 22.

[0085] Based on the same inventive concept, embodiments of this application provide a control method for a display panel, including: applying an adjustment signal to a second capacitor storing capacitance in the display panel, such that during a display cycle, the capacitance value of the second capacitor during the charging phase is less than the capacitance value during the maintenance phase.

[0086] In this embodiment, an adjustment signal is transmitted to the display panel via the first control unit 201 or the GOA circuit 202. The adjustment signal is transmitted to the first electrode 221 of the second capacitor 22 via the first signal trace 40. The capacitance value of the second capacitor 22 changes with the adjustment signal, so that within one display cycle, the capacitance value of the second capacitor 22 during the charging phase is less than the capacitance value during the maintenance phase. This improves the pixel charging rate, supports the improvement of the display panel refresh rate, enhances the pixel voltage maintenance capability, supports the display panel requirements at low refresh rates, and reduces the power consumption of the display panel.

[0087] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0088] In the display panel provided in this embodiment, by configuring the storage capacitor 20 to include a first capacitor 21 and a second capacitor 22 connected in parallel, and by ensuring that the capacitance value of the second capacitor 22 is lower during the charging phase than during the maintenance phase within a display cycle, the capacitance value of the storage capacitor 20 can be reduced during the charging phase, thereby improving the pixel charging rate and supporting the increase in the display panel refresh rate. Simultaneously, the capacitance value of the storage capacitor 20 can be increased during the maintenance phase, thereby improving the pixel voltage maintenance capability, supporting the display panel requirements at low refresh rates, and reducing the power consumption of the display panel.

[0089] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0090] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0091] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0092] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0093] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0094] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0095] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: Thin-film transistors; A storage capacitor is electrically connected to the thin-film transistor; The storage capacitor includes a first capacitor and a second capacitor connected in parallel. During a display cycle, the capacitance value of the second capacitor changes with the applied adjustment signal, such that the capacitance value of the second capacitor during the charging phase is less than the capacitance value during the maintenance phase. The second capacitor includes a first electrode, a dielectric layer, a semiconductor layer, and a second electrode stacked sequentially on one side of the substrate; The first electrode is used to receive the adjustment signal, causing the semiconductor layer to switch between a semiconductor state and a conductor state; The adjustment signal includes a reset signal; During the charging phase of the pixel circuit, the reset signal includes a low-level signal to reduce the capacitance value of the second capacitor. During the maintenance phase of the pixel circuit, the reset signal includes a high-level signal to increase the capacitance value of the second capacitor.

2. The display panel according to claim 1, characterized in that, The first electrode is electrically connected to one end of the first signal trace, and the other end of the first signal trace is used to receive the adjustment signal.

3. The display panel according to claim 1, characterized in that, The first electrode is disposed in the same layer as the gate of the thin-film transistor; The second electrode is disposed on the same layer as the source and drain of the thin-film transistor, and both the second electrode and one electrode of the first capacitor are electrically connected to the source and drain of the thin-film transistor.

4. The display panel according to claim 3, characterized in that, The gate of the thin-film transistor is electrically connected to the second signal trace, and the second signal trace, the first electrode, and the first signal trace are disposed on the same layer.

5. A display device, characterized in that, include: The display panel according to any one of claims 1-4.

6. The display device according to claim 5, characterized in that, Also includes: The first control unit is electrically connected to the second capacitor of the display panel and is used to output an adjustment signal to the second capacitor.

7. The display device according to claim 5, characterized in that, Also includes: The GOA circuit is electrically connected to the second capacitor of the display panel and is used to output an adjustment signal to the second capacitor; the adjustment signal includes a scan signal or a reset signal of the thin-film transistor.

8. A control method for a display panel as described in any one of claims 1-4, characterized in that, include: An adjustment signal is applied to a second capacitor that stores capacitance in the display panel, such that the capacitance value of the second capacitor during the charging phase is less than the capacitance value during the maintenance phase within one display cycle. The adjustment signal includes a reset signal; During the charging phase of the pixel circuit, the reset signal includes a low-level signal to reduce the capacitance value of the second capacitor. During the maintenance phase of the pixel circuit, the reset signal includes a high-level signal to increase the capacitance value of the second capacitor.

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