SiC MOSFET device structure

Abstract

The present application discloses a SiC The MOSFET device structure comprises: a source metal layer, an interlayer dielectric, a gate poly layer, a gate oxide layer, a P+ source region, an N+ source region, a Pwell region, an N-conducting layer, a P+ injection region, a JFET region, an N-epitaxial layer, an N+ substrate and a drain metal layer; the drain metal layer, the N+ substrate and the N-epitaxial layer are stacked in sequence; the JFET region is arranged on the upper layer of the N-epitaxial layer; the Pwell region, the P+ source region and the N+ source region are all arranged on the upper layer of the N-epitaxial layer and are located on both sides of the JFET region; the gate oxide layer is located on the upper layer of the JFET region and both ends are located on the upper layer of part of the N+ source region; the gate poly layer is located on the upper layer of part of the gate oxide layer; the P+ injection region is arranged at the center of the JFET region and is located at the lower layer of the gate oxide layer; the N-conducting layer is arranged in the JFET region corresponding to the region not covered by the gate poly layer, and the N-conducting layer overlaps with the Pwell region on one side; the interlayer dielectric covers the upper layers of the gate poly layer and the gate oxide layer; the source metal layer covers the upper layer of the interlayer dielectric. The present application can improve the reliability of the device.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a SiC MOSFET device structure. Background Art

[0002] SiC material is a typical representative of the third generation wide bandgap semiconductor materials. Due to its advantages such as higher critical breakdown electric field strength, higher carrier saturation drift velocity, and higher thermal conductivity, it has become an ideal material for making high-power, high-temperature, high-frequency, and radiation-resistant devices.

[0003] After more than 20 years of rapid development, SiC power devices have achieved impressive results. For example, 600V, 1200V, 1700V, 3300V, and 10kV SiC MOSFET devices have been successfully developed, and 600V, 1200V, and 1700V SiC MOSFET devices have been commercialized. However, there is still a lot of room for improvement in the reliability of SiC power devices. Taking SiC MOSFET as an example, on the one hand, the gate-drain capacitance C gd The size of affects the dynamic performance of MOSFET. On the other hand, in the reverse bias withstand voltage aging tests such as HTRB and H3TRB, the gate oxide reliability of MOSFET will be significantly reduced, and the excessive electric field strength will easily cause the gate oxide layer to break down prematurely, or generate more electron holes to be injected into the gate oxide, resulting in reduced gate oxide reliability. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a SiCMOSFET device structure that can reduce the electric field strength of the gate oxide layer, improve the reliability of the device, and reduce the gate-drain capacitance C gd size to optimize the switching characteristics of the device.

[0005] The present application provides a SiC MOSFET device structure, comprising:

[0006] Source metal layer, interlayer dielectric, gate poly layer, gate oxide layer, P+ source region, N+ source region, Pwell region, N- conducting layer, P+ injection region, JFET region, N- epitaxial layer, N+ substrate and drain metal layer;

[0007] The drain metal layer, the N+ substrate and the N- epitaxial layer are stacked in sequence from bottom to top;

[0008] The JFET region is disposed on the upper layer of the N-epitaxial layer;

[0009] The Pwell region, the P+ source region and the N+ source region are all arranged in the upper layer of the N-epitaxial layer and located on both sides of the JFET region, the N+ source region is formed in the Pwell region and close to both sides of the JFET region, the P+ source region is formed in the Pwell region and far away from both sides of the JFET region, and the N+ source region and the P+ source region are arranged adjacent to each other;

[0010] The gate oxide layer is located on the upper layer of the JFET region and both ends are located on the upper layer of part of the N+ source region;

[0011] The gate poly layer is located on the upper layer of a portion of the gate oxide layer;

[0012] The P+ implantation region is arranged at the center of the JFET region and is located at the lower layer of the gate oxide layer;

[0013] The N-conducting layer is disposed in the JFET region corresponding to the region not covered by the gate poly layer, and the N-conducting layer overlaps the Pwell on one side;

[0014] The interlayer dielectric covers the gate poly layer and the upper layer of the gate oxide layer;

[0015] The source metal layer covers the upper layer of the interlayer dielectric.

[0016] According to the SiC MOSFET device structure of the first aspect embodiment of the present application, at least the following beneficial effects are achieved: relative to the conventional SiC MOSFET device structure, the SiC MOSFET provided in the present application introduces a P+ injection region and an N-conducting layer. Specifically, when the device is in a blocking state, the gate oxide layer below the gate poly layer in the connected state is shielded by the P+ injection region for electric field, which effectively reduces the electric field strength of the gate oxide layer, and the gate poly layer in the separated state will not have gate oxide reliability issues in the JFET region. When the device is in forward conduction, due to the introduction of the N-conducting layer region on the side of the JFET region that is not covered by the gate poly layer, the forward conduction resistance is reduced, compensating for the conductivity sacrificed by the P+ injection region, so that the on-resistance of the device is basically consistent with the conventional structure. In addition, the structure of partially separating the gate poly layer adopted by the SiC MOSFET device in the present application reduces the overlapping area between the gate poly layer and the source metal layer of the entire device, thereby making the gate-drain capacitance C gd The short-circuit capability of the device of the present invention is improved due to the increase of the P+ injection region, thereby improving the structural reliability of the SiC MOSFET device provided by the present application.

[0017] According to some embodiments of the first aspect of the present application, the N-conducting layer is implanted by N ions, the junction depth is 0.2 μm-0.3 μm, and the doping concentration is 1e17 cm -3 The size of the N-conducting layer in the X direction is 0.5 μm, and the size in the Y direction is 1 μm.

[0018] According to some embodiments of the first aspect of the present application, the size of the P+ injection region in the X direction is 0.5 μm, the size in the Y direction is 1 μm, and the vertical distance from the N-guide layer in the Y direction is 0.5 μm.

[0019] According to some embodiments of the first aspect of the present application, the concentration of the N+ substrate is 1e19cm -3 N-type doping, thickness is 150μm.

[0020] According to some embodiments of the first aspect of the present application, the thickness of the N-epitaxial layer is 12 μm.

[0021] According to some embodiments of the first aspect of the present application, the Pwell region is implanted with Al ions, and the peak concentration of the Pwell region is 4e18cm -3 , the peak concentration depth is 0.5μm.

[0022] According to some embodiments of the first aspect of the present application, the N+ source region is formed into a box-shaped distribution by N ion implantation, with a concentration of 2e19cm -3 .

[0023] According to some embodiments of the first aspect of the present application, the P+ source region is formed into a box-shaped distribution by Al ion implantation, with a concentration of 1e19cm -3 .

[0024] According to some embodiments of the first aspect of the present application, the gate oxide layer is formed by thermal oxidation, and the thickness of the gate oxide layer is 0.05 μm.

[0025] According to some embodiments of the first aspect of the present application, the drain metal is made of Ni metal, the source metal is made of Ti or Al metal, and the gate poly layer is made of polycrystalline silicon.

[0026] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1A partial cross-sectional view of a SiC MOSFET device structure according to an embodiment of the present application;

[0029] Figure 2 A complete structural schematic diagram of a SiC MOSFET device structure according to another embodiment of the present application;

[0030] Figure 3 A comparison curve of a SiC MOSFET device structure according to an embodiment of the present application;

[0031] Figure 4 A comparison curve of a SiC MOSFET device structure according to another embodiment of the present application;

[0032] Figure 5 A comparison curve of a SiC MOSFET device structure according to another embodiment of the present application;

[0033] Figure 6 This is a comparison curve of a SiC MOSFET device structure according to another embodiment of the present application.

[0034] The figures are as follows:

[0035] Source metal layer 101; interlayer dielectric 102; gate poly layer 103; gate oxide layer 104; P+ source region 105; N+ source region 106; Pwell region 107; N- conducting layer 108; P+ injection region 109; JFET region 110; N- epitaxial layer 111; N+ substrate 112; drain metal layer 113. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0037] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] In the description of this application, if there is a description of first or second, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0039] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0040] SiC material is a typical representative of the third generation wide bandgap semiconductor materials. Due to its advantages such as higher critical breakdown electric field strength, higher carrier saturation drift velocity, and higher thermal conductivity, it has become an ideal material for making high-power, high-temperature, high-frequency, and radiation-resistant devices.

[0041] After more than 20 years of rapid development, SiC power devices have achieved impressive results. For example, 600V, 1200V, 1700V, 3300V, and 10kV SiC MOSFET devices have been successfully developed, and 600V, 1200V, and 1700V SiC MOSFET devices have been commercialized. However, there is still a lot of room for improvement in the reliability of SiC power devices.

[0042] Taking SiC MOSFET as an example, on the one hand, the gate-drain capacitance C gd The size of the gate-drain capacitance C affects the dynamic performance of the MOSFET. gd As the parasitic capacitance of MOSFET, it plays a vital role in MOSFET devices. If it is too large, the device will be delayed during the shutdown process. The delay will increase power consumption, thus affecting the dynamic performance of MOSFET.

[0043] On the other hand, the gate oxide reliability of MOSFET will be significantly reduced in reverse bias withstand voltage aging tests such as HTRB and H3TRB, and excessive electric field strength can easily cause the gate oxide layer to break down prematurely, or generate more electron holes to be injected into the gate oxide, resulting in reduced gate oxide reliability.

[0044] Before describing the solution of the present application in detail, the relevant terms are explained.

[0045] SiC: silicon carbide; MOSFET: metal oxide semiconductor field effect transistor; HTRB: high temperature reverse bias; H3TRB: high temperature and high humidity reverse bias; JFET region: junction field effect transistor region; gate poly: gate polysilicon; Pwell region: P-well injection region.

[0046] Reference Figure 1 and Figure 2The present application provides a SiC MOSFET device structure, comprising: a source metal layer 101, an interlayer dielectric 102, a gate poly layer 103, a gate oxide layer 104, a P+ source region 105, an N+ source region 106, a Pwell region 107, an N-conducting layer 108, a P+ injection region 109, a JFET region 110, an N-epitaxial layer 111, an N+ substrate 112 and a drain metal layer 113; the drain metal layer 113, the N+ substrate 112 and the N-epitaxial layer 111 are stacked in sequence from bottom to top; the JFET region 110 is arranged on the upper layer of the N-epitaxial layer 111; the Pwell region 107, the P+ source region 105 and the N+ source region 106 are all arranged on the upper layer of the N-epitaxial layer 111 and are located on both sides of the JFET region 110, and the N+ source region 106 is formed in the Pwell region 107 and is close to both sides of the JFET region 110 , the P+ source region 105 is formed in the Pwell region 107 and is far away from both sides of the JFET region 110, and the N+ source region 106 and the P+ source region 105 are arranged adjacent to each other; the gate oxide layer 104 is located on the upper layer of the JFET region 110 and its two ends are located on the upper layer of part of the N+ source region 106; the gate poly layer 103 is located on the upper layer of part of the gate oxide layer 104; the P+ injection region 109 is arranged at the center of the JFET region 110 and is located at the lower layer of the gate oxide layer 104; the N-conducting layer 108 is arranged in the JFET region 110 corresponding to the area not covered by the gate poly layer 103, and the N-conducting layer 108 overlaps with the Pwell region 107 on one side; the interlayer dielectric 102 covers the upper layers of the gate poly layer 103 and the gate oxide layer 104; the source metal layer 101 covers the upper layer of the interlayer dielectric 102.

[0047] Compared with the conventional SiC MOSFET device structure, the SiC MOSFET provided in the present application introduces a P+ injection region 109 and an N-conducting layer 108. Specifically, when the device is in a blocking state, the gate oxide layer 104 below the gate poly layer 103 in the connected state is shielded by the P+ injection region 109 for electric field, which effectively reduces the electric field strength of the gate oxide layer 104, and the gate poly layer 103 in the separated state will not have gate oxide reliability issues in the JFET region 110. When the device is in forward conduction, due to the introduction of the N-conducting layer 108 region on the side of the JFET region 110 that is not covered by the gate poly layer 103, the forward conduction resistance is reduced, which compensates for the conductivity sacrificed by the P+ injection region 109, so that the on-resistance of the device is basically consistent with the conventional structure. In addition, the structure of separating part of the gate poly layer 103 used in the SiC MOSFET device in the present application reduces the overlapping area between the gate poly layer 103 of the entire device and the source metal layer 101, thereby making the gate-drain capacitance C gdThe short-circuit capability of the device of the present invention is improved due to the addition of the P+ injection region 109, thereby improving the structural reliability of the SiC MOSFET device provided by the present application.

[0048] Specifically, the P+ injection region 109 optimizes the electric field strength of the gate oxide layer 104, and in the present application, a partial separation gate structure is adopted, and the gate poly layer 103 above part of the JFET region 110 is removed. This removed area does not need P+ injection for protection, and the addition of the P+ injection region 109 will increase the on-resistance and reduce the forward conduction performance. The introduction of the P+ center injection is equivalent to reducing the concentration of the JFET region 110, increasing the resistance of the JFET region 110, and thus increasing the overall on-resistance. The JFET region 110 at the position of the N-conducting layer 108 is not provided with a P+ injection region 109, and the addition of the N-conducting layer 108 is equivalent to reducing the resistance of the JFET region 110 and reducing the overall on-resistance. And the N-conducting layer 108 is only provided on one side to ensure the improvement of the short-circuit capability.

[0049] The N-conducting layer 108 is implanted with N ions, with a junction depth of 0.2 μm-0.3 μm and a doping concentration of 1e17 cm -3 , the size of the N-conducting layer 108 in the X direction is 0.5μm, and the size in the Y direction is 1μm. When the device is in forward conduction, the introduction of the N-conducting layer 108 region on the side of the JFET region 110 covered by the gate-free poly layer 103 reduces the forward conduction resistance, making up for the conductivity sacrificed by the P+ injection region 109, so that the on-resistance of the device is basically consistent with the conventional structure.

[0050] The size of the P+ injection region 109 in the X direction is 0.5 μm, the size in the Y direction is 1 μm, and the vertical distance from the N-conducting layer 108 in the Y direction is 0.5 μm. When the device is in the blocking state, the gate oxide layer 104 under the gate poly layer 103 in the connected state is shielded by the P+ injection region 109, which effectively reduces the electric field strength of the gate oxide layer 104, and the gate poly layer 103 in the separated state will not have gate oxide reliability problems in the JFET region 110.

[0051] The concentration of N+ substrate 112 is 1e19 cm -3 The N-type doping has a thickness of 150 μm. The thickness of the N-epitaxial layer 111 is 12 μm. The Pwell region 107 is implanted with Al ions, and the peak concentration of the Pwell region 107 is 4e18 cm -3 The peak concentration depth is 0.5 μm. The N+ source region 106 is formed into a box-shaped distribution by N ion implantation, with a concentration of 2e19 cm -3The P+ source region 105 is formed into a box-shaped distribution by Al ion implantation with a concentration of 1e19cm -3 The gate oxide layer 104 is formed by thermal oxidation, and the thickness of the gate oxide layer 104 is 0.05 μm.

[0052] The drain metal is made of Ni metal, the source metal is made of Ti or Al metal, and the gate poly layer 103 is made of polysilicon. Specifically, the drain metal layer 113 is formed on the back of the N+ substrate 112 by Ni metal sputtering, and the gate poly layer 103 is formed on the gate oxide layer 104 by polysilicon deposition.

[0053] The SiC MOSFET device structure provided in the present application is constructed using the TCAD software Silvaco. In order to ensure that the structure of the embodiment of the present invention has little effect on the performance of the device, a comparison of the static performance of the structure of the embodiment of the present invention and the conventional MOSFET structure is performed below, including on-resistance and reverse breakdown voltage.

[0054] from Figure 3 It can be seen that the specific on-resistance of the conventional structure and the structure of the present invention is basically the same. Figure 3 In the figure, the square legend curve and the circular legend curve represent the conventional MOSFET device and the MOSFET device of the present invention respectively, and are curves of the drain current varying with the drain voltage when the gate voltage is 20V. The slope of the curve represents the on-resistance of the device. It can be seen that the on-resistance of the MOSFET device of the present invention is smaller, and the forward on-resistance is reduced due to the introduction of the N-conducting layer 108 region on the side of the JFET region 110 covered by the gate-free poly layer 103.

[0055] from Figure 4 It can be seen that the square legend curve represents the breakdown characteristic curve of the conventional MOSFET device, and the circular legend curve represents the breakdown characteristic curve of the MOSFET device of the present invention. The reverse breakdown voltage of the conventional structure and the structure of the present invention is about 1400V, and the breakdown voltage of the structure of the present invention is improved compared with the conventional structure.

[0056] When the static parameters of the two are basically the same, the capacitance characteristics of the conventional MOSFET device structure and the SiC MOSFET device structure provided in the present application are simulated. The Silvaco simulation software is also used to apply a 1MHz AC signal. When the drain voltage is 1000V, Figure 5 As shown, the square legend curve and the circular legend curve represent the conventional MOSFET device and the MOSFET device of the present application respectively. When the drain voltage is from 0 to 1000V and the frequency is 1MHz, the gate-drain capacitance C gd The curve of voltage change, C of the structure of the present invention gdThe capacitance is reduced to 50% of that of conventional structures.

[0057] The short-circuit thermoelectric hybrid simulation of the MOSFET device structure is performed by TCAD software Silvaco. Due to the introduction of the P+ injection region 109, under the same short-circuit test conditions: bus voltage 600V, gate voltage 15V, short-circuit time 5us; Figure 5 As shown, the unmarked legend curve and the square legend curve respectively represent the curves of short-circuit current and lattice temperature of conventional MOSFET devices and the MOSFET device of the present invention over time. The short-circuit current of the structure of the present invention is reduced by 10%, and the maximum lattice temperature is reduced by 80K.

[0058] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A SiC MOSFET device structure, characterized in that: include: Source metal layer, interlayer dielectric, gate poly layer, gate oxide layer, P+ source region, N+ source region, Pwell region, N- conducting layer, P+ injection region, JFET region, N- epitaxial layer, N+ substrate and drain metal layer; The drain metal layer, the N+ substrate and the N- epitaxial layer are stacked in sequence from bottom to top; The JFET region is disposed on the upper layer of the N-epitaxial layer; The Pwell region, the P+ source region and the N+ source region are all arranged in the upper layer of the N-epitaxial layer and located on both sides of the JFET region, the N+ source region is formed in the Pwell region and close to both sides of the JFET region, the P+ source region is formed in the Pwell region and far away from both sides of the JFET region, and the N+ source region and the P+ source region are arranged adjacent to each other; The gate oxide layer is located on the upper layer of the JFET region and both ends are located on the upper layer of part of the N+ source region; The gate poly layer is located on the upper layer of a portion of the gate oxide layer; The P+ implantation region is arranged at the center of the JFET region and is located at the lower layer of the gate oxide layer; The N-conducting layer is disposed in the JFET region corresponding to the region not covered by the gate poly layer, and the N-conducting layer overlaps with the Pwell region on one side; The interlayer dielectric covers the gate poly layer and the upper layer of the gate oxide layer; The source metal layer covers the upper layer of the interlayer dielectric; The N-conducting layer is implanted with N ions, with a junction depth of 0.2 μm-0.3 μm and a doping concentration of 1e17 cm -3 , the size of the N-conducting layer in the X direction is 0.5 μm, and the size in the Y direction is 1 μm; The size of the P+ injection region in the X direction is 0.5 μm, the size in the Y direction is 1 μm, and the vertical distance between the P+ injection region and the N-guide layer in the Y direction is 0.5 μm.

2. The SiC MOSFET device structure according to claim 1, characterized in that: The concentration of the N+ substrate is 1e19cm -3 N-type doping, thickness is 150μm.

3. The SiC MOSFET device structure according to claim 1, characterized in that: The thickness of the N-epitaxial layer is 12 μm.

4. The SiC MOSFET device structure according to claim 1, characterized in that: The Pwell region is implanted with Al ions, and the peak concentration of the Pwell region is 4e18cm -3 , the peak concentration depth is 0.5μm.

5. The SiC MOSFET device structure according to claim 1, characterized in that: The N+ source region is formed into a box-shaped distribution by N ion implantation with a concentration of 2e19cm -3 .

6. The SiC MOSFET device structure according to claim 1, characterized in that: The P+ source region is formed into a box-shaped distribution by Al ion implantation, with a concentration of 1e19cm -3 .

7. The SiC MOSFET device structure according to claim 1, characterized in that: The gate oxide layer is formed by thermal oxidation, and the thickness of the gate oxide layer is 0.05 μm.

8. The SiC MOSFET device structure according to claim 1, characterized in that: The drain metal is made of Ni metal, the source metal is made of Ti or Al metal, and the gate poly layer is made of polysilicon.

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