Semiconductor device structure and manufacturing method thereof

Abstract

The present invention relates to a semiconductor device structure and a method for fabricating the same. The semiconductor device structure comprises a semiconductor substrate; a gate structure formed on the substrate and first gate sidewall spacers formed on both sides of the gate structure; a channel region formed in the semiconductor substrate below the gate structure, lightly doped regions on both sides of the channel region, and epitaxially grown source and drain regions on both sides of the lightly doped regions; and at least one diffusion barrier region formed below and adjacent to the source and drain regions, respectively, wherein the doping concentration of the diffusion barrier region is higher than that of the channel region. By embedding heavily doped diffusion barrier structures below and between the source and drain regions on both sides of the substrate channel region and below the lightly doped regions, the distribution of doping impurities used to reduce short channel effects and doping impurities used to form source and drain regions is concentrated in a defined region. This effectively reduces short channel effects while maintaining the device's driving capability (Idsat), achieving a balance between device performance and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and more particularly to a semiconductor device structure and a method for manufacturing the same. Background Art

[0002] As the feature size of semiconductor devices continues to shrink, the short channel effect becomes more and more serious. That is, as the gate length of MOSFET devices decreases, the threshold voltage Vth continues to decrease and the leakage current Ioff increases exponentially.

[0003] In order to reduce the impact of the above-mentioned short channel effect, halo ion implantation (Halo), also known as pocket implantation (Pocket), is often used. By using a larger implantation angle, such as the common 20-50 degree implantation angle, impurities of the same conductivity type as the active area are implanted into the lower side of the lightly doped source and drain (LDD), biased towards the center of the channel region, to suppress the punch-through of the source and drain depletion regions, thereby reducing the short channel effect. Figure 1 shown.

[0004] However, the problem with the halo structure is that the halo formed by ion implantation is widely distributed in space. If the dose of ion implantation is small, the improvement on the punch-through effect is limited, and the improvement effect on the short channel effect is not obvious. If the dose of ion implantation is large, part of the implanted ions will diffuse to the upper channel region, and the ion concentration in the channel region will increase significantly, causing a substantial increase in the threshold voltage Vth, affecting the driving current Idsat of the device, and thus affecting the performance of the device.

[0005] Therefore, as the feature size of semiconductor devices decreases, it is necessary to seek a device structure and manufacturing method to effectively reduce the short channel effect and better ensure device performance. Summary of the Invention

[0006] In order to solve the above problems, the present invention provides a semiconductor device structure, which includes:

[0007] semiconductor substrates;

[0008] A gate structure formed on the substrate and first gate spacers formed on both sides of the gate structure;

[0009] A channel region is formed in the semiconductor substrate below the gate structure, lightly doped regions are formed on both sides of the channel region, and source and drain regions are epitaxially grown on both sides of the lightly doped regions, and at least one diffusion barrier region is formed below the lightly doped region and adjacent to the source and drain regions, wherein the doping concentration of the diffusion barrier region is higher than the doping concentration of the channel region.

[0010] Preferably, the doping element of the diffusion barrier region is selected from phosphorus, arsenic, antimony, boron, boron difluoride, indium, carbon or nitrogen.

[0011] Preferably, the diffusion barrier region has the same doping type as the channel region.

[0012] Preferably, the doping concentration of the diffusion barrier region is 1-2 orders of magnitude higher than the doping concentration of the channel region.

[0013] Preferably, the semiconductor device structure further comprises a halo ring located below the lightly doped region and close to the channel region, and the halo ring has the same conductivity type as the channel region.

[0014] Preferably, the doping element of the diffusion barrier region is selected from phosphorus, arsenic, antimony, boron, boron difluoride, indium, carbon or nitrogen.

[0015] Preferably, the semiconductor device includes a plurality of diffusion barrier regions formed below the lightly doped region and sequentially arranged to the source and drain regions, and the height, thickness, type of doping element and doping concentration of each diffusion barrier region are the same or different.

[0016] Preferably, the semiconductor device includes a first diffusion barrier region and a second diffusion barrier region respectively formed below the lightly doped region and arranged to the source and drain regions, and the doping concentration of the first diffusion barrier region away from the source and drain regions is less than the doping concentration of the second diffusion barrier region close to the source and drain regions.

[0017] Preferably, the semiconductor device includes a first diffusion barrier region, a second diffusion barrier region and a third diffusion barrier region respectively formed below the lightly doped region and arranged in sequence to the source and drain regions, wherein the third diffusion barrier region and the first diffusion barrier region have the same doping element.

[0018] Preferably, the doping elements of the third diffusion barrier region and the first diffusion barrier region are C or N, and the second diffusion barrier region has the same doping type as that of the channel region.

[0019] The present invention further provides a method for preparing a semiconductor device, the method comprising:

[0020] Providing a substrate, wherein the substrate includes an active region and an isolation region;

[0021] forming a gate structure on a substrate;

[0022] forming lightly doped regions on both sides of the channel region in the substrate;

[0023] Forming a groove structure in an area where a source and drain region is to be formed in the substrate by etching;

[0024] forming a heavily doped layer in the trench structure, wherein the doping concentration of the heavily doped layer is greater than the doping concentration of the channel region;

[0025] Etching the formed heavily doped layer to retain only a portion of the heavily doped layer located below the lightly doped region, thereby obtaining a diffusion barrier region and a remaining portion of the trench structure; and

[0026] A source and drain region is formed in the remaining portion of the trench structure.

[0027] Preferably, the method further comprises, before the step of forming source and drain regions in the obtained trench-shaped structure, repeating the steps of forming a heavily doped layer in the trench-shaped structure and etching the heavily doped layer to obtain a plurality of diffusion barrier regions.

[0028] Preferably, the heavily doped layer is formed by selective epitaxial growth.

[0029] Preferably, the method further comprises forming a halo ring below the lightly doped region and near the channel region by ion implantation after forming the source and drain regions.

[0030] The beneficial effects of the present invention are as follows:

[0031] The present invention provides a semiconductor device structure. By embedding a heavily doped diffusion barrier structure below the lightly doped regions on both sides of a substrate channel region and between the source and drain regions, the distribution of doping impurities used to reduce the short channel effect and the doping impurities used to form the source and drain regions are concentrated in a region with a determined position. This can effectively reduce the short channel effect while maintaining the device's driving capability Idsat unchanged, thereby achieving a balance between device performance and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of a semiconductor device with a halo structure in the prior art is shown;

[0033] Figure 2 A schematic structural diagram of a semiconductor device according to a first embodiment of the present invention is shown;

[0034] Figure 3-Figure 7 A schematic flow chart showing a method for fabricating a semiconductor device structure according to a first embodiment of the present invention;

[0035] Figure 8 A schematic structural diagram of a semiconductor device according to a second embodiment of the present invention is shown;

[0036] Figures 9-12 A schematic flow chart showing a method for manufacturing a semiconductor device structure according to a third embodiment of the present invention;

[0037] Figure 13-16 A schematic flow chart of a method for fabricating a semiconductor device structure according to a fourth embodiment of the present invention is shown. DETAILED DESCRIPTION

[0038] In order to illustrate the present invention more clearly, the present invention is further described below in conjunction with the embodiments and drawings. Similar parts in the drawings are represented by the same or similar reference numerals. It should be understood by those skilled in the art that the drawings in this application are schematic and are not drawn strictly in accordance with the dimensions and proportions used for the device layout. The actual layout is more complicated than the schematic diagram, and some structures not involved in the schematic diagram are added, but these common technologies do not affect those skilled in the art to implement the present invention according to the scheme provided by the present invention. It should be understood by those skilled in the art that the embodiments described below are illustrative and not restrictive, and should not be used to limit the scope of protection of the present invention.

[0039] It should be noted that, in the present invention, ordinal numbers such as "first", "second" and "third" are not intended to limit the specific order, but are only used to distinguish the various parts.

[0040] In the present invention, expressions such as "on...", "formed on..." and "disposed on..." may indicate that one layer is directly formed or disposed on another layer, or may indicate that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0041] First embodiment

[0042] Figure 2A schematic diagram of a semiconductor device structure 200 according to a first embodiment of the present invention is shown. Semiconductor device structure 200, for example, a MOS device, includes a semiconductor substrate, such as a silicon substrate; a gate structure 203 formed on the surface of the semiconductor substrate, including a gate insulating layer and a gate electrode; a gate heavy oxide layer 204, a first spacer 205, and a second spacer 206, formed sequentially outside the gate structure; an active region 201 and an isolation structure 211 formed in the substrate; a channel region located below the gate structure in the active region; LDD regions 213 formed on both sides of the channel region; source and drain regions (collectively, the source and drain regions) 212 epitaxially grown on both sides of the LDD region 213; and diffusion barrier regions 216 formed below and adjacent to the source and drain regions on either side of the LDD region. The diffusion barrier regions have a higher doping concentration than the channel region. In this embodiment, the material used to form the source and drain regions, such as silicon (Si) or silicon germanium (SiGe), is selectively epitaxially grown in the trench structure. Specifically, after forming the LDD region in the substrate, the area where the source and drain regions are to be formed is removed by etching to obtain a trench structure. Then, a heavily doped "wedge-shaped" diffusion barrier region is formed in the formed trench structure by selective epitaxial growth combined with etching. For convenience, the heavily doped diffusion barrier region is also referred to as a wedge-shaped structure, a wedge-shaped barrier region, etc. in the context of this application. According to the preparation method of the semiconductor device structure of the present invention described in detail later, the "wedge-shaped" diffusion barrier region has a determined position and a determined concentration. The concentration of impurities in the wedge-shaped structure is higher than the impurity concentration in the active region, and has a blocking effect of delaying the diffusion of impurities in the channel region and the diffusion of impurities in the source and drain regions. Then, the source and drain regions are formed in the trench structure including the wedge structure by, for example, epitaxial growth combined with ion implantation, thereby obtaining the semiconductor device structure of the first embodiment of the present invention. The semiconductor device structure of the first embodiment of the present invention can precisely locate the physical position of the wedge-shaped structure, employing a "self-aligned" technology. Compared to conventional halo ion implantation techniques, the device structure of the present invention concentrates heavily doped regions within the active region, controlling the diffusion of impurities within these heavily doped regions. This allows for higher impurity doping concentrations while improving the penetration effect and preventing diffusion into the channel region. Compared to conventional halo ion implantation techniques, the present invention significantly optimizes the impurity distribution in the region beneath the LDD. The present invention achieves a more concentrated impurity distribution than halo ion implantation, effectively reducing short-channel effects while maintaining device performance.

[0043] Refer to the following Figures 3 to 7 , specifically describing the various steps and preferred embodiments of the preparation process of the semiconductor device structure of the first embodiment of the present invention.

[0044] A semiconductor substrate is provided, in which an active region 201 and an isolation structure 211 are formed. The isolation structure 211 is used to laterally isolate different semiconductor devices. The area outside the isolation structure 101 is the active region 201, which is used to form the semiconductor devices. The isolation structure 211 can be formed using shallow trench isolation (STI), field oxide isolation (FOX), or local oxidation (LOCOS). The method for forming the isolation structure 211 is conventional and will not be described in detail here.

[0045] A gate structure 203 is formed on the surface of a semiconductor substrate, including a gate dielectric layer and a gate electrode layer. For example, the gate dielectric layer and the gate electrode layer are sequentially formed on the substrate surface by photolithography and etching techniques, thereby obtaining the gate structure 203. The gate structure is then re-oxidized (Re-Oxidation) to form a gate heavy oxide layer 204 on both sides of the gate structure. Subsequently, a first sidewall 205, also known as an offset sidewall, is formed outside the gate heavy oxide layer by thin film deposition and etching techniques to obtain a gate stack. Subsequently, ion implantation is performed using the obtained gate stack as a mask to form LDD regions 213 on both sides of the channel region, such as Figure 3 As shown. For PMOS devices, the doping type of the LDD region 213 is p-type, and the doping elements are such as B, BF2, In, etc.; for NMOS devices, the doping type of the LDD region 213 is n-type, and the doping elements are such as P or As, etc. The process and steps for forming LDD are common semiconductor process flows. According to the requirements of the electrical performance and reliability of the device, the order of each process flow may vary. For example, the ion implantation of LDD may be performed immediately after the gate structure etching step, or after the heavy oxidation process. In addition, the first sidewall may adopt a single-layer structure or a multi-layer composite structure. These changes in the order of steps and changes in structure are all conventional technologies and will not be described in detail here.

[0046] Subsequently, a trench structure 217 is formed in the active region 201 by etching. The trench structure is located between the gate stack and the isolation structure, corresponding to the location where the source and drain regions will be formed. Figure 4 The process of forming the trench structure 217 retains the LDD 213 between the source and drain regions and the channel region. Subsequently, a thin film heavily doped layer 218 is formed by a selective epitaxial process such as in-situ doping. Figure 5 The thickness of the thin film heavily doped layer 218 is several angstroms to several microns, and the doping concentration is higher than the doping concentration of the active region. In a preferred embodiment, the doping concentration of the active region is, for example, about 10 15 / cm 3 ~10 16 / cm 3 The doping concentration of the thin film heavily doped layer 218 is 10 15 / cm 3 to 1021 / cm 3 The doping concentration of the active region is preferably 1 to 6 orders of magnitude higher than that of the active region. Subsequently, the thin film heavily doped layer 218 is etched using a dry etching process, leaving only the portion of the heavily doped layer located below the lightly doped region. A heavily doped wedge-shaped barrier region 216 is formed below the LDD 213 in the trench structure, and a remaining trench structure 217 is obtained. Figure 6 The distance between the LDD region and the wedge-shaped barrier region is about several to tens of nanometers. Then, the groove structure is filled by selective epitaxial growth. Figure 7 , a second spacer 206 is formed by thin film deposition and etching technology. The second spacer can also adopt a single-layer structure or a multi-layer composite structure. Then, for example, dopant impurities are implanted by ion implantation to form the source and drain regions 212. According to a preferred embodiment, the groove structure obtained can be filled by in-situ doping selective epitaxial growth to form the source and drain regions 212. Subsequently, an annealing process is performed to activate the implanted ions to obtain the device structure 200 according to the present invention, as shown in FIG. Figure 2 The subsequent processes for forming semiconductor devices include forming metal silicide, forming contact holes, and CMOS processes for forming metal interconnections, which are conventional technologies and will not be described in detail here.

[0047] During the growth of the heavily doped thin film layer 218, in-situ doping is performed using elements such as phosphorus, arsenic, antimony, boron, boron difluoride, indium, carbon, or nitrogen that can delay impurity diffusion in the channel region. In a preferred embodiment, the wedge-shaped barrier region uses impurities of the same conductivity type as the active region in the substrate, and the doping type is the same as that of the active region. For NMOS devices, the doping elements of the heavily doped thin film layer 218 include, but are not limited to, B, BF2, and In; for PMOS devices, the doping elements of the heavily doped thin film layer 218 include, but are not limited to, P, As, and antimony. Thus, the heavily doped diffusion barrier region formed on the side of the source and drain regions 212 near the channel region, having a doping type opposite to that of the source and drain regions, forms a PN junction with the source and drain regions, thereby blocking the diffusion of impurity ions within the source and drain regions into the channel region. In a preferred embodiment, the elements used during the growth of the heavily doped thin film layer 218 that can delay impurity diffusion in the channel region include, but are not limited to, C or N. The C or N in the wedge-shaped barrier region can slow the diffusion of dopant impurities in the channel region, making the impurity distribution in the channel region more concentrated and uniform. This optimizes the impurity distribution during device operation and improves device performance. Furthermore, because the heavily doped barrier region is formed only on the side of the source and drain regions close to the channel region, the depletion region widths of the junctions in other areas of the substrate active region remain the same as those of conventional MOS devices, preventing an increase in source-drain junction leakage current. The present invention's structure, in which the wedge-shaped barrier region is formed below the LDD region, achieves a more concentrated impurity distribution than the prior art halo ion implantation technique, effectively reducing short-channel effects while maintaining device performance.

[0048] Second embodiment

[0049] Figure 8 A schematic structural diagram of a semiconductor device 200' according to a second embodiment of the present invention is shown. The second embodiment is an optimized structure of the first embodiment. Referring to the formation steps of the semiconductor device of the first embodiment, during the growth of the thin-film heavily doped layer 218, in-situ doping is performed with elements capable of delaying impurity diffusion in the channel region, including but not limited to C or N. Dry etching is then used to form a wedge-shaped barrier region 216. After the source and drain region trench structures are filled, and before the second sidewall spacer 206 is deposited and etched, a halo ring 220 is formed by ion implantation. The halo ring 220 is located below the LDD region and near the channel region, and has the same conductivity type as the channel region but a higher doping concentration than the channel region. In a preferred embodiment, the halo ring is positioned between the LDD region and the wedge-shaped diffusion barrier layer, further blocking the diffusion of impurities from the LDD region and the source and drain regions, thereby further simulating the short channel effect. Subsequent process steps remain consistent with those of the first embodiment and will not be described in detail here.

[0050] Taking N-type MOSFET as an example, compared with the traditional halo that only uses B element doping, the C or N in the wedge-shaped barrier region in the structure of this embodiment can slow down the diffusion of B in the halo region and the channel region, making the distribution of B element more concentrated, and the channel impurity distribution is optimized. In the case where the impurity doping concentration injected in the halo stage is 1 to 2 orders of magnitude higher than the doping concentration in the channel region, the heavily doped diffusion barrier region of the present invention makes the B element injected when the halo is formed mainly concentrated below the LDD side, effectively reducing the depletion layer width between the source and drain regions and the substrate, thereby preventing the punch-through effect and improving the direct leakage current between the source and drain. At the same time, because the B element is more concentrated and less diffused into the channel region, the threshold voltage Vth will not increase too much, and the driving current Idsat of the device is improved. The semiconductor device structure provided by the embodiment of the present invention achieves a balance between device performance, such as the driving current Idsat of the device and the leakage current.

[0051] Third embodiment

[0052] Figure 9-12 A schematic flow chart and a schematic structural diagram of a method for fabricating a semiconductor device structure 300 according to a third embodiment of the present invention are shown. The third embodiment is an optimized structure of the first embodiment, wherein the heavily doped diffusion barrier region includes a first diffusion barrier region 316 and a second diffusion barrier region 326 formed below the lightly doped region 313 and extending to the source and drain regions 312. The doping concentration of the first diffusion barrier region 316 on the side away from the source and drain regions is less than the doping concentration of the second diffusion barrier region 326 on the side closer to the source and drain regions. Figure 12 The doping types of the two wedge-shaped regions are the same as the doping type of the channel region, and the doping concentrations are higher than the doping concentration of the channel region.

[0053] refer to Figure 3-6 The device structure of the third embodiment is formed by forming a trench structure at a location where the source and drain regions are to be formed in the substrate, and further comprising selectively epitaxially growing a first thin film heavily doped layer in the trench structure, referring to Figure 5 ; Using dry etching to form a first wedge-shaped structure 316 and the remaining groove 317, reference Figure 6 Then, a second thin film heavily doped layer 318 is selectively grown epitaxially in the remaining trench structure. Figure 9 In a preferred embodiment, when the second thin film heavily doped layer 318 is grown by in-situ doping epitaxial growth, the doping concentration is higher than the doping concentration of the first wedge-shaped region 316 near the channel region. In other words, the doping concentration of the first thin film heavily doped layer formed by the in-situ doping selective epitaxial process is lower than the doping concentration of the second thin film heavily doped layer formed by the in-situ doping selective epitaxial process. The second thin film heavily doped layer 318 is dry-etched to form the second wedge-shaped barrier region 326, see Figure 10The height and thickness of the two wedge-shaped regions 316 and 326 may be consistent or inconsistent, which is determined by the performance parameters of the device. The subsequent process steps of forming the source and drain regions 312 and the second sidewall 206 are similar to those of the first embodiment, see Figure 11-12 , I will not go into details here.

[0054] In a preferred embodiment, the doping elements of the first tapered region 316 and the second tapered region 326 are the same. For N-type MOS devices, the doping impurities of the tapered barrier region include but are not limited to B, BF2, and In; for P-type MOS devices, the doping impurities of the tapered barrier region include but are not limited to P or As. The doping concentration of the second tapered region 326 close to the source and drain regions is higher, for example, at 10 17 / cm 3 to 10 19 / cm 3 , the doping concentration of the first wedge region away from the source and drain regions is low, for example, at 10 16 / cm 3 to 10 18 / cm 3 , the doping concentration of the active region is, for example, 10 15 / cm 3 ~10 16 / cm 3 The second wedge-shaped region 326 near the source and drain regions has a doping type opposite to that of the source and drain regions and a higher doping concentration. The resulting PN junction structure can effectively suppress punch-through of the source and drain depletion regions, reducing the channel effect. At the same time, the reduced doping concentration of the first wedge-shaped region adjacent to the channel region can reduce the diffusion of implanted ions into the upper channel region, avoiding an increase in the ion concentration in the channel region, thereby avoiding an increase in the threshold voltage and effectively improving the performance of the device related to drive current.

[0055] In a preferred embodiment, the halo ring structure shown in the second embodiment can be used in combination with the two wedge-shaped diffusion barrier regions shown in the third embodiment, which are located below the LDD region on both sides of the channel region. The specific formation steps are not described in detail here.

[0056] Fourth embodiment

[0057] Figure 13-16 The flowchart and structure diagram of the method for manufacturing a semiconductor device structure 400 according to the fourth embodiment of the present invention are shown. The fourth embodiment is an optimized structure of the first embodiment, wherein the heavily doped diffusion barrier region includes three heavily doped wedge-shaped regions 436, 426, and 416 arranged in sequence from the source and drain regions to the channel region, and the doping concentrations are higher than the doping concentration of the channel region. Figure 16The three heavily doped wedge-shaped regions form a sandwich structure. The third wedge-shaped region, adjacent to the source / drain region, has the same doping element as the first wedge-shaped region, further away from the source / drain region. The doping dose of the third wedge-shaped region can be consistent with or inconsistent with the first wedge-shaped region. The second wedge-shaped region has a different doping element than the third and first wedge-shaped regions. The heights and thicknesses of the three wedge-shaped regions can be consistent or inconsistent.

[0058] refer to Figure 3-6 and Figure 9-10 The device structure of the fourth embodiment is formed by forming a trench structure at the position where the source and drain regions are to be formed in the substrate, and further comprising selectively epitaxially growing a first thin film heavily doped layer in the trench structure 417, referring to Figure 5 ; Using dry etching to form the first wedge-shaped region 416 and the remaining groove structure, reference Figure 6 Then, a second heavily doped thin film layer is selectively grown epitaxially in the obtained trench structure. Figure 9 ; Using dry etching to form a second wedge-shaped region 426, reference Figure 10 Continue to selectively epitaxially grow the third thin film heavily doped layer 418 in the obtained trench structure, see Figure 13 ; Using dry etching to form a third wedge-shaped region 436, reference Figure 14 The height and thickness of the three wedge-shaped regions 416, 426, and 436 may be consistent or inconsistent, depending on the performance parameters of the device. The subsequent process steps of forming the source and drain regions 412 and the second sidewall spacer 206 are similar to those of the first embodiment, see Figure 11-12 , I will not go into details here.

[0059] In a preferred embodiment, the doping impurities of the in-situ epitaxially grown first and third thin-film heavily doped layers are C or N, and the doping concentrations may be the same or different. The doping impurities of the in-situ epitaxially grown second thin-film heavily doped layer are different from the doping impurities of the first and third thin-film heavily doped layers, including but not limited to B, BF2, In, P, or As, providing the same doping type as the channel region. For example, for an N-type MOS device, the doping impurities of the first and third wedge regions are C or N, while the second wedge region is doped with B. The C or N in the wedge regions can slow B diffusion, confining the distribution of the B element to the second wedge region. Such an impurity distribution is conducive to improving the short channel effect. Similarly, for a P-type MOS device, the doping impurities of the first and third wedge regions are C or N, while the second wedge region is doped with elements including but not limited to P. The C or N in the wedge regions can slow P diffusion, confining the distribution of the P element to the second wedge region. Such an impurity distribution is conducive to improving the short channel effect.

[0060] In a preferred embodiment, the halo ring structure shown in the second embodiment can be used in combination with the wedge-shaped diffusion barrier region shown in the fourth embodiment, and the specific formation steps are not described in detail here.

[0061] In a preferred embodiment, the semiconductor device structure of the present invention may include a plurality of diffusion barrier regions formed below the LDD region side and arranged in sequence to the source and drain regions, the height, thickness, type of doping element and doping dose of each diffusion barrier region being the same or different, and the diffusion barrier structure formed by each diffusion barrier layer being able to delay the diffusion of impurities in the channel region and the diffusion of impurities in the source and drain regions.

[0062] In a preferred embodiment, after forming one or more wedge-shaped barrier regions, when selective epitaxially forming source and drain regions, a material different from that of the substrate can be used to grow the source and drain regions. The different lattice matching of different materials can generate stress that can further improve the performance of the semiconductor device. For N-type MOS devices, the substrate is a Si substrate, including but not limited to silicon carbide (SiC); for P-type MOS devices, the substrate includes but is not limited to silicon germanium (SiGe).

[0063] Fifth embodiment

[0064] A fifth embodiment of the present invention provides a method for preparing a semiconductor device of the present invention. The method comprises providing a substrate, wherein the substrate comprises an active region and an isolation region; forming a gate structure on the substrate; forming LDD regions on both sides of the channel region in the substrate by ion implantation, such as Figure 3 As shown; a groove structure is formed in the area where the source and drain regions are to be formed in the substrate by etching, and the LDD regions on both sides of the channel region are retained, as shown Figure 4 As shown; forming a heavily doped layer in the groove structure, as Figure 5 As shown; the heavily doped layer is etched, leaving only the heavily doped layer located below the LDD region, to obtain a heavily doped diffusion barrier region and the remaining groove structure, as shown Figure 6As shown; source and drain regions are formed in the remaining groove-shaped structure by epitaxial growth, thereby obtaining the semiconductor device according to the present invention. The above-mentioned processes and steps for forming the LDD region are common semiconductor process flows. According to the requirements of the electrical performance and reliability of the device, the order of each process flow may be changed. For example, the ion implantation for forming the LDD region may be performed immediately after the gate structure etching step, or after the heavy oxidation process. In addition, the first sidewall and the second sidewall may respectively adopt a single-layer structure or a multi-layer composite structure. These changes in the order of steps and changes in structure are all conventional technologies and will not be described in detail here. The process for forming the source and drain regions may adopt a selective epitaxial growth method to fill the groove-shaped structure and then perform doping by ion implantation to obtain the source and drain regions, or may adopt an in-situ doping selective epitaxial growth method to obtain the source and drain regions. Those skilled in the art may select a corresponding process according to the performance and parameters of the device to obtain the semiconductor device structure of the present invention.

[0065] According to a preferred embodiment, the above steps of forming a heavily doped layer in the trench structure and etching to form a heavily doped diffusion barrier region can be repeated to obtain a semiconductor device including a plurality of heavily doped diffusion barrier regions. Figure 9-10 and Figure 13-14 .

[0066] According to a preferred embodiment of the present invention, after the step of forming the source and drain regions, a halo ring can be formed below the LDD region near the channel region by ion implantation. Figure 8 As a preferred embodiment, the position of the halo ring corresponds to the position between the LDD region and the wedge-shaped barrier region.

[0067] The method of the present invention embeds a heavily doped wedge-shaped structure below the side of the light LDD region, and the impurity distribution of the wedge-shaped structure is concentrated. This can effectively reduce the short channel effect while maintaining the driving capability Idsat of the device unchanged, thereby achieving a balance between device performance and power consumption.

[0068] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in this field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. A semiconductor device structure, characterized in that: The semiconductor device structure comprises: semiconductor substrates; A gate structure formed on the substrate and first gate spacers formed on both sides of the gate structure; A channel region below the gate structure, lightly doped regions on both sides of the channel region, and epitaxially grown source and drain regions on both sides of the lightly doped regions are formed in the semiconductor substrate, and a plurality of diffusion barrier regions are formed below the lightly doped regions and adjacent to the source and drain regions, wherein the doping concentration of the diffusion barrier regions is higher than the doping concentration of the channel region. The multiple diffusion barrier regions include a first diffusion barrier region, a second diffusion barrier region and a third diffusion barrier region arranged in sequence to the source and drain regions, wherein the third diffusion barrier region and the first diffusion barrier region have the same doping element, the doping element of the third diffusion barrier region and the first diffusion barrier region is C or N, and the second diffusion barrier region has the same doping type as the channel region.

2. The semiconductor device structure according to claim 1, wherein: The doping element of the diffusion barrier region is selected from phosphorus, arsenic, antimony, boron, boron difluoride, indium, carbon or nitrogen.

3. The semiconductor device structure according to claim 1, wherein: The doping concentration of the diffusion barrier region is 1-2 orders of magnitude higher than the doping concentration of the channel region.

4. The semiconductor device structure according to claim 1, wherein: The semiconductor device structure further includes a halo ring located below the lightly doped region and close to the channel region, wherein the halo ring has the same conductivity type as the channel region.

5. The semiconductor device structure according to claim 4, wherein: The doping element of the diffusion barrier region is selected from phosphorus, arsenic, antimony, boron, boron difluoride, indium, carbon or nitrogen.

6. A method for preparing a semiconductor device, characterized in that: The method includes: Providing a substrate, wherein the substrate includes an active region and an isolation region; forming a gate structure on a substrate; forming lightly doped regions on both sides of the channel region in the substrate; Forming a groove structure in an area where a source and drain region is to be formed in the substrate by etching; forming a heavily doped layer in the trench structure, wherein the doping concentration of the heavily doped layer is greater than the doping concentration of the active region; Etching the formed heavily doped layer to retain only a portion of the heavily doped layer located below the lightly doped region, thereby obtaining a first diffusion barrier region and a remaining trench structure; Repeating the steps of forming a heavily doped layer in the trench structure and etching the formed heavily doped layer to obtain a second diffusion barrier region and a third diffusion barrier region, wherein the third diffusion barrier region and the first diffusion barrier region have the same doping element, the doping element of the third diffusion barrier region and the first diffusion barrier region is C or N, and the second diffusion barrier region has the same doping type as the channel region; and A source and drain region is formed in the remaining trench structure.

7. The method for preparing a semiconductor device according to claim 6, wherein: The heavily doped layer is formed by selective epitaxial growth.

8. The method for preparing a semiconductor device according to claim 6, wherein: The method further includes forming a halo ring below the lightly doped region and near the channel region by ion implantation after forming the source and drain regions.

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