Gate lead structure of trench gate super-junction device and preparation method thereof

Abstract

The application provides a preparation method of a gate lead-out structure of a trench gate super-junction device, in the preparation method of the gate lead-out structure of the trench gate super-junction device, the application fills the same type of doped polysilicon as in the polysilicon gate structure in a contact hole of a lead-out source region and a polysilicon gate structure, forms a polysilicon spacer (Poly Spacer) on two sidewalls of the contact hole of the lead-out source region, and forms a polysilicon plug (Poly Plug) in the contact hole of the lead-out gate structure, so that the process is simple and stable, and the large-scale production capacity of the existing power production line is used. Since the source region (Source) has only a small range of polysilicon spacers (Poly Spacer), the contact between NP and PP is not obviously affected, and then the application can break through the production capacity bottleneck on the basis of ensuring the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a gate lead-out structure and its fabrication method for a trench gate superjunction device. Background Technology

[0002] Superjunction devices combine the advantages of low switching loss of VDMOS and low on-state loss of IGBT (Insulated Gate Bipolar Transistor), resulting in their widespread application due to their superior performance. The superjunction in a superjunction device consists of alternating P-type thin layers (P-pillars) and N-type thin layers (N-pillars) formed in a semiconductor substrate. By utilizing the charge balance between the P-type and N-type thin layers to reduce the surface electric field in bulk (Resurf) technology, the reverse breakdown voltage of the device can be improved while maintaining a low on-resistance.

[0003] With technological advancements, superjunction devices are becoming increasingly widely used. As semiconductor device integration requirements increase and device cell sizes shrink, device structures have evolved to meet these demands, leading to the emergence of trench gate structures that enable faster switching speeds and lower switching losses. Superjunction devices typically employ a process where a superjunction trench is formed in an N-type epitaxial layer (such as an N-type silicon epitaxial layer), followed by filling the trench with a P-type epitaxial layer (such as a P-type silicon epitaxial layer). The trench gate comprises a trench formed in the semiconductor substrate, a gate dielectric layer formed within the trench, and a polysilicon gate.

[0004] As semiconductor device dimensions shrink, the critical dimension (CD) of contact holes or contact trenches also decreases, posing greater challenges to the filling process. Currently, the mainstream superjunction products have a step size of 5–11 μm, and the source lead-out structure size is generally above 2.5 μm, which can be filled using hot-aluminum filling. However, since the gate structure size is typically 0.75–1.5 μm, its gate lead-out contact holes are generally around 0.5 μm, making hot-aluminum filling impossible. To address this issue, the conventional approach is to introduce a tungsten plug process. A complete tungsten plug (W-Plug) is formed at the small contact hole of the gate structure, and a tungsten spacer (W-Spacer) is formed at the large contact hole of the source structure. Then, the contact hole is filled using hot-aluminum filling, simultaneously forming a gate metal line that contacts the tungsten plug of the gate structure.

[0005] Tungsten plug (W-Plug) technology is a mature process for small linewidths, but for power device production lines with larger linewidths, it often suffers from insufficient capacity, creating a serious capacity bottleneck. In particular, as the pitch of superjunctions continues to shrink and the trench opening becomes smaller, a slower fill rate is required to achieve a good filling effect, which significantly increases the capacity requirements and costs.

[0006] Another method that avoids the tungsten plug (W-Plug) process involves adding a photolithography step, utilizing the extension of polysilicon to bring out the gate structure and form larger contact holes. The disadvantage of this approach is the increased number of photomask layers. Furthermore, for reliability, an additional GFOX photomask is often required to define the GFOX region. The contact hole (CT) area at the polysilicon gate lead-out requires placement on a thick GFOX oxide layer, significantly increasing costs and limiting the application of this approach. Summary of the Invention

[0007] The purpose of this invention is to provide a gate lead structure and its fabrication method for a trench gate superjunction device, in order to solve the problem that with the continuous shrinking of the current superjunction pitch and trench opening, a slower filling rate is required to achieve a good filling effect. The mature tungsten plug (W-Plug) process under small linewidth is often insufficient for power device production lines with larger linewidths, forming a serious production capacity bottleneck.

[0008] To solve the above technical problems, the present invention provides a gate lead-out structure for a trench gate superjunction device, comprising:

[0009] A semiconductor substrate having a superjunction structure formed thereon;

[0010] A trench gate structure is formed within a superjunction structure in the semiconductor substrate;

[0011] Source region, surrounding both sides of the trench gate;

[0012] An interlayer dielectric layer is formed on the top surface of the trench gate and source regions;

[0013] A contact hole is formed in the interlayer dielectric layer, which penetrates the interlayer dielectric layer to form a first contact hole for the source region and a second contact hole for the trench gate.

[0014] A polycrystalline silicon spacer layer is located on the two sidewalls of the first contact hole in the source region;

[0015] A polysilicon plug is located inside the second contact hole of the trench gate.

[0016] Furthermore, the polysilicon forming the spacer layer and plug is polysilicon with the same doped structure as that inside the trench gate.

[0017] Meanwhile, to solve the above-mentioned technical problems, this invention also provides a method for fabricating the gate lead-out structure of a trench gate superjunction device based on the above-mentioned trench gate superjunction device gate lead-out structure, including:

[0018] The N-type thin layer is etched to form a trench, and a gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trench to form a gate structure through the two film layers. The trench is filled with the polysilicon.

[0019] The source region of the trench gate superjunction device is formed on both sides of the gate structure within the substrate;

[0020] An interlayer dielectric layer is deposited on the N-type semiconductor substrate and the trench surface, and a first contact hole and a first contact hole are etched in the interlayer dielectric layer. The contact hole is used to lead out the polysilicon gate structure and the source region.

[0021] ~4KN type doped polysilicon is deposited on the surface of the interlayer dielectric layer and the inner wall of the contact hole, and the ~4KN type doped polysilicon at least fills the second contact hole of the gate structure;

[0022] The deposited N-type doped polysilicon is subjected to back-side dry etching to form a polysilicon spacer layer on the two sidewalls of the first contact hole in the source region, and a polysilicon plug is formed in the second contact hole of the gate structure.

[0023] Metal deposition is performed to form a front metal layer, and photolithography is used to etch the front metal layer to form a metal bus, thus completing the fabrication of the trench gate superjunction device.

[0024] Furthermore, the polysilicon spacer layer and the polysilicon plug are doped polysilicon, and are doped polysilicon of the same type as that in the trench gate, which can be N-type doped, P-type doped or As-type doped.

[0025] Furthermore, the contact hole is rectangular or square in shape.

[0026] Furthermore, the size of the first contact hole in the source region is greater than 2.5 μm.

[0027] Furthermore, the second contact hole of the lead-out trench gate structure has a size of 0.05 to 2 μm.

[0028] Furthermore, the formation area of ​​the contact hole is defined by photolithography, and the corresponding contact hole is formed at the lead-out position of the gate structure.

[0029] Furthermore, the polysilicon plug extends downwards between the interlayer dielectric layer and the polysilicon gate, thereby connecting to the polysilicon gate.

[0030] Furthermore, the source region is formed using ion implantation and annealing processes. The formation area of ​​the source region is defined by photolithography. In the device cell region, the source region and the side of the corresponding gate structure are self-aligned.

[0031] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0032] In the method for fabricating the gate lead-out structure of a trench gate superjunction device proposed in this invention, firstly, a superjunction structure composed of alternating P-type and N-type thin layers is formed in an N-type semiconductor substrate; the N-type thin layer is etched to form a trench, and a gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trench, forming a gate structure through the two film layers, and the trench is filled with the polysilicon; the source region of the trench gate superjunction device is formed on the substrate surface; next, an interlayer dielectric layer is deposited on the N-type semiconductor substrate and the trench surface, and the corresponding source region and gate structure in the interlayer dielectric layer are etched to form a first contact hole and a first contact hole, respectively, to lead out the source region and the polysilicon gate structure; finally, ~4KN-type doped polysilicon of the same type as that in the gate structure is deposited on the inner wall of the contact hole; the deposited N-type doped polysilicon is subjected to back-side dry etching to form a polysilicon spacer layer on the two sidewalls of the first contact hole leading out the source region, and a polysilicon plug is formed in the second contact hole leading out the gate structure. This invention utilizes polysilicon with the same doping type as the trench gate to form a polysilicon plug for the gate structure of a trench-gate superjunction device. The process is simple and stable, and it leverages existing large-scale production capacity on power lines. Since the source region only has a small polysilicon spacer layer, it does not significantly affect the contact between the NP and PP. Therefore, this invention can overcome production capacity bottlenecks on a large scale while ensuring device performance. Attached Figure Description

[0033] Figure 1 This is a schematic flowchart illustrating the fabrication method of the gate lead-out structure of a trench gate superjunction device according to an embodiment of the present invention.

[0034] Figures 2a-2h This is a schematic diagram of the fabrication process of the gate lead-out structure of the trench gate superjunction device according to an embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, with technological advancements, the use of superjunction devices is becoming increasingly widespread. The integration requirements for semiconductor devices are increasing, device cell sizes are gradually decreasing, and device structures are changing accordingly. Devices with trench gate structures, capable of achieving faster switching speeds and lower switching losses, have emerged. Superjunction devices typically employ a method of forming superjunction trenches in an N-type epitaxial layer, such as an N-type silicon epitaxial layer, and then filling the superjunction trenches with a P-type epitaxial layer, such as a P-type silicon epitaxial layer. The trench gate comprises a trench formed in a semiconductor substrate, a gate dielectric layer formed within the trench, and a polysilicon gate.

[0036] As semiconductor device dimensions shrink, the critical dimension (CD) of contact holes or contact trenches also shrinks, posing greater challenges to the filling process. Currently, the mainstream superjunction products have a step size of 5–11 μm, and the source lead-out structure size is generally above 2.5 μm, which can be filled using hot-aluminum technology. However, since the gate structure size is typically 0.75–1.5 μm, its gate lead-out contact holes are generally around 0.5 μm, making hot-aluminum filling impossible. To address this issue, the conventional approach is to introduce a tungsten plug process. A complete tungsten plug (W-Plug) is formed at the small contact hole of the gate structure, and a tungsten spacer (W-Spacer) is formed at the large contact hole of the source structure. Then, the contact hole is filled using hot-aluminum technology, simultaneously forming a gate metal line that contacts the tungsten plug of the gate structure. While the W-Plug process is a mature technology for small linewidths, it often suffers from insufficient capacity for power device production lines with larger linewidths, creating a significant production bottleneck. In particular, as the pitch of superjunctions continues to shrink and the trench opening continues to shrink, a slower filling rate is required to achieve a good filling effect, which significantly increases the occupation of production capacity and the cost.

[0037] Another method that avoids the tungsten plug (W-Plug) process involves adding a photolithography step, utilizing the extension of polysilicon to bring out the gate structure and form larger contact holes. The disadvantage of this approach is the increased number of photomask layers. Furthermore, for reliability, an additional GFOX photomask is often required to define the GFOX region. The contact hole (CT) area at the polysilicon gate lead-out requires placement on a thick GFOX oxide layer, significantly increasing costs and limiting the application of this approach.

[0038] Therefore, the purpose of this invention is to provide a gate lead structure and its fabrication method for a trench gate superjunction device, in order to solve the problem that with the continuous shrinking of the current superjunction pitch and trench opening, a slower filling rate is required to achieve a good filling effect. The mature tungsten plug (W-Plug) process under small linewidth is often insufficient for power device production lines with larger linewidths, forming a serious production capacity bottleneck.

[0039] For example, refer to Figure 1 As shown, the gate lead-out structure and its fabrication method for the trench gate superjunction device include the following steps:

[0040] Step S100: An N-type semiconductor substrate is provided, and a superjunction structure composed of alternating P-type and N-type thin layers is formed in the N-type semiconductor substrate;

[0041] Step S200: The N-type thin layer is etched to form a trench, and a gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trench to form a gate structure through the two film layers. The trench is filled with the polysilicon.

[0042] Step S300: Form the source region of the trench gate superjunction device on both sides of the gate structure within the substrate;

[0043] Step S400: Deposit an interlayer dielectric layer on the N-type semiconductor substrate and the trench surface, and etch a first contact hole and a first contact hole in the interlayer dielectric layer. The contact hole is used to lead out the polysilicon gate structure and the source region.

[0044] Step S500: Deposit ~4KN type doped polysilicon on the surface of the interlayer dielectric layer and the inner wall of the contact hole, wherein the ~4KN type doped polysilicon at least fills the second contact hole of the gate structure.

[0045] Step S600: Perform back-side dry etching on the deposited N-type doped polysilicon to form a polysilicon spacer layer on the two sidewalls of the first contact hole in the source region and a polysilicon plug in the second contact hole of the gate structure.

[0046] In step S700, metal deposition is performed to form a front metal layer, and photolithography is performed on the front metal layer to form a metal bus, thus completing the fabrication of the trench gate superjunction device.

[0047] In the method for fabricating the gate lead-out structure of a trench gate superjunction device proposed in this invention, firstly, a superjunction structure composed of alternating P-type and N-type thin layers is formed in an N-type semiconductor substrate; the N-type thin layer is etched to form a trench, and a gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trench, forming a gate structure through the two film layers, and the trench is filled with the polysilicon; the source region of the trench gate superjunction device is formed on the substrate surface; next, an interlayer dielectric layer is deposited on the N-type semiconductor substrate and the trench surface, and the corresponding source region and gate structure in the interlayer dielectric layer are etched to form a first contact hole and a first contact hole, respectively, to lead out the source region and the polysilicon gate structure; finally, ~4KN-type doped polysilicon of the same type as that in the gate structure is deposited on the inner wall of the contact hole; the deposited N-type doped polysilicon is subjected to back-side dry etching, forming a polysilicon spacer layer on the two sidewalls of the first contact hole leading out the source region, and forming a polysilicon plug in the second contact hole leading out the gate structure. This invention utilizes polysilicon with the same doping type as the trench gate to form a polysilicon plug for the gate structure of a trench-gate superjunction device. The process is simple and stable, and it leverages existing large-scale production capacity on power lines. Since the source region only has a small polysilicon spacer layer, it does not significantly affect the contact between the NP and PP. Therefore, this invention can overcome production capacity bottlenecks on a large scale while ensuring device performance.

[0048] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the fabrication method for the gate lead-out structure of a trench gate superjunction device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0049] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] The fabrication method of the gate lead-out structure of the trench gate superjunction device provided by this invention will be described in detail below. For details, please refer to... Figures 2a to 2h As shown, Figures 2a to 2h This is a schematic diagram illustrating the fabrication process of the gate lead-out structure of a trench gate superjunction device according to an embodiment of the present invention; wherein, the fabrication method of the gate lead-out structure of the trench gate superjunction device may include the following steps:

[0051] In step S100, please refer to the following for details. Figure 2a An N-type semiconductor substrate 1 is provided, which serves as an operating platform for subsequent processes to generate trench-gate superjunction devices. The material of the N-type semiconductor substrate is selected from single-crystal silicon, polycrystalline silicon, or amorphous silicon; the N-type semiconductor substrate may also be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon carbon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors; the N-type semiconductor substrate may also be other semiconductor materials such as a ceramic substrate (e.g., alumina), quartz, or glass substrate. Exemplarily, in this embodiment of the invention, the N-type semiconductor substrate is a silicon substrate.

[0052] An N-type semiconductor epitaxial layer (N-epi) 2 is formed on the upper surface of the N-type semiconductor substrate 1. In this embodiment, the N-type semiconductor epitaxial layer is an N-type silicon epitaxial layer. A body region 3 is formed using ion implantation and annealing processes. Multiple periodically alternating superjunction trenches are formed in the N-type semiconductor epitaxial layer 2 by photolithography definition and etching. Due to the limitations of the etching process, the sides of the superjunction trenches deviate from the ideal vertical structure and have an inclination angle of less than 90 degrees, making the cross-sectional structure of the superjunction trenches in the width direction an inverted trapezoidal shape that is wider at the top and narrower at the bottom. The superjunction trenches are filled to form a P-type thin layer 4, and the filling is achieved by depositing multiple layers of undoped polysilicon. The N-type semiconductor epitaxial layers between each P-type thin layer form an N-type thin layer, and the P-type thin layers and the N-type thin layers are arranged alternately to form a superjunction structure.

[0053] In step S200, please refer to the following for details. Figure 2bA gate trench 5 is formed by photolithography and etching on the N-type thin layer on which the superjunction is formed and the surface is flat. The width of the gate trench at the lead-out position of the gate structure meets the requirements for forming a contact hole. Exemplarily, in this embodiment, a gate oxide layer 6 is deposited on the inner wall of the gate trench 5 using a thermal oxidation process. The polysilicon gate 7 is filled in the gate trench, and the trench gate structure is composed of the gate oxide layer formed on the inner wall of the gate trench and the polysilicon gate. Exemplarily, in this embodiment, the polysilicon gate filled in the gate trench is ~4KN-type doped polysilicon.

[0054] In step S300, please refer to the following for details. Figure 2c Source regions 8 are formed on both sides of the trench gate in the N-type semiconductor substrate. Exemplarily, in this embodiment, the source regions 8 are formed using ion implantation and annealing processes. The formation region of the source regions 8 is defined by photolithography. In the device cell region, the source regions 8 and the corresponding sidewalls of the gate structure are self-aligned. In this embodiment of the invention, the N-type semiconductor substrate 1 includes a trench gate structure region B located to the right of the dashed line BB' and a source region A located to the left of the dashed line BB', separated by the dashed line BB'.

[0055] In step S300, please refer to the following for details. Figure 2d An interlayer dielectric layer 9 is deposited on the upper surface of the trench filled with ~4KN-type doped polysilicon on the N-type semiconductor substrate.

[0056] In step S400, please refer to the following for details. Figure 2e A first contact hole 10 and a first contact hole 11 are formed in the interlayer dielectric layer using photolithography. The first contact hole and the first contact hole are used to lead out the source region and the polysilicon gate structure, respectively. For example, in this embodiment, the shape of the contact hole is rectangular or square, the size of the first contact hole 10 leading out the source region is greater than 2.5 μm, and the size of the second contact hole 11 leading out the trench gate structure ranges from 0.05 μm to 2 μm. Specifically, the size of the second contact hole 11 can be 0.05μm, 0.1μm, 0.15μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.0μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, and 2.0μm.

[0057] In step S500, please refer to the following for details. Figure 2fDoped polysilicon 12 is deposited on the surface of the interlayer dielectric layer 9, inside the first contact hole 10 of the source region, and in the second contact hole 11 of the gate trench structure. Exemplarily, in this embodiment, the filled doped polysilicon is ~4KN-type doped polysilicon, which can be N-type, P-type, or As-type doped polysilicon, and the ~4KN-type doped polysilicon at least completely fills the second contact hole of the gate trench structure.

[0058] In step S600, please refer to the following for details. Figure 2g The deposited N-type doped polysilicon is subjected to back-side dry etching to form a polysilicon spacer layer 13 on the two sidewalls of the first contact hole in the source region and a polysilicon plug 14 in the second contact hole of the gate structure.

[0059] In step S700, please refer to the following for details. Figure 2h Metal is deposited in the contact hole and on the surface of the interlayer dielectric layer to form a front metal layer 15. The front metal layer is then photolithographically etched to form a metal bus. For example, in this embodiment, a surface passivation layer is deposited, the back side is thinned, and the back side metal is deposited. These are necessary steps to complete the fabrication of the trench gate superjunction device.

[0060] In summary, this invention proposes a method for fabricating the gate lead-out structure of a trench gate superjunction device. First, a superjunction structure consisting of alternating P-type and N-type thin layers is formed within an N-type semiconductor substrate. The N-type thin layers are etched to form trenches. A gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trenches, forming a gate structure through the two layers. The trenches are filled with the polysilicon. A source region of the trench gate superjunction device is formed on the substrate surface. Next, an interlayer dielectric layer is deposited between the N-type semiconductor substrate and the trench surface. Etching is performed at the corresponding source region and gate structure locations within the interlayer dielectric layer to form first contact holes and first contact apertures, respectively, to lead out the source region and the polysilicon gate structure. Finally, ~4K N-type doped polysilicon of the same type as that in the gate structure is deposited on the inner wall of the contact holes. The deposited N-type doped polysilicon is subjected to back-side dry etching to form polysilicon spacer layers on the two sidewalls of the first contact hole leading out the source region, and a polysilicon plug is formed in the second contact hole leading out the gate structure. This invention utilizes polysilicon with the same doping type as the trench gate to form a polysilicon plug for the gate structure of a trench-gate superjunction device. The process is simple and stable, and it leverages existing large-scale production capacity on power lines. Since the source region only has a small polysilicon spacer layer, it does not significantly affect the contact between the NP and PP. Therefore, this invention can overcome production capacity bottlenecks on a large scale while ensuring device performance.

[0061] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0062] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0063] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A gate lead-out structure for a trench gate superjunction device, characterized in that, The gate lead-out structure includes: A semiconductor substrate having a superjunction structure formed thereon; A trench gate structure is formed within a superjunction structure in the semiconductor substrate; Source region, surrounding both sides of the trench gate; An interlayer dielectric layer is formed on the top surface of the trench gate and source regions; A contact hole is formed in the interlayer dielectric layer, which penetrates the source region of the interlayer dielectric layer and a trench gate second contact hole is formed therethrough; wherein, the first contact hole is formed between two source regions, which are located on both sides of the superstructure trench, and the superstructure trench is formed on an N-type semiconductor epitaxial layer formed on the upper surface of the semiconductor substrate; A polycrystalline silicon spacer layer is located on the two sidewalls of the first contact hole in the source region; A polysilicon plug is located inside the second contact hole of the trench gate. The polysilicon forming the polysilicon spacer layer and the polysilicon plug is polysilicon of the same type as that in the trench gate; wherein, the size of the first contact hole of the source region is greater than 2.5 μm, and the size of the second contact hole of the trench gate structure is 0.05~1 μm.

2. A method for fabricating a gate lead-out structure based on the trench gate superjunction device of claim 1, characterized in that, The preparation method includes: An N-type semiconductor substrate is provided, and a superjunction structure consisting of alternating P-type and N-type thin layers is formed within the N-type semiconductor substrate; The N-type thin layer is etched to form a trench, and a gate oxide layer and polysilicon are sequentially deposited on the inner surface of the trench to form a gate structure through the two film layers. The trench is filled with the polysilicon. The source region of the trench gate superjunction device is formed on both sides of the gate structure within the substrate; An interlayer dielectric layer is deposited between the N-type semiconductor substrate and the trench surface, and a first contact hole and a second contact hole are etched in the interlayer dielectric layer. The formed contact holes are used to lead out the polysilicon gate structure and the source region. The first contact hole is formed between the two source regions, which are located on both sides of the superstructure trench. The superstructure trench is formed on the N-type semiconductor epitaxial layer formed on the upper surface of the semiconductor substrate. ~4K N-type doped polysilicon is deposited on the surface of the interlayer dielectric layer and the inner wall of the contact hole, wherein the ~4K N-type doped polysilicon at least fills the second contact hole of the gate structure; The deposited N-type doped polysilicon is subjected to back-side dry etching to form a polysilicon spacer layer on the two sidewalls of the first contact hole in the source region, and a polysilicon plug is formed in the second contact hole of the gate structure. Metal deposition is performed to form a front metal layer, and photolithography is used to etch the front metal layer to form a metal bus, thus completing the fabrication of the trench gate superjunction device. The polysilicon spacer layer and polysilicon plug are doped polysilicon, and are doped polysilicon of the same type as that inside the trench gate, namely N-type doping or P-type doping.

3. The method for fabricating the gate lead-out structure of the trench gate superjunction device as described in claim 2, characterized in that, The contact hole is rectangular or square in shape.

4. The method for fabricating the gate lead-out structure of the trench gate superjunction device as described in claim 2, characterized in that, The formation area of ​​the contact hole is defined by photolithography, and the corresponding contact hole is formed at the lead-out position of the gate structure.

5. The method for fabricating the gate lead-out structure of the trench gate superjunction device as described in claim 2, characterized in that, The polysilicon plug passes downwards between the interlayer dielectric layer and the polysilicon gate, thereby connecting to the polysilicon gate.

6. The method for fabricating the gate lead-out structure of the trench gate superjunction device as described in claim 2, characterized in that, The source region is formed using ion implantation and annealing processes. The formation area of ​​the source region is defined by photolithography. In the device cell region, the source region and the corresponding gate structure are self-aligned side by side.

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