Power factor correction control device, method and welding machine power supply

Abstract

The present invention provides a power factor correction control device, method and welding machine power supply. The above-mentioned control device includes a sampling unit, which samples the input voltage, output voltage and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal and an output current sampling signal respectively; a voltage compensation unit, which calculates a compensation voltage signal based on the output voltage sampling signal and a preset voltage reference value; a voltage loop output unit, which calculates a voltage loop output signal based on the output current sampling signal and the compensation voltage signal; a voltage balancing unit, which calculates multiple duty cycle signals based on the input voltage sampling signal and the voltage loop output signal; and generates a pulse width modulation wave based on the duty cycle signal to control the conduction and disconnection of corresponding switch components respectively. The present invention is conducive to maintaining the bus voltage stability of the PFC circuit and improving the stability of the welding performance of the welding machine.

Description

Technical Field

[0001] The present invention relates to the technical field of welding machines, and in particular to a power factor correction control device and method and a welding machine power supply. Background Art

[0002] In welding power supply applications, a PFC (Power Factor Correction) circuit is often incorporated to reduce grid pollution, increase active power, and reduce switching transistor stress. As PFC technology matures, its advantages in addressing electromagnetic interference and electromagnetic compatibility issues, as well as its wide operating voltage range, are becoming increasingly apparent.

[0003] To improve converter control performance, reduce the impact of temperature drift on analog device precision, and facilitate host computer communication and human-machine interaction, PFC circuits typically employ digital control. Because welding power supplies frequently operate under short-circuit and no-load conditions, high dynamic performance requirements are placed on the PFC circuit.

[0004] For PFC circuit, refer to Figure 1 The three-level PFC circuit can realize the voltage between points A and B at 0V and 0.5U according to the on and off of the switch tubes Q1 and Q2. out and U out Switch between. out Represents the output voltage of the PFC circuit. Compared with the two-level PFC circuit, the three-level PFC circuit has certain advantages in that the voltage stress of the switching devices is relatively small and the cost of the switching devices is lower.

[0005] The output voltage of the three-level PFC circuit in current welding power supplies, i.e., the bus voltage, cannot be kept stable. This adversely affects the regulation of the subsequent converter, resulting in poor welding performance and an inability to guarantee guaranteed results. For example, if the input voltage suddenly drops, the subsequent converter will not be able to meet the required power, resulting in arc interruption during welding. Summary of the Invention

[0006] In view of this, the present invention provides a power factor correction control device, method and welding machine power supply, so that the output voltage of the PFC circuit remains stable, thereby keeping the regulation effect of the subsequent converter stable, which is conducive to ensuring that the welding machine achieves good welding effect.

[0007] According to one aspect of the present invention, a power factor correction control device is provided for controlling a power factor correction circuit in a welding power supply. The control device is electrically connected to the power factor correction circuit, and the power factor correction circuit includes at least one switch component. The control device includes:

[0008] a sampling unit for sampling the input voltage, output voltage, and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively;

[0009] A voltage compensation unit is connected to the sampling unit and calculates a compensation voltage signal according to the output voltage sampling signal and a preset voltage reference value;

[0010] a voltage loop output unit, connected to the sampling unit and the voltage compensation unit respectively, and calculating a voltage loop output signal according to the output current sampling signal and the compensation voltage signal;

[0011] The voltage balancing unit is connected to the sampling unit and the voltage loop output unit respectively, and calculates multiple duty cycle signals based on the input voltage sampling signal and the voltage loop output signal; and generates a pulse width modulation wave based on the duty cycle signal to control the corresponding switching components to be turned on and off respectively; the duty cycle signal corresponds to the switching component one by one.

[0012] Optionally, the voltage loop output unit includes:

[0013] an output current feedforward subunit, connected to the sampling unit, and configured to calculate an output current feedforward signal based on the output current sampling signal;

[0014] The voltage loop output unit calculates a voltage loop output signal according to the output current feedforward signal and the compensation voltage signal.

[0015] Optionally, the pressure balancing unit includes:

[0016] A phase-locked loop subunit is connected to the sampling unit, and the phase-locked loop subunit obtains a phase-locked loop output signal through phase-locked loop calculation based on the input voltage sampling signal;

[0017] The voltage balancing unit calculates and obtains multiple duty cycle signals according to the phase-locked loop output signal and the voltage loop output signal.

[0018] Optionally, the power factor correction circuit further includes a first inductor, wherein the first inductor is connected to one of the switch components;

[0019] The sampling module is further configured to sample the current of the first inductor to obtain an inductor current sampling signal; and the voltage balancing unit further includes:

[0020] The current bias calculation subunit obtains a current reference signal based on the phase-locked loop output signal and the voltage loop output signal; calculates a duty cycle reference signal based on the inductor current sampling signal, the preset current bias signal, and the current reference signal; and calculates multiple duty cycle signals based on the duty cycle reference signal.

[0021] Optionally, the power factor correction circuit further includes a first capacitor and a second capacitor connected in series, wherein a first end of the first capacitor is connected to the first inductor and the switch component respectively, and a second end of the second capacitor is connected to the switch component; and the voltage balancing unit further includes:

[0022] The duty cycle difference calculation subunit samples the voltages of the first capacitor and the second capacitor respectively to obtain a first capacitor voltage sampling signal and a second capacitor voltage sampling signal; calculates a duty cycle difference value based on the first capacitor voltage sampling signal and the second capacitor voltage sampling signal; and the current bias calculation subunit calculates the duty cycle signals corresponding to each switching tube according to the duty cycle reference signal and the duty cycle difference value.

[0023] According to another aspect of the present invention, a power factor correction control method is provided, which is controlled by any of the above-mentioned power factor correction control devices, and includes the following steps:

[0024] S110, sampling the input voltage, output voltage, and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively;

[0025] S120, calculating a compensation voltage signal according to the output voltage sampling signal and a preset voltage reference value;

[0026] S130, calculating a voltage loop output signal according to the output current sampling signal and the compensation voltage signal;

[0027] S140, calculating multiple duty cycle signals based on the input voltage sampling signal and the voltage loop output signal; and generating pulse width modulation waves based on the duty cycle signals to respectively control the on and off of corresponding switch components; the duty cycle signals correspond one to one to the switch components.

[0028] Optionally, step S130 includes:

[0029] Calculating an output current feedforward signal according to the output current sampling signal; and

[0030] A voltage loop output signal is calculated based on the output current feedforward signal and the compensation voltage signal.

[0031] Optionally, step S140 includes:

[0032] Based on the input voltage sampling signal, a phase-locked loop output signal is obtained through phase-locked loop calculation;

[0033] A plurality of duty cycle signals are calculated based on the phase-locked loop output signal and the voltage loop output signal.

[0034] Optionally, the power factor correction circuit further includes a first inductor, wherein the first inductor is connected to one of the switch components;

[0035] Step S110 further includes:

[0036] Sampling the current of the first inductor to obtain an inductor current sampling signal;

[0037] Step S140 further includes:

[0038] Obtaining a current reference signal according to the phase-locked loop output signal and the voltage loop output signal;

[0039] Calculating a duty cycle reference signal according to the inductor current sampling signal, the preset current bias signal and the current reference signal; and

[0040] Multiple duty cycle signals are calculated based on the duty cycle reference signal.

[0041] Optionally, the power factor correction circuit further includes a first capacitor and a second capacitor connected in series, wherein a first end of the first capacitor is connected to the first inductor and a switch component respectively, and a second end of the second capacitor is connected to the switch component; step S140 further includes:

[0042] Sampling the voltages of the first capacitor and the second capacitor respectively to obtain a first capacitor voltage sampling signal and a second capacitor voltage sampling signal;

[0043] Calculating a duty cycle difference value according to the first capacitor voltage sampling signal and the second capacitor voltage sampling signal; and

[0044] The duty cycle corresponding to each switch tube is calculated based on the duty cycle reference signal and the duty cycle difference value.

[0045] Optionally, the obtaining a phase-locked loop output signal by calculating through a phase-locked loop based on the input voltage sampling signal includes:

[0046] When the input voltage is detected to cross a zero point, a first count value of the first counter and a second count value of the second counter are respectively acquired;

[0047] Calculating a voltage period of a power grid access based on the first count value;

[0048] Using the voltage period as the period of a second counter, performing proportional integral calculation based on the second count value to obtain a voltage phase of the power grid;

[0049] A phase-locked loop calculation is performed according to the voltage cycle and voltage phase of the access power grid and the input voltage sampling signal to obtain a phase-locked loop output signal.

[0050] Optionally, the obtaining a phase-locked loop output signal by calculating through a phase-locked loop based on the input voltage sampling signal includes:

[0051] Obtaining a difference between the second count value and the previous voltage phase;

[0052] It is determined whether the difference is less than a preset period. If so, a proportional integral calculation is performed to obtain the current voltage phase of the power grid.

[0053] Optionally, step S130 includes:

[0054] extracting an alternating current from the output current of the power factor correction circuit, sampling the alternating current, and obtaining an output current sampling signal;

[0055] The output current sampling signal is filtered using a notch filter to obtain an output current feedforward signal.

[0056] According to another aspect of the present invention, a welding power supply is provided, comprising any one of the above-mentioned power factor correction control devices.

[0057] The beneficial effects of the present invention compared with the prior art are:

[0058] The power factor correction control device, method, and welding machine power supply provided by the present invention utilize a preset voltage reference value to perform voltage compensation on an output voltage sampling signal, sample and filter the output current to obtain an output current feedforward signal, thereby adding load feedforward to the PFC circuit for regulation, thereby subsequently generating a PWM wave for regulating the on / off of the switching tube. This helps maintain the bus voltage stability of the PFC circuit, thereby maintaining the stability of the regulation effect of the subsequent converter, ensuring that the welding machine achieves a good welding effect, and improving the stability of its welding performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0060] Figure 1 A schematic structural diagram of a power factor correction circuit disclosed in one embodiment of the present invention;

[0061] Figure 2 A schematic diagram of the framework structure of a power factor correction control device disclosed in one embodiment of the present invention;

[0062] Figure 3 A schematic diagram of the principle of a power factor correction control device disclosed in one embodiment of the present invention;

[0063] Figure 4 A schematic diagram of a flow chart of frequency-locked loop calculation in a power factor correction control device disclosed in one embodiment of the present invention;

[0064] Figure 5 Schematic diagram of PI calculation in the frequency-locked loop calculation disclosed in one embodiment of the present invention;

[0065] Figure 6 A schematic diagram of a phase-locked loop calculation process in a power factor correction control device disclosed in an embodiment of the present invention;

[0066] Figure 7 A schematic diagram of PI calculation in the above-mentioned phase-locked loop calculation disclosed in one embodiment of the present invention;

[0067] Figure 8 The input current waveform when the current loop calculation in the prior art does not add a preset current bias signal;

[0068] Figure 9 The input current waveform after adding a preset current bias signal to the current loop calculation in one embodiment of the present invention;

[0069] Figure 10 This is a schematic structural diagram of a welding power supply disclosed in one embodiment of the present invention;

[0070] Figure 11 A schematic flow chart of a power factor correction control method disclosed in one embodiment of the present invention;

[0071] Figure 12 A schematic flow chart of a power factor correction control method disclosed in another embodiment of the present invention;

[0072] Figure 13 A schematic flow chart of a power factor correction control method disclosed in another embodiment of the present invention;

[0073] Figure 14 Schematic diagram of the flow of step S140 in the power factor correction control method disclosed in another embodiment of the present invention;

[0074] Figure 152 is a flow chart of step S141 in a power factor correction control method disclosed in another embodiment of the present invention. DETAILED DESCRIPTION

[0075] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, materials, devices, etc. may be adopted. In other cases, well-known technical solutions are not shown or described in detail to avoid blurring various aspects of the present disclosure. The same reference numerals in the figures represent the same or similar structures, and their detailed descriptions will be omitted.

[0076] The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including," "having," and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0077] The present invention discloses a power factor correction control device for controlling a power factor correction circuit, namely, a PFC circuit, in a welding power supply. The power factor correction control device is electrically connected to the PFC circuit. The PFC circuit includes at least one switching component. In a specific implementation, the switching component can be a switching transistor, namely, a switching transistor.

[0078] like Figure 1 As shown, an embodiment of the present invention discloses a PFC circuit. The PFC circuit includes a rectifier bridge, a first inductor L1, a second inductor L2, a first switch tube Q1, a second switch tube Q2, a first capacitor C1, a second capacitor C2, a fifth diode D5 and a sixth diode D6. Figure 1 In this embodiment, the rectifier bridge includes a first diode D1, a second diode D2, and a third diode D3 and a fourth diode D4 connected in series. Each two diodes are connected in series and then in parallel. The PFC circuit is connected to a power grid, with one pole of the grid connected between the first diode D1 and the second diode D2, and the other pole of the grid connected between the third diode D3 and the fourth diode D4.

[0079] refer to Figure 1The rectifier bridge is connected to the first end of the first inductor L1 and the first end of the second inductor L2. The second end of the first inductor L1 is connected to the anode of the fifth diode D5 and the first electrode of the first switch Q1. The cathode of the fifth diode D5 is connected to the first end of the first capacitor C1.

[0080] The second electrode of the first switching transistor Q1, the first electrode of the second switching transistor Q2, the second end of the first capacitor C1, and the first end of the second capacitor C2 are connected. The second end of the second inductor L2 is respectively connected to the second electrode of the second switching transistor Q2 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the second end of the second capacitor C2.

[0081] like Figure 2 and Figure 3 As shown, one embodiment of the present invention discloses a power factor correction control device. The control device includes a sampling unit 21, a voltage compensation unit 22, a voltage loop output unit 23, and a voltage balancing unit 24. The sampling unit 21 is connected to a PFC circuit 25 and the voltage compensation unit 22, respectively. The voltage loop output unit 23 is connected to the sampling unit 21 and the voltage compensation unit 22, respectively. The voltage balancing unit 24 is connected to the sampling unit 21, the voltage loop output unit 23, and the PFC circuit 25, respectively.

[0082] The sampling unit 21 is configured to sample the input voltage, output voltage, and output current of the PFC circuit 25 to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively; and to sample the current of the first inductor to obtain an inductor current sampling signal. Specifically, the sampling unit 21 samples the input voltage of the PFC circuit 25 to obtain an input voltage sampling signal. The sampling unit 21 samples the output voltage of the PFC circuit 25 to obtain an output voltage sampling signal. The sampling unit 21 samples the output current of the PFC circuit 25 to obtain an output current sampling signal.

[0083] For example, the input voltage can be converted into a small voltage signal through differential sampling, and then sampled and conditioned by a second-order Bessel circuit to obtain an input voltage sampling signal. Similarly, the output voltage sampling can also be achieved through differential sampling. The output current sampling can be achieved by using Figure 3 The current sampling of the first inductor can be realized by the current Hall sensor (i.e. Figure 3 The CS in the sample is converted into a small voltage signal, and then sampled and conditioned by a second-order Bessel circuit to obtain an inductor current sampling signal. The specific implementation process of the sampling unit can be referenced to the existing technology, and this embodiment will not be repeated.

[0084] The voltage compensation unit calculates a compensated voltage signal based on the output voltage sampling signal and a preset voltage reference value. The voltage loop output unit calculates a voltage loop output signal based on the output current sampling signal and the compensated voltage signal. For example, the compensated voltage signal can be obtained by performing a PI calculation on the difference between the preset voltage reference value and the output voltage sampling signal. The voltage loop output signal can be obtained by adding the result obtained by processing the output current sampling signal to the compensated voltage signal.

[0085] For example, refer to Figure 3 , the output voltage sampling signal is expressed as u o , the preset voltage reference value is expressed as u ref , then the compensation voltage signal can be based on u ref with u o The difference between the two is calculated by PI (proportional integral, proportional integral regulation circuit), that is, (u ref -u o ) is input to a PI calculation unit and outputs a compensation voltage signal u mo The specific implementation process of PI calculation can be achieved by referring to the existing technology, and will not be described in detail in this embodiment.

[0086] The voltage balancing unit calculates multiple duty cycle signals based on the input voltage sampling signal and the voltage loop output signal. Based on these duty cycle signals, it generates pulse width modulation waves to control the on and off of corresponding switching components. The duty cycle signals correspond one-to-one to the switching components.

[0087] Specifically, the voltage loop output unit includes an output current feedforward subunit. The output current feedforward subunit is connected to the sampling unit. The output current feedforward subunit is configured to calculate an output current feedforward signal based on the output current sampling signal. The voltage loop output unit then calculates a voltage loop output signal based on the output current feedforward signal and the compensation voltage signal.

[0088] For example, continue to refer to Figure 3 , extract the AC current from the output current of the power factor correction circuit, sample the AC current, and obtain the output current sampling signal i o In specific implementation, in order to reduce the impact of load current feedforward on the steady-state operation of the circuit and reduce costs, a coupling magnetic ring can be used to collect the AC component of the load current, that is, the output current. The output current feedforward subunit outputs the current sampling signal i o With the preset feedforward coefficient k f After multiplication, the output current feedforward signal I is obtained by filtering using a notch filter. fThe voltage loop output unit will output the current feedforward signal I f and compensation voltage signal u mo Add together to get the voltage loop output signal u m .

[0089] That is, since there is power pulsation in the output of the PFC circuit, the output current needs to be notched after acquisition to filter out the twice power frequency component of 100Hz. Then multiply it by the preset feedforward coefficient k f The controller then participates in the loop control. When the load suddenly increases, the output current increases. Due to the addition of output current feedforward regulation, the duty cycle of the PWM wave output by the control device also increases, effectively avoiding the problem of output voltage drop caused by loading. Correspondingly, when unloading, the output current decreases and the duty cycle decreases, preventing the problem of bus voltage overshoot and damage to the switching tube.

[0090] This embodiment uses a preset voltage reference value to perform voltage compensation on the output voltage sampling signal, samples and filters the output current to obtain an output current feedforward signal, and implements load feedforward regulation in the PFC circuit to subsequently generate a PWM wave for regulating the on / off of the switch tube. This helps maintain bus voltage stability, thereby stabilizing the output voltage of the PFC circuit, and further stabilizing the regulation effect of the subsequent converter. It also avoids the problem of damage to the switch tube in the circuit due to bus voltage fluctuations, helps ensure that the welding machine achieves good welding results, and improves the stability of its welding performance.

[0091] In this embodiment, the voltage balancing unit includes a phase-locked loop subunit, a duty cycle difference calculation subunit, and a current bias calculation subunit. The phase-locked loop subunit and the duty cycle difference calculation subunit are respectively connected to the current bias calculation subunit. The phase-locked loop subunit is also connected to the sampling unit.

[0092] The phase-locked loop (PLL) subunit calculates a PLL output signal based on the input voltage sampling signal. The current bias calculation subunit obtains a current reference signal based on the PLL output signal and the voltage loop output signal. Furthermore, the current bias calculation subunit calculates a duty cycle reference signal based on the inductor current sampling signal, a preset current bias signal, and the current reference signal. Furthermore, multiple duty cycle signals are calculated based on the duty cycle reference signal. The calculation principle of the duty cycle reference signal is a current loop.

[0093] The duty cycle difference calculation subunit samples the voltages of the first and second capacitors to obtain first and second capacitor voltage sampling signals, respectively. The duty cycle difference calculation subunit calculates the duty cycle difference value based on the first and second capacitor voltage sampling signals. The calculation principle of the duty cycle difference calculation subunit is a voltage grading loop.

[0094] The current bias calculation subunit calculates the duty cycle signal corresponding to each switch tube according to the duty cycle reference signal and the duty cycle difference value.

[0095] In addition to the aforementioned addition of the compensation voltage signal and the output current feedforward signal, this embodiment utilizes the input voltage sampling signal to generate a phase-locked loop output signal using a phase-locked loop (PLL) to serve as a reference waveform for the current of the first inductor to follow. This further helps maintain bus voltage stability, thereby stabilizing the output voltage of the PFC circuit and, in turn, maintaining a stable regulation effect of the subsequent converter.

[0096] For example, continue to refer to Figure 3 , grid voltage U in After sampling, the input voltage sampling signal is obtained. The input voltage sampling signal is calculated by PLL (Phase Lock Loop) to generate a phase-locked loop output signal i with the same frequency and phase as the grid voltage. PLL , as a reference waveform of the current of the first inductor.

[0097] Specifically, when the input voltage zero crossing is detected, the phase-locked loop (PLL) subunit obtains the first count value of the first counter and the second count value of the second counter. Based on the first count value, the voltage period of the connected power grid is calculated. This voltage period is used as the period of the second counter, and a proportional-integral calculation is performed based on the second count value to obtain the grid voltage phase. A PLL calculation is performed based on the grid voltage period, voltage phase, and the input voltage sampling signal to obtain a PLL output signal.

[0098] The above zero-crossing detection link is mainly aimed at the grid voltage. When the grid voltage is detected to change from negative to positive or from positive to negative, the flag bit is changed and the value of the relevant timer is recorded at the same time for the subsequent frequency-locked loop calculation and phase-locked loop calculation. The frequency-locked loop is the pre-link of the phase-locked loop, which mainly provides frequency information, that is, calculates the grid voltage frequency to ensure that the current reference signal i ref The frequency of the phase-locked loop is consistent with the grid voltage. The phase-locked loop mainly provides phase information to ensure that the phase of the phase-locked loop output signal is consistent with the grid voltage. The following describes the calculation of the frequency-locked loop and the phase-locked loop respectively:

[0099] In the frequency-locked loop (FLL) calculation, timer Tim5 is used for counting. When the grid voltage crosses zero, the count value is extracted and the timer is reset, thereby obtaining the count value within a power frequency cycle. The power frequency cycle of the grid can be obtained based on the main frequency of the carrier chip of the control device and the frequency division of timer Tim5. Taking the Stm32f103 chip as an example, its main frequency is 72MHz and the power frequency cycle is 50Hz. Setting the timer division to 1 means that the timer count period within a power frequency cycle is 14400.

[0100] refer to Figure 4 In this embodiment, the frequency locked loop calculation includes the following steps:

[0101] S410, timer Tim5 starts counting.

[0102] S420: Detect that the input voltage crosses zero.

[0103] S430, obtaining the Tim5 count value as a frequency locked loop input.

[0104] S440, reset timer Tim5.

[0105] S450: Determine whether the Tim5 count value is within a preset range. The preset range can be determined based on the frequency of the grid voltage. If the Tim5 count value is within the preset range, it indicates that it is reasonable to use it as the grid voltage.

[0106] If yes, then go to step S460: perform PI calculation. Otherwise, jump to step S420.

[0107] refer to Figure 5 After obtaining the Tim5 count value, the error PI calculation is performed to ensure that the PI calculation result follows the count value. That is, after subtracting the PI calculation result from the new count value, the PI calculation is performed again, thereby reducing the impact of sampling jitter. The PI calculation result is used as the voltage cycle of the power grid.

[0108] Similarly, reference Figure 6 and Figure 7 In the phase-locked loop (PLL) calculation, timer Tim4 is used for counting, and its period is the output of the FLL. When a zero crossing is detected, the count value of Tim4 can be regarded as the phase difference between Tim4 and the grid voltage. This phase information is extracted and substituted into the PI calculation for tracking. It is important to note that the PLL calculation process includes a validity check to determine whether the difference between the phase input value and the PLL output is less than a preset period. If it is not satisfied, the sampled data is considered incorrect and the count value is re-read to reduce sampling error and improve sampling accuracy.

[0109] refer to Figure 6 , the phase-locked loop calculation includes the following steps:

[0110] S610, timer Tim4 starts counting.

[0111] S620: Detect that the input voltage crosses zero.

[0112] S630, obtaining the Tim4 count value as a phase input.

[0113] S640, the FLL output value is used as the Tim4 cycle.

[0114] S650: Determine whether the difference between the phase input value and the PLL output is less than a preset period. That is, obtain the difference between the second count value and the previous voltage phase, and determine whether the difference is less than a preset period.

[0115] If yes, then go to step S660: perform PI calculation. Otherwise, jump to step S620.

[0116] refer to Figure 7 After obtaining the Tim4 count value, the PI calculation is performed so that the PI calculation result follows the count value. That is, after subtracting the PI calculation result from the new count value, the PI calculation is performed again. The PI calculation result is used as the voltage phase of the power grid.

[0117] The frequency-locked loop (FLL) and phase-locked loop (PLL) calculations disclosed in this embodiment utilize the high-frequency clock of the control device's carrier chip to count power grid cycles and phases, rather than cumulatively counting during calculation interruptions. This ensures calculation accuracy. For example, if the FLL were to accumulate counts once per calculation cycle, with a set calculation cycle of 20kHz, the count value within one power frequency cycle would be only 400, significantly reducing calculation accuracy.

[0118] In this embodiment, the voltage loop output signal u m and the phase-locked loop output signal i PLL Multiply and take the absolute value to get the current reference signal i ref The inductor current sampling signal is represented by i L , the preset current bias signal is represented by i bias , the current bias calculation subunit will i L 、i bias And the current reference signal i ref As the input of a current loop, the current loop calculation is performed to obtain the duty cycle reference signal d. For example, (i ref +i bias -i L ) is input to the PI controller of the current loop for PI calculation to obtain the duty cycle reference signal d.

[0119] From the above analysis, we can see that: Where w represents the frequency of the phase-locked loop output signal, It is assumed that the current of the first inductor tracks the current reference signal i ref , then: Among them, i o Indicates the output current, U in 、U o are the effective values ​​of the input voltage and the output voltage respectively.

[0120] It can be seen from this that the output current feedforward signal I f and the output current i o is proportional to Therefore, for example, the feedforward coefficient k is preset f The value can be

[0121] according to Figure 3 It can be seen that:

[0122] K p (i ref +i bias -i L )=d*T c (1),

[0123] Where, d is the duty cycle reference signal, K p is the preset current loop gain coefficient, T c The period of the timer corresponding to the PWM wave generated in the carrier chip of the control device can be generated by preset. The preset current loop gain coefficient K can be adjusted p To control the dynamic performance of the current loop.

[0124] In the continuous current mode (CCM) of the inductor, the input voltage and output voltage of the PFC circuit need to meet the following requirements:

[0125]

[0126] Combining the above formulas (1) and (2), and making the DC quantity and AC quantity equal, we can know that:

[0127]

[0128] get:

[0129] From this we can know that the preset current bias signal i bias The value of .

[0130] From the above formula (1) and formula (2), it can be seen that when the input voltage crosses zero, the duty cycle needs to be increased to close to 1 to provide a larger step-up ratio and output a higher voltage. However, the algorithm in the existing technology that does not add a preset current bias signal is difficult to achieve this goal, and it is easy to have the following problems: Figure 8 The current zero-crossing distortion phenomenon is shown in Figure 2. Figure 9 After adding the preset current bias signal, the present application increases the duty cycle at the zero-crossing point, thus achieving the goal of full duty cycle output at the voltage zero-crossing point, thereby effectively solving the problem of zero-crossing distortion, reducing the harmonic content of the input current in the current loop calculation, and improving the stability of the PFC circuit bus voltage. Figure 8 and Figure 9 The horizontal axis represents time, and the vertical axis represents current value. Figure 8 and Figure 9 The input current waveform in FIG is for illustrative purposes only and does not represent the actual waveform.

[0131] In this embodiment, the duty cycle difference calculation subunit uses the first capacitor voltage sampling signal u c1 and the second capacitor voltage sampling signal u c2 , perform voltage balancing loop calculation, that is, input into the PI controller to obtain the duty cycle difference Δd, and then add and subtract the duty cycle difference Δd from the duty cycle reference signal d, respectively, to obtain the first duty cycle signal d1 corresponding to the first switch tube Q1 and the second duty cycle signal d2 corresponding to the second switch tube Q2. Then, the PWM generation module based on the carrier chip of the control device converts the calculated duty cycle signal into a PWM (pulse width modulation) wave to control the corresponding switch tube to turn on or off. The PWM generation module generates a PWM wave corresponding to the period of the timer. Among them, the above-mentioned duty cycle signal refers to the ratio of the time occupied by the high level within one period.

[0132] This embodiment uses the capacitor voltage balancing technique to ensure that the voltages on the two output capacitors are consistent, thereby ensuring that the switches experience the same voltage stress. This prevents damage to any one switch due to excessive voltage, thereby improving the reliability and stability of the PFC circuit.

[0133] For example, when the voltage on the second capacitor C2 is higher than the voltage on the first capacitor C1, that is, U c2 -U c1 is positive, and the error Δd after being amplified by the PI controller is also positive. At this time, d2>d1, and the charging time of C1 by the subsequent converter of the welding power supply (i.e., the phase-shifted full-bridge inverter circuit) is longer than that of C2. The voltage of C2 decreases and the voltage of C1 increases until the voltages of the two capacitors are equal.

[0134] It should be noted that the preset voltage reference value, preset current bias signal, and preset period disclosed above in this application can all be preset and can be set by those skilled in the art as needed. This application does not impose any restrictions on this.

[0135] like Figure 10 As shown, one embodiment of the present invention discloses a welding power supply. The welding power supply includes a power factor correction control device 26 (i.e., a PFC control device) disclosed in any of the above embodiments. The detailed structural features and advantages of the power factor correction control device 26 can be found in the description of the above embodiments and will not be repeated here.

[0136] refer to Figure 10 The welding power supply also includes an EMI (Electro Magnetic Interference) suppression module 31, a PFC circuit 25, a phase-shifted full-bridge inverter circuit 32, a phase-shifted full-bridge inverter control module 33, a high-frequency transformer 34, a rectifier module 35, an auxiliary power supply 36, and a fan 37. The EMI suppression module is connected to the power grid, and the rectifier module is connected to the welding load. The connection relationship between the EMI suppression module, the PFC circuit, the PFC control device, the phase-shifted full-bridge inverter circuit, the phase-shifted full-bridge inverter control module, the high-frequency transformer, the rectifier module, the auxiliary power supply, and the fan can be referred to. Figure 10 , this embodiment will not be described in detail.

[0137] An embodiment of the present invention further provides a power factor correction control method, which is controlled by the power factor correction control device disclosed in any of the above embodiments. The detailed structural features and advantages of the power factor correction control device can be referred to the description of the above embodiments, which will not be repeated here. Figure 11 As shown, the control method includes the following steps:

[0138] S110 , sampling the input voltage, output voltage, and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively.

[0139] S120 , calculating and obtaining a compensation voltage signal according to the output voltage sampling signal and a preset voltage reference value.

[0140] S130 , calculating and obtaining a voltage loop output signal according to the output current sampling signal and the compensation voltage signal.

[0141] S140 , calculating multiple duty cycle signals based on the input voltage sampling signal and the voltage loop output signal; and generating pulse width modulation waveforms based on the duty cycle signals to control the on and off of corresponding switching components. The duty cycle signals correspond one to one with the switching components.

[0142] For example, in step S110, the input voltage can be converted into a small voltage signal through differential sampling, and then sampled and conditioned by a second-order Bessel circuit to obtain an input voltage sampling signal. Similarly, the sampling of the output voltage can also be achieved through differential sampling. The sampling of the output current can be achieved by using Figure 3 The current sampling of the first inductor can be realized by the current Hall sensor (i.e. Figure 3 The CS in the sample is converted into a small voltage signal, and then sampled and conditioned by a second-order Bessel circuit to obtain an inductor current sampling signal. The specific implementation process of the sampling process can be referenced to the existing technology, and this embodiment will not be repeated.

[0143] For example, in this embodiment, the compensation voltage signal can be obtained by performing a PI calculation on the difference between a preset voltage reference value and the output voltage sampling signal. The voltage loop output signal can be obtained by adding the compensation voltage signal to the result obtained by processing the output current sampling signal.

[0144] like Figure 12 As shown, in another embodiment of the present application, another power factor correction control method is disclosed. Figure 11 Based on the corresponding embodiment, step S120 includes:

[0145] S121 , obtaining a first output voltage signal according to the output voltage sampling signal and a preset voltage reference value.

[0146] S122: Perform proportional integral calculation on the first output voltage signal to obtain a compensation voltage signal.

[0147] Step S130 includes:

[0148] S131, extracting the AC current from the output current of the power factor correction circuit, sampling the AC current, and obtaining an output current sampling signal.

[0149] S132, filtering the output current sampling signal using a notch filter to obtain an output current feedforward signal.

[0150] S133: Calculate and obtain a voltage loop output signal based on the output current feedforward signal and the compensation voltage signal.

[0151] For example, refer to Figure 3 , the output voltage sampling signal is expressed as u o , the preset voltage reference value is expressed as u ref , then the compensation voltage signal can be based on u ref with u oThe difference between the two is calculated by PI (proportional integral, proportional integral regulation circuit), that is, (u ref -u o ) is input to a PI calculation unit and outputs a compensation voltage signal u mo .

[0152] Continue to refer Figure 3 , extract the AC current from the output current of the power factor correction circuit, sample the AC current, and obtain the output current sampling signal i o In specific implementation, in order to reduce the influence of load current feedforward on the steady-state operation of the circuit and reduce the cost, a coupling magnetic ring can be used to collect the AC component of the load current, that is, the output current. o With the preset feedforward coefficient k f After multiplication, the output current feedforward signal I is obtained by filtering using a notch filter. f In step S133, the output current feedforward signal I f and compensation voltage signal u mo Add together to get the voltage loop output signal u m .

[0153] That is, since there is power pulsation in the output of the PFC circuit, the output current needs to be notched after acquisition to filter out the twice power frequency component of 100Hz. Then multiply it by the preset feedforward coefficient k f The controller then participates in the loop control. When the load suddenly increases, the output current increases. Due to the addition of output current feedforward regulation, the duty cycle of the PWM wave output by the control device also increases, effectively avoiding the problem of output voltage drop caused by loading. Correspondingly, when unloading, the output current decreases and the duty cycle decreases, preventing the problem of bus voltage overshoot and damage to the switching tube.

[0154] This embodiment uses a preset voltage reference value to perform voltage compensation on the output voltage sampling signal, samples and filters the output current to obtain an output current feedforward signal, and implements load feedforward regulation in the PFC circuit to subsequently generate a PWM wave for regulating the on / off of the switch tube. This helps maintain bus voltage stability, thereby stabilizing the output voltage of the PFC circuit, and further stabilizing the regulation effect of the subsequent converter. It also avoids the problem of damage to the switch tube in the circuit due to bus voltage fluctuations, helps ensure that the welding machine achieves good welding results, and improves the stability of its welding performance.

[0155] In another embodiment of the present application, another power factor correction control method is disclosed. Figure 13 As shown in the above Figure 11On the basis of the corresponding embodiment, step S110 is replaced by step S111:

[0156] The input voltage, output voltage and output current of the power factor correction circuit are sampled to obtain an input voltage sampling signal, an output voltage sampling signal and an output current sampling signal respectively; and the current of the first inductor is sampled to obtain an inductor current sampling signal.

[0157] refer to Figure 13 In this embodiment, step S140 includes:

[0158] S141 , obtaining a phase-locked loop output signal through phase-locked loop calculation based on the input voltage sampling signal.

[0159] S142, obtaining a current reference signal according to the phase-locked loop output signal and the voltage loop output signal.

[0160] S143, calculating a duty cycle reference signal based on the inductor current sampling signal, the preset current bias signal and the current reference signal. And

[0161] S144: Calculate multiple duty cycle signals based on the duty cycle reference signal, and generate pulse width modulation waves based on the duty cycle signals to control the corresponding switch components to turn on and off.

[0162] For example, continue to refer to Figure 3 , grid voltage U in After sampling, the input voltage sampling signal is obtained. The input voltage sampling signal is calculated by PLL (Phase Lock Loop) to generate a phase-locked loop output signal i with the same frequency and phase as the grid voltage. PLL , as a reference waveform of the current of the first inductor.

[0163] Specifically, when the input voltage zero crossing is detected, a first count value of the first counter and a second count value of the second counter are obtained. Based on the first count value, the voltage period of the connected power grid is calculated. This voltage period is used as the period of the second counter, and a proportional integral calculation is performed based on the second count value to obtain the voltage phase of the power grid. A phase-locked loop calculation is performed based on the voltage period and phase of the connected power grid, and the input voltage sampling signal, to obtain a phase-locked loop output signal.

[0164] The above zero-crossing detection link is mainly aimed at the grid voltage. When the grid voltage is detected to change from negative to positive or from positive to negative, the flag bit is changed and the value of the relevant timer is recorded at the same time for the subsequent frequency-locked loop calculation and phase-locked loop calculation. The frequency-locked loop is the pre-link of the phase-locked loop, which mainly provides frequency information, that is, calculates the grid voltage frequency to ensure that the current reference signal i refThe frequency of the phase-locked loop is consistent with the grid voltage. The phase-locked loop mainly provides phase information to ensure that the phase of the phase-locked loop output signal is consistent with the grid voltage. The specific implementation process of the frequency-locked loop calculation and the phase-locked loop calculation can refer to the description of the corresponding embodiment of the PFC control device above, as well as Figures 4 to 7 The implementation method is not described in detail in this embodiment.

[0165] In addition to the aforementioned addition of the compensation voltage signal and the output current feedforward signal, this embodiment utilizes the input voltage sampling signal to generate a phase-locked loop output signal using a phase-locked loop (PLL) to serve as a reference waveform for the current of the first inductor to follow. This further helps maintain bus voltage stability, thereby stabilizing the output voltage of the PFC circuit and, in turn, maintaining a stable regulation effect of the subsequent converter.

[0166] In this embodiment, the voltage loop output signal u m and the phase-locked loop output signal i PLL Multiply and take the absolute value to get the current reference signal i ref The inductor current sampling signal is represented by i L , the preset current bias signal is represented by i bias In step S143, i L 、i bias And the current reference signal i ref As the input of a current loop, current loop calculation is performed to obtain a duty cycle reference signal d.

[0167] From the above analysis, we can see that: Where w represents the frequency of the phase-locked loop output signal, It is assumed that the current of the first inductor tracks the current reference signal i ref , then: Among them, i o Indicates the output current, U in 、U o are the effective values ​​of the input voltage and the output voltage respectively.

[0168] It can be seen from this that the output current feedforward signal I f and the output current i o is proportional to Therefore, for example, the feedforward coefficient k is preset f The value can be

[0169] according to Figure 3 It can be seen that:

[0170] K p (i ref +i bias -i L )=d*Tc (1),

[0171] Where, d is the duty cycle reference signal, K p is the preset current loop gain coefficient, T c The period of the timer corresponding to the PWM wave generated in the carrier chip of the control device can be generated by preset. The preset current loop gain coefficient K can be adjusted p To control the dynamic performance of the current loop.

[0172] In the continuous current mode (CCM) of the inductor, the input voltage and output voltage of the PFC circuit need to meet the following requirements:

[0173]

[0174] Combining the above formulas (1) and (2), and making the DC quantity and AC quantity equal, we can know that:

[0175]

[0176] get:

[0177] From this we can know that the preset current bias signal i bias The value of .

[0178] From the above formula (1) and formula (2), it can be seen that when the input voltage crosses zero, the duty cycle needs to be increased to close to 1 to provide a larger step-up ratio and output a higher voltage. However, the algorithm in the existing technology that does not add a preset current bias signal is difficult to achieve this goal, and it is easy to have the following problems: Figure 8 The current zero-crossing distortion phenomenon is shown in Figure 2. Figure 9 After adding the preset current bias signal, the present application increases the duty cycle at the zero-crossing point, thus achieving the goal of full duty cycle output at the voltage zero-crossing point, thereby effectively solving the problem of zero-crossing distortion, reducing the harmonic content of the input current in the current loop calculation, and improving the stability of the PFC circuit bus voltage. Figure 8 and Figure 9 The horizontal axis represents time, and the vertical axis represents current value.

[0179] In another embodiment of the present application, another power factor correction control method is disclosed. Figure 14 As shown in the above Figure 13 On the basis of the corresponding embodiment, step S140, in addition to the above steps S141, S142 and S143, further includes the following steps:

[0180] S145 , sampling the voltages of the first capacitor and the second capacitor respectively to obtain a first capacitor voltage sampling signal and a second capacitor voltage sampling signal.

[0181] S146, calculating the duty cycle difference value based on the first capacitor voltage sampling signal and the second capacitor voltage sampling signal. And

[0182] S147 , calculating the duty cycle corresponding to each switch tube according to the duty cycle reference signal and the duty cycle difference value.

[0183] In this embodiment, the first capacitor voltage sampling signal u is used c1 and the second capacitor voltage sampling signal u c2 , perform voltage balancing loop calculation, that is, input into the PI controller to obtain the duty cycle difference Δd, and then add and subtract the duty cycle difference Δd from the duty cycle reference signal d, respectively, to obtain the first duty cycle signal d1 corresponding to the first switch tube Q1, and the second duty cycle signal d2 corresponding to the second switch tube Q2. Then, the PWM generation module based on the carrier chip of the control device converts the calculated duty cycle signal into a PWM (pulse width modulation) wave to control the corresponding switch tube to turn on or off. The PWM generation module generates a PWM wave corresponding to the period of the timer. Among them, the above-mentioned duty cycle signal refers to the ratio of the time occupied by the high level within one period.

[0184] This embodiment uses the capacitor voltage balancing technique to ensure that the voltages on the two output capacitors are consistent, thereby ensuring that the switches experience the same voltage stress. This prevents damage to any one switch due to excessive voltage, thereby improving the reliability and stability of the PFC circuit.

[0185] For example, when the voltage on the second capacitor C2 is higher than the voltage on the first capacitor C1, that is, U c2 -U c1 is positive, and the error Δd after being amplified by the PI controller is also positive. At this time, d2>d1, and the charging time of C1 by the subsequent converter of the welding power supply (i.e., the phase-shifted full-bridge inverter circuit) is longer than that of C2. The voltage of C2 decreases and the voltage of C1 increases until the voltages of the two capacitors are equal.

[0186] like Figure 15 As shown, in one embodiment of the present invention, the above step S141 may include:

[0187] S1411 , when it is detected that the input voltage crosses a zero point, respectively obtain a first count value of the first counter and a second count value of the second counter.

[0188] S1412: Based on the first count value, calculate and obtain a voltage period of the grid.

[0189] S1413: Using the voltage period as the period of the second counter, performing proportional integral calculation based on the second count value to obtain the voltage phase of the power grid.

[0190] S1414: Perform phase-locked loop calculation based on the voltage cycle and voltage phase of the grid and the input voltage sampling signal to obtain a phase-locked loop output signal.

[0191] In this embodiment, step S1413 includes:

[0192] Gets the calculated last voltage phase of the power grid.

[0193] A difference between the second count value and the previous voltage phase is obtained.

[0194] Determine whether the difference is less than a preset period.

[0195] If yes, then perform proportional integral calculation to obtain the current voltage phase of the power grid. If no, jump to step S1411.

[0196] The aforementioned zero-crossing detection process primarily targets the grid voltage. When the grid voltage changes from negative to positive or vice versa, a flag is changed and the values ​​of the relevant timers are recorded for subsequent frequency-locked loop (FLL) and phase-locked loop (PLL) calculations. The FLL is a precursor to the PLL and primarily provides frequency information, specifically calculating the grid voltage frequency to ensure that the frequency of the current reference signal (iref) matches the grid voltage. The PLL primarily provides phase information to ensure that the phase of the PLL output signal matches the grid voltage.

[0197] In summary, the power factor correction control device, method, and welding power supply of the present invention have at least the following advantages:

[0198] The power factor correction control device, method, and welding machine power supply disclosed in the present invention utilize a preset voltage reference value to perform voltage compensation on an output voltage sampling signal, sample and filter the output current to obtain an output current feedforward signal, thereby implementing load feedforward regulation in the PFC circuit to subsequently generate a PWM wave for regulating the on / off of the switch tube. This helps maintain the bus voltage stability of the PFC circuit, thereby maintaining the stability of the regulation effect of the subsequent converter, ensuring good welding results for the welding machine, and improving the stability of its welding performance.

[0199] On the other hand, the present invention realizes voltage balancing of the two switching tubes in the PFC circuit, thereby preventing the voltage from being too high and damaging any switching tube, thereby improving the reliability of the PFC circuit and further ensuring the welding effect of the welding machine.

[0200] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A power factor correction control device, characterized in that: Used to control a power factor correction circuit in a welding power supply, the control device is electrically connected to the power factor correction circuit, the power factor correction circuit includes at least one switch component and a first inductor, the first inductor is connected to the switch component, and the control device includes: a sampling unit for sampling the input voltage, output voltage, and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively; and further for sampling the current of the first inductor to obtain an inductor current sampling signal; A voltage compensation unit is connected to the sampling unit and calculates a compensation voltage signal according to the output voltage sampling signal and a preset voltage reference value; a voltage loop output unit, connected to the sampling unit and the voltage compensation unit respectively, and calculating a voltage loop output signal according to the output current sampling signal and the compensation voltage signal; A voltage balancing unit is respectively connected to the sampling unit and the voltage loop output unit. The voltage balancing unit includes a phase-locked loop subunit and a current bias calculation subunit. The phase-locked loop subunit is connected to the sampling unit. The phase-locked loop subunit obtains a phase-locked loop output signal through phase-locked loop calculation based on the input voltage sampling signal. The current bias calculation subunit obtains a current reference signal according to the phase-locked loop output signal and the voltage loop output signal; and calculates a duty cycle reference signal according to the inductor current sampling signal, the preset current bias signal and the current reference signal; calculates multiple duty cycle signals according to the duty cycle reference signal; and generates a pulse width modulation wave according to the duty cycle signal to respectively control the corresponding switch components to be turned on and off; the duty cycle signal corresponds one-to-one to the switch component.

2. The power factor correction control device according to claim 1, wherein: The voltage loop output unit includes: an output current feedforward subunit, connected to the sampling unit, and configured to calculate an output current feedforward signal based on the output current sampling signal; The voltage loop output unit calculates a voltage loop output signal according to the output current feedforward signal and the compensation voltage signal.

3. The power factor correction control device according to claim 1, wherein: The power factor correction circuit further includes a first capacitor and a second capacitor connected in series, wherein a first end of the first capacitor is connected to the first inductor and the switch component respectively, and a second end of the second capacitor is connected to the switch component; The pressure balancing unit further includes: The duty cycle difference calculation subunit samples the voltages of the first capacitor and the second capacitor respectively to obtain a first capacitor voltage sampling signal and a second capacitor voltage sampling signal; calculates a duty cycle difference value based on the first capacitor voltage sampling signal and the second capacitor voltage sampling signal; and the current bias calculation subunit calculates the duty cycle signals corresponding to each switching tube according to the duty cycle reference signal and the duty cycle difference value.

4. A power factor correction control method, using the power factor correction control device according to any one of claims 1 to 3 for control, characterized in that: The following steps are involved: S110, sampling the input voltage, output voltage, and output current of the power factor correction circuit to obtain an input voltage sampling signal, an output voltage sampling signal, and an output current sampling signal, respectively; S120, calculating a compensation voltage signal according to the output voltage sampling signal and a preset voltage reference value; S130, calculating a voltage loop output signal according to the output current sampling signal and the compensation voltage signal; S140, calculating and obtaining multiple duty cycle signals according to the input voltage sampling signal and the voltage loop output signal; And according to the duty cycle signal, a pulse width modulation wave is generated to control the corresponding switch components to be turned on and off respectively; The duty cycle signals correspond one-to-one to the switch components.

5. The power factor correction control method according to claim 4, wherein: Step S130 includes: Calculating an output current feedforward signal according to the output current sampling signal; and A voltage loop output signal is calculated based on the output current feedforward signal and the compensation voltage signal.

6. The power factor correction control method according to claim 4, wherein: Step S140 includes: Based on the input voltage sampling signal, a phase-locked loop output signal is obtained through phase-locked loop calculation; A plurality of duty cycle signals are calculated based on the phase-locked loop output signal and the voltage loop output signal.

7. The power factor correction control method according to claim 6, wherein: The power factor correction circuit further includes a first inductor, wherein the first inductor is connected to the switch component; Step S110 further includes: Sampling the current of the first inductor to obtain an inductor current sampling signal; Step S140 further includes: Obtaining a current reference signal according to the phase-locked loop output signal and the voltage loop output signal; Calculating a duty cycle reference signal according to the inductor current sampling signal, the preset current bias signal and the current reference signal; and Multiple duty cycle signals are calculated based on the duty cycle reference signal.

8. The power factor correction control method according to claim 7, wherein: The power factor correction circuit further includes a first capacitor and a second capacitor connected in series, wherein a first end of the first capacitor is connected to the first inductor and the switch component respectively, and a second end of the second capacitor is connected to the switch component; step S140 further includes: Sampling the voltages of the first capacitor and the second capacitor respectively to obtain a first capacitor voltage sampling signal and a second capacitor voltage sampling signal; Calculating a duty cycle difference value according to the first capacitor voltage sampling signal and the second capacitor voltage sampling signal; and The duty cycle corresponding to each switch tube is calculated based on the duty cycle reference signal and the duty cycle difference value.

9. The power factor correction control method according to claim 6, wherein: The step of obtaining a phase-locked loop output signal by calculating the phase-locked loop based on the input voltage sampling signal includes: When the input voltage is detected to cross a zero point, a first count value of the first counter and a second count value of the second counter are respectively acquired; Calculating a voltage period of a power grid access based on the first count value; Using the voltage period as the period of a second counter, performing proportional integral calculation based on the second count value to obtain a voltage phase of the power grid; A phase-locked loop calculation is performed according to the voltage cycle and voltage phase of the access power grid and the input voltage sampling signal to obtain a phase-locked loop output signal.

10. The power factor correction control method according to claim 9, wherein: The step of obtaining a phase-locked loop output signal by calculating the phase-locked loop based on the input voltage sampling signal includes: Obtaining a difference between the second count value and the previous voltage phase; It is determined whether the difference is less than a preset period. If so, a proportional integral calculation is performed to obtain the current voltage phase of the power grid.

11. The power factor correction control method according to claim 5, wherein: Step S130 includes: extracting an alternating current from the output current of the power factor correction circuit, sampling the alternating current, and obtaining an output current sampling signal; The output current sampling signal is filtered using a notch filter to obtain an output current feedforward signal.

12. A welding power supply, characterized in that: The invention comprises a power factor correction control device as claimed in any one of claims 1 to 3.

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