Space Vector Modulation Method and System for Asymmetric Quasi-Z-Source Three-Level Inverter

Abstract

The present invention provides a space vector modulation method and system for an asymmetric quasi-Z-source three-level inverter, which relates to the technical field of power electronic power conversion. According to the amplitude and phase angle of the reference voltage vector, it is judged which sector the reference voltage vector is located in the space vector diagram; in combination with the sector where the reference voltage vector is located and the voltage deviation between the two capacitors in the quasi-Z-source network, the corresponding basic voltage vectors are selected, and the switching sequence flag bits are calculated; the voltage deviation between the two capacitors in the quasi-Z-source network is adjusted to obtain the output of the DC-side capacitor voltage balance controller; based on the switching sequence flag bits, different types of through states are selected for injection, and the duty ratios of the basic voltage vectors are calculated; according to the switching sequence flag bits and the duty ratios of the basic voltage vectors, a switching sequence is designed. The present invention can overcome the influence of the topological structure asymmetry on the system output, ensure three-phase symmetrical output current, and at the same time have the active control capabilities of boost and neutral point voltage balance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and particularly relates to a space vector modulation method and system for an asymmetric quasi-Z-source three-level inverter. Background Art

[0002] The statements in this part only provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] The quasi-Z-source three-level inverter has advantages such as single-stage power conversion, continuous input current, small capacity of passive devices, and no need to set dead time, and has been widely used in fields such as solar photovoltaic power generation, energy storage systems, and motor drives. The quasi-Z-source neutral point clamped (NPC) and T-type three-level inverters are the two most commonly used quasi-Z-source three-level inverter topologies, but both require a relatively large number of power switching tubes, which inevitably increases the system cost and volume.

[0004] To further reduce the number of power switching tubes, system volume and cost, an asymmetric quasi-Z-source three-level inverter topology structure can be adopted, that is, one phase bridge arm of the quasi-Z-source three-level inverter is replaced with the bridge arm of a two-level inverter topology; however, the three-phase bridge arms of this topology structure are no longer symmetrical, and the existing modulation methods for quasi-Z-source three-level inverters are not applicable.

[0005] The inventors found that the number of basic voltage vectors of the asymmetric quasi-Z-source three-level inverter is limited, which brings great difficulties to the design of space vector modulation strategies; therefore, a space vector modulation method applicable to the asymmetric quasi-Z-source three-level inverter needs to be studied urgently. Summary of the Invention

[0006] To overcome the deficiencies of the above-mentioned prior art, the present invention provides a space vector modulation method and system for an asymmetric quasi-Z-source three-level inverter, which can overcome the influence of topological structure asymmetry on the system output, ensure three-phase symmetrical output current, and at the same time have the ability of active control of boost and neutral point voltage balance.

[0007] To achieve the above object, one or more embodiments of the present invention provide the following technical solutions:

[0008] The first aspect of the present invention provides a space vector modulation method for an asymmetric quasi-Z-source three-level inverter.

[0009] The space vector modulation method for an asymmetric quasi-Z-source three-level inverter includes:

[0010] Judging the sector where the reference voltage vector is located in the space vector diagram according to the amplitude and phase angle of the reference voltage vector;

[0011] Combined with the sector where the reference voltage vector is located and the voltage deviation of the two capacitors in the quasi-Z-source network, select the corresponding basic voltage vector and generate the switch sequence flag bit;

[0012] Adjust the voltage deviation of the two capacitors in the quasi-Z-source network to obtain the output of the DC-side capacitor voltage equalization controller;

[0013] Based on the switch sequence flag bit, select different types of through states to inject, calculate the duty cycle of the basic voltage vector, and limit the output of the DC-side capacitor voltage equalization controller according to the calculated duty cycle;

[0014] According to the switch sequence flag bit and the duty cycle of the basic voltage vector, design the switch sequence, convert the switch sequence into the PWM drive signal of the power switch tube, and control the operation of the asymmetric quasi-Z-source three-level inverter.

[0015] Furthermore, according to the requirements of the system neutral point voltage balance control, set the neutral point voltage balance control threshold ΔV np_th , combined with the sector Sector where the reference voltage vector is located and the capacitors C 2 、C 3 's voltage deviation ΔV np , select the corresponding basic voltage vectors to synthesize the reference voltage vector according to the rules and generate the switch sequence flag bit Flag.

[0016] Furthermore, the voltage deviation ΔV of the two capacitors in the quasi-Z-source network np , and send it to a proportional-integral (PI) regulator, and further perform an absolute value operation to obtain the output of the DC-side capacitor voltage equalization controller.

[0017] Furthermore, according to the value of the switch sequence flag bit, determine the calculation method of the basic voltage vector duty cycle; use the volt-second balance principle to write a system of equations and solve the duty cycle of the basic voltage vector.

[0018] Furthermore, the specific method of the above-mentioned selection of different types of through states to inject is as follows: when the switch sequence flag bit Flag = 5 or 14, inject the lower through state in the P-type small vector and the upper through state in the N-type small vector to achieve the boost function and do not affect the normal output of the AC voltage of the system; when the switch sequence flag bit Flag takes other values, inject the full through state in the zero vector [PPP] or [NNN] to achieve the boost function and do not affect the normal output of the AC voltage of the system.

[0019] Furthermore, the output of the DC-side capacitor voltage balancing controller is limited to ensure that the duty ratios of all basic voltage vectors are greater than 0 and less than 1, and the duty ratios of all basic voltage vectors are updated to achieve the neutral point voltage balance control.

[0020] Furthermore, according to the value of the switch sequence flag bit, the switch sequence is designed.

[0021] Furthermore, the designed switch sequence is converted into the PWM drive signal of the power switch tube, and then the asymmetric quasi-Z-source three-level inverter system is controlled to work.

[0022] The second aspect of the present invention provides a space vector modulation system for an asymmetric quasi-Z-source three-level inverter.

[0023] The space vector modulation system for an asymmetric quasi-Z-source three-level inverter includes a sector judgment module, a flag bit calculation module, a DC-side capacitor voltage balancing control module, a duty ratio calculation module, and a switch design module;

[0024] The sector judgment module is configured to: judge the sector where the reference voltage vector is located in the space vector diagram according to the amplitude and phase angle of the reference voltage vector;

[0025] The flag bit calculation module is configured to: select the corresponding basic voltage vector in combination with the sector where the reference voltage vector is located and the voltage deviation between the two capacitors in the quasi-Z-source network, and calculate the switch sequence flag bit;

[0026] The DC-side capacitor voltage balancing control module is configured to: adjust the voltage deviation between the two capacitors in the quasi-Z-source network to obtain the output of the DC-side capacitor voltage balancing controller;

[0027] The duty ratio calculation module is configured to: select different types of through states to inject based on the switch sequence flag bit, calculate the duty ratios of the basic voltage vectors, and limit the output of the DC-side capacitor voltage balancing controller according to the calculated duty ratios;

[0028] The switch design module is configured to: design the switch sequence according to the switch sequence flag bit and the duty ratios of the basic voltage vectors, convert the switch sequence into the PWM drive signal of the power switch tube, and control the asymmetric quasi-Z-source three-level inverter to work.

[0029] The third aspect of the present invention provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the steps in the space vector modulation method for an asymmetric quasi-Z-source three-level inverter described in the first aspect of the present invention are implemented.

[0030] The fourth aspect of the present invention provides an electronic device, including a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, the steps in the space vector modulation method of the asymmetric quasi-Z-source three-level inverter as described in the first aspect of the present invention are implemented.

[0031] The above one or more technical solutions have the following beneficial effects:

[0032] 1. In different sectors, the boost function is achieved by injecting the full-through state into the zero vector or injecting the upper-through and lower-through states into the small vectors.

[0033] 2. According to the sector where the reference voltage vector is located and the DC-side capacitor voltage deviation value, the corresponding basic voltage vectors are selected to effectively control the neutral point voltage balance, and the amplitude of the capacitor voltage fluctuation is very small.

[0034] 3. When abnormal factors cause the neutral point voltage to shift, the method of the present invention has the active control ability of neutral point voltage balance to restore the neutral point voltage balance state, thereby improving the operation reliability of the system.

[0035] 4. Overcome the influence of the topological structure asymmetry on the system output and ensure three-phase symmetric output current.

[0036] The advantages of the additional aspects of the present invention will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present invention. Brief Description of the Drawings

[0037] The specification drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0038] Figure 1 It is the circuit topology diagram of the asymmetric quasi-Z-source three-level inverter in the first embodiment;

[0039] Figure 2 It is the space vector diagram in the first embodiment;

[0040] Figure 3 It is the control block diagram in the first embodiment;

[0041] Figures 4(a) and 4(b) are the working waveform diagrams of the method in this embodiment in the non-boost operation mode.

[0042] Figures 5(a) and 5(b) are the working waveform diagrams of the method in this embodiment in the boost operation mode.

[0043] Figure 6(a) is the working waveform diagram of the method of this embodiment in the non-boost operation mode when the modulation degree step-changes from 0.6 to 0.8.

[0044] Figure 6(b) is the working waveform diagram of the method of this embodiment in the boost operation mode when the modulation degree step-changes from 0.6 to 0.8.

[0045] Figure 7(a) is the working waveform diagram of the method of this embodiment in the non-boost operation mode when the midpoint voltage balance control changes from enabled to disabled.

[0046] Figure 7(b) is the working waveform diagram of the method of this embodiment in the boost operation mode when the midpoint voltage balance control changes from enabled to disabled. Detailed implementation manners

[0047] The present invention will be further described below in conjunction with the drawings and embodiments.

[0048] It should be noted that the following detailed descriptions are all exemplary and are intended to provide further descriptions of the present invention; unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0049] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present invention; as used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0050] Embodiment 1

[0051] This embodiment discloses a space vector modulation method for an asymmetric quasi-Z-source three-level inverter.

[0052] Figure 1 is the circuit topology diagram of the asymmetric quasi-Z-source three-level inverter, which includes the following components: a DC power supply, a quasi-Z-source network, an asymmetric three-level inverter, and a load. Among them, the quasi-Z-source network is connected between the DC power supply and the asymmetric three-level inverter to realize the boost function; its input voltage is V in , and the output voltage is V dc ; the asymmetric three-level inverter is composed of three-phase bridge arms A, B, and C. The A-phase bridge arm contains 2 power switching tubes, and the B-phase and C-phase bridge arms each contain 4 power switching tubes.

[0053] The switching states of the asymmetric quasi-Z-source three-level inverter can be divided into two types: non-shoot-through state and shoot-through state.

[0054] Similar to the ordinary three-level inverter, the non-shoot-through states of the asymmetric quasi-Z-source three-level inverter include three types: [P], [O], and [N]; the neutral point of the quasi-Z-source network (i.e., the point O in Figure 1 is selected as the reference point; when the switching state is [P], the output voltage of the bridge arm is +V dc / 2; when the switching state is [O], the output voltage of the bridge arm is 0; when the switching state is [N], the output voltage of the bridge arm is -V dc / 2.

[0055] Table 1 Switching States and Turned-on Power Switch Tubes of Phase A

[0056]

[0057] Table 2 Switching States and Turned-on Power Switch Tubes of Phase B and Phase C

[0058]

[0059] The shoot-through states of the asymmetric quasi-Z-source three-level inverter include three types: up-shoot-through (UST) state (abbreviated as [U]), down-shoot-through (DST) state (abbreviated as [D]), and full-shoot-through (FST) state (abbreviated as [F]); Table 1 shows the switching states and turned-on power switch tubes of Phase A, and Table 2 shows the switching states and turned-on power switch tubes of Phase B and Phase C.

[0060] The pulse width modulation (PWM) method is used to control the turning-on and turning-off of each power switch tube; it can be understood that the power switch tube is an insulated-gate bipolar transistor (IGBT); other forms of transistors can also be used to implement the power switch tube.

[0061] Figure 2It is the space vector diagram of the asymmetric quasi-Z-source three-level inverter. Among them, the basic voltage vectors include 6 large vectors, 4 medium vectors, 6 small vectors and 2 zero vectors. Specifically, the large vectors include: [PNN], [PPN], [NPN], [NPP], [NNP], [PNP]; the medium vectors include: [PON], [NPO], [NOP], [PNO]; the small vectors include: [POO], [PPO], [NON], [NOO], [NNO], [POP]; the zero vectors include: [PPP], [NNN].

[0062] The control block diagram of the method of the present invention is as Figure 3 shown. To obtain three-phase symmetric output current, achieve neutral point voltage balance control and boost and other objectives, a space vector modulation method for an asymmetric quasi-Z-source three-level inverter is designed, including:

[0063] Step S1: According to the amplitude and phase angle of the reference voltage vector, judge the sector where the reference voltage vector is located in the space vector diagram;

[0064] Step S2: Combine the sector where the reference voltage vector is located and the voltage deviation of the two capacitors in the quasi-Z-source network, select the corresponding basic voltage vector, and generate a switching sequence flag bit;

[0065] Sample the voltages at both ends of the capacitors C 2 and C 3 in the quasi-Z-source network, and calculate the voltage deviation ΔV np .

[0066] According to the requirements of the system neutral point voltage balance control, set the neutral point voltage balance control threshold (ΔV np_th ), combine the sector (Sector) where the reference voltage vector is located and the voltage deviation (ΔV 2 , C 3 ) of the capacitors C np , select the corresponding basic voltage vector to synthesize the reference voltage vector, and generate a switching sequence flag bit (Flag). The specific rules are as follows:

[0067] When Sector = 1 and ΔV np ≤ΔV np_th , select the large vector [PNN], the medium vector [PON], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switching sequence flag bit Flag = 1;

[0068] When Sector = 1 and ΔV np >ΔV np_thWhen, select large vector [PNN], medium vector [PON], small vector [POO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 2;

[0069] When Sector = 2 and ΔV np ≤ΔV np_th When, select large vector [PPN], medium vector [PON], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 3;

[0070] When Sector = 2 and ΔV np >ΔV np_th When, select large vector [PPN], medium vector [PON], small vector [PPO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 4;

[0071] When Sector = 3 or 4, select large vector [PPN], large vector [NPN], small vector [PPO], and small vector [NON] to synthesize the reference voltage vector. At the same time, inject the lower-through state into the small vector [PPO] and the upper-through state into the small vector [NON] to achieve the boost function, and the switch sequence flag bit Flag = 5;

[0072] When Sector = 5 and ΔV np ≥-ΔV np_th When, select large vector [NPN], medium vector [NPO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 6;

[0073] When Sector = 5 and ΔV np <-ΔV np_th When, select large vector [NPN], medium vector [NPO], small vector [NON], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 7;

[0074] When Sector = 6 and ΔV np ≥-ΔV np_th When, select large vector [NPP], medium vector [NPO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 8;

[0075] When Sector = 6 and ΔV np <-ΔV np_th , select the large vector [NPP], medium vector [NPO], small vector [NOO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 9;

[0076] When Sector = 7 and ΔV np ≥ -ΔV np_th , select the large vector [NPP], medium vector [NOP], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 10;

[0077] When Sector = 7 and ΔV np <-ΔV np_th , select the large vector [NPP], medium vector [NOP], small vector [NOO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 11;

[0078] When Sector = 8 and ΔV np ≥ -ΔV np_th , select the large vector [NNP], medium vector [NOP], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 12;

[0079] When Sector = 8 and ΔV np <-ΔV np_th , select the large vector [NNP], medium vector [NOP], small vector [NNO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 13;

[0080] When Sector = 9 or 10, select the large vector [NNP], large vector [PNP], small vector [POP], and small vector [NNO] to synthesize the reference voltage vector. At the same time, inject the lower-through state into the small vector [POP] and the upper-through state into the small vector [NNO] to achieve the boost function, and the switch sequence flag bit Flag = 14;

[0081] When Sector = 11 and ΔV np ≤ ΔV np_thWhen it is the case, select the large vector [PNP], the medium vector [PNO], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 15;

[0082] When Sector = 11 and ΔV np > ΔV np_th When it is the case, select the large vector [PNP], the medium vector [PNO], the small vector [POP], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 16;

[0083] When Sector = 12 and ΔV np ≤ ΔV np_th When it is the case, select the large vector [PNN], the medium vector [PNO], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 17;

[0084] When Sector = 12 and ΔV np > ΔV np_th When it is the case, select the large vector [PNN], the medium vector [PNO], the small vector [POO], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 18.

[0085] Step S3: Adjust the voltage deviation between the two capacitors in the Z-source network to obtain the output of the DC-side capacitor voltage equalization controller;

[0086] Take the voltage deviation ΔV between the two capacitors in the quasi-Z-source network np , and send it to the PI regulator, and further perform the absolute value operation to obtain the output of the DC-side capacitor voltage equalization controller, that is

[0087]

[0088] Among them, V C2 and V C3 are the voltages across the capacitors C 2 and C 3 respectively, and k p,np and k i,np are the parameters of the PI regulator.

[0089] The obtained output of the DC-side capacitor voltage equalization controller (i.e., y np)It is used to limit the output of the DC-side capacitor voltage equalization controller in the next step to ensure that the duty ratios of all basic voltage vectors are greater than 0 and less than 1, thereby achieving the neutral point voltage balance control.

[0090] Step S4: Based on the switch sequence flag bit, select different types of through states to inject, calculate the duty ratios of the basic voltage vectors, and limit the output of the DC-side capacitor voltage equalization controller according to the calculated duty ratios;

[0091] According to the value of the switch sequence flag bit, determine the calculation method of the basic voltage vector duty ratio; use the volt-second balance principle to write a system of equations and solve the duty ratio of the basic voltage vector. The specific steps are as follows:

[0092] (1) When the switch sequence flag bit Flag = 1, 3, 6, 8, 10, 12, 15, 17, adopt the direct calculation method to solve the duty ratios of the large vector, medium vector, and zero vector.

[0093] Without loss of generality, taking the switch sequence flag bit Flag = 1, 3 as an example, the detailed solution steps are as follows.

[0094] When the switch sequence flag bit Flag = 1, the basic voltage vectors include the large vector [PNN], the medium vector [PON], and the zero vector [PPP]. Use the volt-second balance principle to write a system of equations:

[0095]

[0096] Among them, V 1 , V 7 and V 0 represent the expressions of the large vector [PNN], the medium vector [PON], and the zero vector [PPP] respectively, d 1 , d 7 and d 0 represent the duty ratios of the large vector [PNN], the medium vector [PON], and the zero vector [PPP] respectively, and V ref is the amplitude of the reference voltage vector.

[0097] Solve the above system of equations, and at the same time consider injecting the through state in the zero vector [PPP], the duty ratios of each basic voltage vector can be obtained as:

[0098]

[0099] Among them, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, and d st is the through duty ratio. The modulation degree m is defined as

[0100]

[0101] Among them, V ref is the amplitude of the reference voltage vector, and V dc is the amplitude of the output voltage of the quasi-Z-source network.

[0102] When the switch sequence flag bit Flag = 3, the basic voltage vectors include the large vector [PPN], the medium vector [PON], and the zero vector [PPP]. The equations are written based on the volt-second balance principle:

[0103]

[0104] Among them, V 2 , V 7 and V 0 represent the large vector [PPN], the medium vector [PON], and the zero vector [PPP] respectively, and d 2 , d 7 and d 0 represent the duty cycles of the large vector [PPN], the medium vector [PON], and the zero vector [PPP] respectively, and V ref is the reference voltage vector.

[0105] Solving the above equations, and considering injecting the direct-conduction state into the zero vector [PPP], and representing the injection of the direct-conduction state by directly subtracting the direct-conduction duty cycle from the duty cycle of the zero vector, the duty cycles of each basic voltage vector can be obtained as:

[0106]

[0107] Among them, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, and d st is the direct-conduction duty cycle.

[0108] When the switch sequence flag bit Flag takes other values, a similar method can be adopted and combined with the symmetry of the space vector diagram to complete the solution process.

[0109] (2) When the switch sequence flag bit Flag = 2, 4, 7, 9, 11, 13, 16, 18, the output of the DC-side capacitor voltage equalization controller is used as the duty cycle of the small vector, and an indirect calculation method is further designed to solve the duty cycles of the large vector, the medium vector, and the zero vector. At the same time, the output of the DC-side capacitor voltage equalization controller needs to be limited to ensure that the duty cycles of each basic voltage vector are greater than 0 and less than 1.

[0110] Without loss of generality, taking the switch sequence flag bit Flag = 2, 4 as an example, the detailed solution steps are given as follows.

[0111] When the switch sequence flag bit Flag = 2, the basic voltage vectors include the large vector [PNN], the medium vector [PON], the small vector [POO], and the zero vector [PPP]. The equations are written using the volt-second balance principle:

[0112]

[0113] Among them, V 1 , V 7 , V 11 and V 0 represent the large vector [PNN], the medium vector [PON], the small vector [POO], and the zero vector [PPP] respectively. d 1 , d 7 , d 11 and d 0 represent the duty cycles of the large vector [PNN], the medium vector [PON], the small vector [POO], and the zero vector [PPP] respectively. V ref is the reference voltage vector.

[0114] Taking the output of the DC-side capacitor voltage equalization controller as the duty cycle of the small vector, and considering injecting the through state into the zero vector [PPP], the duty cycles of each basic voltage vector can be further obtained as:

[0115]

[0116] Among them, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively. y np is the output of the DC-side capacitor voltage equalization controller, and d st is the through duty cycle.

[0117] To ensure that the duty cycles of each basic voltage vector are greater than 0 and less than 1, the output y np of the DC-side capacitor voltage equalization controller is limited, that is:

[0118]

[0119] When the switch sequence flag bit Flag = 4, the basic voltage vectors include the large vector [PPN], the medium vector [PON], the small vector [PPO], and the zero vector [PPP]. The equations are written using the volt-second balance principle:

[0120]

[0121] Among them, V 2 , V 7 , V 12 and V 0 represent the large vector [PPN], the medium vector [PON], the small vector [PPO], and the zero vector [PPP] respectively. d2 , d 7 , d 12 and d 0 represent the duty cycles of the large vector [PPN], medium vector [PON], small vector [PPO], and zero vector [PPP] respectively, and V ref is the reference voltage vector.

[0122] Taking the output of the DC-side capacitor voltage equalization controller as the duty cycle of the small vector, and considering injecting a direct-through state into the zero vector [PPP], the duty cycles of each basic voltage vector can be further obtained as follows:

[0123]

[0124] where m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, and y np is the output of the DC-side capacitor voltage equalization controller, and d st is the direct-through duty cycle.

[0125] To ensure that the duty cycles of each basic voltage vector are greater than 0 and less than 1, the output y np of the DC-side capacitor voltage equalization controller is limited, that is

[0126]

[0127] When the switch sequence flag bit Flag takes other values, a similar method can be adopted and combined with the symmetry of the space vector diagram to complete the solution process.

[0128] (3) When the switch sequence flag bit Flag = 5, 14, take the output of the DC-side capacitor voltage equalization controller as the change amount of the small vector duty cycle distribution factor, and further design an indirect calculation method to solve the duty cycles of two large vectors and two small vectors. At the same time, the output of the DC-side capacitor voltage equalization controller needs to be limited to ensure that the duty cycles of each basic voltage vector are greater than 0 and less than 1.

[0129] Without loss of generality, taking the switch sequence flag bit Flag = 5 as an example, the detailed solution steps are as follows.

[0130] When the switch sequence flag bit Flag = 5, the basic voltage vectors include the large vector [PPN], large vector [NPN], small vector [PPO], and small vector [NON]. Using the volt-second balance principle, a set of equations is written:

[0131]

[0132] where V 2 , V 3 , V 12 and V13 respectively represent the large vectors [PPN], [NPN], the small vectors [PPO] and [NON], d 2 , d 3 , d 12 and d 13 respectively represent the duty cycles of the large vectors [PPN], [NPN], the small vectors [PPO] and [NON], V ref is the reference voltage vector.

[0133] Substitute the expressions of each basic voltage vector into Equation (12), and combine with the definition of the modulation degree (Equation (4)), after simplification, the duty cycles d 12 and d 13 satisfy:

[0134] d 12 +d 13 = 2 - 2·m·sinθ (14)

[0135] Introduce the small vector duty cycle distribution factor λ(0 < λ < 1), which is used to represent the duty cycles d 12 , d 13 , that is

[0136]

[0137] The duty cycles of each basic voltage vector can be further expressed as:

[0138]

[0139] Obviously, the duty cycles of each basic voltage vector should be greater than 0 and less than 1. At the same time, the duty cycles of the small vectors should be greater than the through duty cycle to accurately inject the through state to achieve the boost function. Therefore, the small vector duty cycle distribution factor λ satisfies the following constraint conditions:

[0140]

[0141] Taking into account all the constraint conditions that the small vector duty cycle distribution factor λ should satisfy, we can obtain:

[0142] λ min < λ < λ max (18)

[0143] where, λ max and λ min are shown in Equations (18) and (19) respectively:

[0144]

[0145]

[0146] Take the initial value λ of the small vector duty ratio distribution factor λ 0 as λ max and λ min is the arithmetic mean of, that is

[0147]

[0148] Consider the voltage deviation of capacitors C 2 and C 3 in the quasi-Z-source network, and use the output of the DC-side capacitor voltage balancing controller as the change amount of the small vector duty ratio distribution factor, and the corrected value of the small vector duty ratio distribution factor is obtained as:

[0149]

[0150] Use the constraint conditions given by formulas (17)-(19) to limit the corrected value of the small vector duty ratio distribution factor, and then substitute it into formula (15), so as to update the duty ratio of each basic voltage vector, and then realize the neutral point voltage balance control.

[0151] To achieve the boost function, inject the lower direct-through state and the upper direct-through state into the small vectors [PPO] and [NON] respectively, and the duty ratios of each basic voltage vector are further updated as:

[0152]

[0153] When the switch sequence flag bit Flag takes other values, a similar method can be used and combined with the symmetry of the space vector diagram to complete the solution process.

[0154] Step S5: According to the switch sequence flag bit and the duty ratio of the basic voltage vector, considering factors such as low output harmonic content and as little switching loss as possible, design the switch sequence, convert the switch sequence into the PWM drive signal of the power switch tube, and control the operation of the asymmetric quasi-Z-source three-level inverter.

[0155] Design the switch sequence, and the specific rules are as follows:

[0156] When the switch sequence flag bit Flag = 1, the switch sequence is designed as:

[0157] PPP-FFF-PON-PNN-PON-FFF-PPP;

[0158] When the switch sequence flag bit Flag = 2, the switch sequence is designed as:

[0159] PPP-FFF-POO-PON-PNN-PON-POO-FFF-PPP;

[0160] When the switch sequence flag bit Flag = 3, the switch sequence is designed as:

[0161] PPP-FFF-PON-PPN-PON-FFF-PPP;

[0162] When the switch sequence flag bit Flag = 4, the switch sequence is designed as:

[0163] PPP-FFF-PPO-PON-PPN-PON-PPO-FFF-PPP;

[0164] When the switch sequence flag bit Flag = 5, the switch sequence is designed as:

[0165] PPO-PPD-PPN-NPN-NUN-NON-NUN-NPN-PPN-PPD-PPO;

[0166] When the switch sequence flag bit Flag = 6, the switch sequence is designed as:

[0167] NNN-FFF-NPO-NPN-NPO-FFF-NNN;

[0168] When the switch sequence flag bit Flag = 7, the switch sequence is designed as:

[0169] NNN-FFF-NON-NPO-NPN-NPO-NON-FFF-NNN;

[0170] When the switch sequence flag bit Flag = 8, the switch sequence is designed as:

[0171] NNN-FFF-NPO-NPP-NPO-FFF-NNN;

[0172] When the switch sequence flag bit Flag = 9, the switch sequence is designed as:

[0173] NNN-FFF-NOO-NPO-NPP-NPO-NOO-FFF-NNN;

[0174] When the switch sequence flag bit Flag = 10, the switch sequence is designed as:

[0175] NNN-FFF-NOP-NPP-NOP-FFF-NNN;

[0176] When the switch sequence flag bit Flag = 11, the switch sequence is designed as:

[0177] NNN-FFF-NOO-NOP-NPP-NOP-NOO-FFF-NNN;

[0178] When the switch sequence flag bit Flag = 12, the switch sequence is designed as:

[0179] NNN - FFF - NOP - NNP - NOP - FFF - NNN;

[0180] When the switch sequence flag bit Flag = 13, the switch sequence is designed as:

[0181] NNN - FFF - NNO - NOP - NNP - NOP - NNO - FFF - NNN;

[0182] When the switch sequence flag bit Flag = 14, the switch sequence is designed as:

[0183] NNO - NNU - NNP - PNP - PDP - POP - PDP - PNP - NNP - NNU - NNO;

[0184] When the switch sequence flag bit Flag = 15, the switch sequence is designed as:

[0185] PPP - FFF - PNO - PNP - PNO - FFF - PPP;

[0186] When the switch sequence flag bit Flag = 16, the switch sequence is designed as:

[0187] PPP - FFF - POP - PNO - PNP - PNO - POP - FFF - PPP;

[0188] When the switch sequence flag bit Flag = 17, the switch sequence is designed as:

[0189] PPP - FFF - PNO - PNN - PNO - FFF - PPP;

[0190] When the switch sequence flag bit Flag = 18, the switch sequence is designed as:

[0191] PPP - FFF - POO - PNO - PNN - PNO - POO - FFF - PPP.

[0192] Finally, the switch sequence is converted into the PWM drive signal of the power switch tube to control the operation of the asymmetric quasi - Z - source three - level inverter.

[0193] Figures 4(a) and 4(b) are the working waveform diagrams of the method of the present invention in the non - boost operation mode, including the DC input voltage (V in ), the output voltage of the quasi - Z - source network (V dc ), the line voltages (v ab , v bc , v ca ), the three - phase output currents (i a , i b , i c ), and the DC - side capacitor voltage (VC1 , V C2 , V C3 , V C4 ). At this time, the DC input voltage is set to 400V, and the modulation index and the direct-through duty ratio are set to 0.8 and 0 respectively.

[0194] It can be seen from the working waveform diagram that: the output voltage of the quasi-Z-source network is basically equal to the DC input voltage; the line voltages v ab and v ca are asymmetric five-level waveforms, and the line voltage v bc is a symmetric five-level waveform; the output current is a three-phase symmetric sinusoidal waveform; the voltages across the DC-side capacitors C 2 and C 3 are equal, both being 200V, and the fluctuations are very small. The method of the present invention can effectively control the neutral point voltage balance.

[0195] Figures 5(a) and 5(b) are the working waveform diagrams of the method of the present invention in the boost operation mode, including the DC input voltage (V in ), the output voltage of the quasi-Z-source network (V dc ), the line voltages (v ab , v bc , v ca ), the three-phase output currents (i a , i b , i c ), and the DC-side capacitor voltages (V C1 , V C2 , V C3 , V C4 ). At this time, the DC input voltage is set to 300V, and the modulation index and the direct-through duty ratio are set to 0.8 and 0.125 respectively.

[0196] It can be seen from the working waveform diagram that: the amplitude of the output voltage of the quasi-Z-source network is 400V, which is higher than the DC input voltage, verifying that the method of the present invention can achieve the normal boost function of the system; when the full direct-through state is injected into the zero vector, the output voltage of the quasi-Z-source network varies in the range of 0 to 400V; when the upper direct-through and lower direct-through states are injected into the small vectors, the output voltage of the quasi-Z-source network varies in the range of 200V to 400V; the voltages across the capacitors C 2 and C 3 are equal and the fluctuations are very small, indicating that the method of the present invention can effectively control the neutral point voltage balance.

[0197] Figure 6(a) is the working waveform diagram of the method of the present invention in the non-boost operation mode when the modulation index step-changes from 0.6 to 0.8, including the DC input voltage (V in ), the output voltage of the quasi-Z-source network (V dc ), the line voltage (v ab) The three-phase output currents (i a i b i c ), the DC-link capacitor voltages (V C1 V C2 V C3 V C4 ). Fig. 6(b) is the waveform diagram of the method of the present invention in the boost operation mode when the modulation degree step-changes from 0.6 to 0.8, including the DC input voltage (V in ), the quasi-Z-source network output voltage (V dc ), the line voltage (v ab ), the three-phase output currents (i a i b i c ), the DC-link capacitor voltages (V C1 V C2 V C3 V C4 ).

[0198] From the waveform diagram, it can be seen that when the modulation degree increases step by step, the amplitudes of the three-phase output currents will increase accordingly; at the same time, the boost function of the system and the neutral point voltage balance control are not affected, verifying the effectiveness of the method of the present invention.

[0199] Fig. 7(a) is the waveform diagram of the method of the present invention in the non-boost operation mode when the neutral point voltage balance control changes from enabled to disabled, including the DC input voltage (V in ), the quasi-Z-source network output voltage (V dc ), the line voltage (v ab ), the three-phase output currents (i a i b i c ), the DC-link capacitor voltages (V C2 V C3 ). Fig. 7(b) is the waveform diagram of the method of the present invention in the boost operation mode when the neutral point voltage balance control changes from enabled to disabled, including the DC input voltage (V in ), the quasi-Z-source network output voltage (V dc ), the line voltage (v ab ), the three-phase output currents (i a i b i c ), the DC-link capacitor voltages (V C2 V C3 ).

[0200] To verify the neutral point voltage balance control function of the method of the present invention, on capacitors C 2 C 3Resistors with resistances of 1 kΩ and 10 kΩ are connected in parallel at both ends. Before the simulation time of 0.6 s, the midpoint balance control function is enabled. At this time, the voltages across the two capacitors can be kept equal, and the method of the present invention can effectively control the midpoint voltage balance. After the simulation time of 0.6 s, the midpoint balance control function is cancelled, and the voltages across the two capacitors deviate significantly, and the midpoint voltage balance state cannot be maintained, thus indicating that the method of the present invention has the active control ability for midpoint voltage balance.

[0201] Embodiment 2

[0202] This embodiment discloses a space vector modulation system for an asymmetric quasi-Z-source three-level inverter;

[0203] The space vector modulation system for an asymmetric quasi-Z-source three-level inverter includes a sector judgment module, a flag bit calculation module, a DC-side capacitor voltage balance control module, a duty cycle calculation module, and a switch design module;

[0204] The sector judgment module is configured to: judge the sector where the reference voltage vector is located in the space vector diagram according to the amplitude and phase angle of the reference voltage vector;

[0205] The flag bit calculation module is configured to: combine the sector where the reference voltage vector is located and the voltage deviation between the two capacitors in the quasi-Z-source network, select the corresponding basic voltage vector, and calculate the switch sequence flag bit;

[0206] The DC-side capacitor voltage balance control module is configured to: adjust the voltage deviation between the two capacitors in the quasi-Z-source network to obtain the output of the DC-side capacitor voltage balance controller;

[0207] The duty cycle calculation module is configured to: based on the switch sequence flag bit, select different types of direct-through states to inject, calculate the duty cycle of the basic voltage vector, and limit the output of the DC-side capacitor voltage balance controller according to the calculated duty cycle;

[0208] The switch design module is configured to: design the switch sequence according to the switch sequence flag bit and the duty cycle of the basic voltage vector, and control the operation of the asymmetric quasi-Z-source three-level inverter.

[0209] Embodiment 3

[0210] The purpose of this embodiment is to provide a computer-readable storage medium.

[0211] The computer-readable storage medium stores a computer program, and when the program is executed by a processor, it implements the steps in the space vector modulation method for an asymmetric quasi-Z-source three-level inverter as described in Embodiment 1 of the present disclosure.

[0212] Embodiment 4

[0213] The purpose of this embodiment is to provide an electronic device.

[0214] An electronic device, comprising a memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the space vector modulation method of the asymmetric quasi-Z-source three-level inverter as described in Embodiment 1 of the present disclosure are implemented.

[0215] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. Space vector modulation method for an asymmetric quasi-Z-source three-level inverter, characterized in that, it includes: judging the sector where the reference voltage vector is located in the space vector diagram according to the amplitude and phase angle of the reference voltage vector; combining the sector where the reference voltage vector is located and the voltage deviation between the two capacitors in the quasi-Z-source network, selecting the corresponding basic voltage vector, and generating a switching sequence flag bit; adjusting the voltage deviation between the two capacitors in the quasi-Z-source network to obtain the output of the DC-side capacitor voltage balancing controller; based on the switching sequence flag bit, selecting different types of through states to be injected, calculating the duty cycle of the basic voltage vector, and limiting the output of the DC-side capacitor voltage balancing controller according to the calculated duty cycle; According to the requirements of neutral point voltage balance control in the system, set the neutral point voltage balance control threshold Δ V np_th , combined with the sector Sector where the reference voltage vector is located and the voltage deviation Δ C 2 、 C 3 of the capacitor V np , select the corresponding basic voltage vectors to synthesize the reference voltage vector according to the rules, and generate the switch sequence flag bit Flag. The specific rules are as follows: When Sector = 1 and Δ V np ≤ Δ V np_th , select the large vector [PNN], medium vector [PON], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 1; When Sector = 1 and Δ V np > Δ V np_th At this time, select the large vector [PNN], medium vector [PON], small vector [POO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 2; When Sector = 2 and Δ V np ≤ Δ V np_th At this time, select the large vector [PPN], the medium vector [PON], and the zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 3; When Sector = 2 and Δ V np > Δ V np_th , select the large vector [PPN], medium vector [PON], small vector [PPO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 4; when Sector = 3 or 4, select the large vector [PPN], large vector [NPN], small vector [PPO], and small vector [NON] to synthesize the reference voltage vector. At the same time, inject the lower through state into the small vector [PPO] and the upper through state into the small vector [NON] to achieve the boost function, and the switching sequence flag bit Flag = 5; When Sector = 5 and Δ V np ≥ -Δ V np_th At this time, select the large vector [NPN], medium vector [NPO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 6; When Sector = 5 and Δ V np < -Δ V np_th At this time, select the large vector [NPN], medium vector [NPO], small vector [NON], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 7; When Sector = 6 and Δ V np ≥ -Δ V np_th , the large vector [NPP], medium vector [NPO], and zero vector [NNN] are selected to synthesize the reference voltage vector. At the same time, the full-through state is injected into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 8; When Sector = 6 and Δ V np < -Δ V np_th At this time, select the large vector [NPP], medium vector [NPO], small vector [NOO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 9; When Sector = 7 and Δ V np ≥ -Δ V np_th , select the large vector [NPP], medium vector [NOP], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 10; When Sector = 7 and Δ V np < -Δ V np_th At this time, select the large vector [NPP], medium vector [NOP], small vector [NOO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 11; When Sector = 8 and Δ V np ≥ -Δ V np_th At this time, select the large vector [NNP], medium vector [NOP], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 12; When Sector = 8 and Δ V np < -Δ V np_th At this time, select the large vector [NNP], medium vector [NOP], small vector [NNO], and zero vector [NNN] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [NNN] to achieve the boost function, and the switch sequence flag bit Flag = 13; when Sector = 9 or 10, select the large vector [NNP], large vector [PNP], small vector [POP], and small vector [NNO] to synthesize the reference voltage vector. At the same time, inject the lower through state into the small vector [POP] and the upper through state into the small vector [NNO] to achieve the boost function, and the switching sequence flag bit Flag = 14; When Sector = 11 and Δ V np ≤ Δ V np_th , select the large vector [PNP], medium vector [PNO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 15; When Sector = 11 and Δ V np > Δ V np_th At this time, select the large vector [PNP], medium vector [PNO], small vector [POP], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 16; When Sector = 12 and Δ V np ≤ Δ V np_th At this time, select the large vector [PNN], medium vector [PNO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 17; When Sector = 12 and Δ V np > Δ V np_th , select the large vector [PNN], medium vector [PNO], small vector [POO], and zero vector [PPP] to synthesize the reference voltage vector. At the same time, inject the full-through state into the zero vector [PPP] to achieve the boost function, and the switch sequence flag bit Flag = 18; designing a switching sequence according to the switching sequence flag bit and the duty cycle of the basic voltage vector, converting the switching sequence into the PWM drive signal of the power switch tube, and controlling the operation of the asymmetric quasi-Z-source three-level inverter.

2. The space vector modulation method for an asymmetric quasi-Z-source three-level inverter according to claim 1, characterized in that, The voltage deviation Δ of the two capacitors in the quasi-Z-source network V np is fed into the PI regulator, and the output value of the PI regulator is further subjected to an absolute value operation to obtain the output of the DC-side capacitor voltage equalization controller.

3. The space vector modulation method for an asymmetric quasi-Z-source three-level inverter according to claim 1, characterized in that, determining the calculation method of the duty cycle of the basic voltage vector according to the value of the switching sequence flag bit; writing a system of equations using the volt-second balance principle and solving the duty cycle of the basic voltage vector; When the switch sequence flag bit Flag = 1, 3, 6, 8, 10, 12, 15, 17, the direct calculation method is adopted to solve the duty cycles of the large vector, medium vector, and zero vector; when the switch sequence flag bit Flag = 2, 4, 7, 9, 11, 13, 16, 18, the output of the DC-side capacitor voltage equalization controller is used as the duty cycle of the small vector, and an indirect calculation method is further designed to solve the duty cycles of the large vector, medium vector, and zero vector. At the same time, the output of the DC-side capacitor voltage equalization controller needs to be limited to ensure that the duty cycles of all basic voltage vectors are greater than 0 and less than 1; when the switch sequence flag bit Flag = 5, 14, the output of the DC-side capacitor voltage equalization controller is used as the change amount of the small vector duty cycle distribution factor, and an indirect calculation method is further designed to solve the duty cycles of two large vectors and two small vectors. At the same time, the output of the DC-side capacitor voltage equalization controller needs to be limited to ensure that the duty cycles of all basic voltage vectors are greater than 0 and less than 1.

4. The space vector modulation method of an asymmetric quasi-Z-source three-level inverter as described in claim 1, characterized in that, when the switch sequence flag bit Flag = 1, the duty cycles of the large vector [PNN], medium vector [PON], and zero vector [PPP] are respectively Among them, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, d st is the direct-conduction duty ratio; when the switch sequence flag bit Flag = 3, the duty cycles of the large vector [PPN], medium vector [PON], and zero vector [PPP] are respectively wherein, m and θ are the modulation index and the phase angle of the reference voltage vector respectively, d st is the direct-conduction duty ratio; when the switch sequence flag bit Flag = 2, the duty cycles of the large vector [PNN], medium vector [PON], small vector [POO], and zero vector [PPP] are respectively Among them, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, y np is the output of the DC-side capacitor voltage balancing controller, d st is the direct-through duty ratio; the output y np of the DC-side capacitor voltage balancing controller is limited, that is, when the switch sequence flag bit Flag = 4, the duty cycles of the large vector [PPN], medium vector [PON], small vector [PPO], and zero vector [PPP] are respectively Wherein, m and θ are the modulation degree and the phase angle of the reference voltage vector respectively, y np is the output of the DC-side capacitor voltage equalization controller, d st is the direct-through duty ratio; the output of the DC-side capacitor voltage equalization controller y np is limited, that is when the switch sequence flag bit Flag = 5, the duty cycles of the large vector [PPN], large vector [NPN], small vector [PPO], and small vector [NON] are respectively wherein, y np is the output of the DC-side capacitor voltage equalization controller; when the switch sequence flag bit Flag takes other values, a similar method can be adopted and combined with the symmetry of the space vector diagram to complete the solution process.

5. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter as described in claim 1, characterized in that, The specific method of selecting and injecting different types of through states is as follows: when the switch sequence flag bit Flag = 5 or 14, the lower through state is injected into the P-type small vector, and the upper through state is injected into the N-type small vector to achieve the boost function and does not affect the normal output AC voltage of the system; when the switch sequence flag bit Flag takes other values, the full through state is injected into the zero vector [PPP] or [NNN] to achieve the boost function and does not affect the normal output AC voltage of the system.

6. The space vector modulation method of the asymmetric quasi-Z-source three-level inverter as described in claim 1, characterized in that, According to the value of the switch sequence flag bit, the switch sequence is designed as follows: When the switch sequence flag bit Flag = 1, the switch sequence is designed as: PPP-FFF-PON-PNN-PON-FFF-PPP; When the switch sequence flag bit Flag = 2, the switch sequence is designed as: PPP-FFF-POO-PON-PNN-PON-POO-FFF-PPP; When the switch sequence flag bit Flag = 3, the switch sequence is designed as: PPP-FFF-PON-PPN-PON-FFF-PPP; When the switch sequence flag bit Flag = 4, the switch sequence is designed as: PPP-FFF-PPO-PON-PPN-PON-PPO-FFF-PPP; When the switch sequence flag bit Flag = 5, the switch sequence is designed as: PPO-PPD-PPN-NPN-NUN-NON-NUN-NPN-PPN-PPD-PPO; When the switch sequence flag bit Flag = 6, the switch sequence is designed as: NNN-FFF-NPO-NPN-NPO-FFF-NNN; When the switch sequence flag bit Flag = 7, the switch sequence is designed as: NNN-FFF-NON-NPO-NPN-NPO-NON-FFF-NNN; When the switch sequence flag bit Flag = 8, the switch sequence is designed as: NNN-FFF-NPO-NPP-NPO-FFF-NNN; When the switch sequence flag bit Flag = 9, the switch sequence is designed as: NNN-FFF-NOO-NPO-NPP-NPO-NOO-FFF-NNN; When the switch sequence flag bit Flag = 10, the switch sequence is designed as: NNN-FFF-NOP-NPP-NOP-FFF-NNN; When the switch sequence flag bit Flag = 11, the switch sequence is designed as: NNN-FFF-NOO-NOP-NPP-NOP-NOO-FFF-NNN; When the switch sequence flag bit Flag = 12, the switch sequence is designed as: NNN-FFF-NOP-NNP-NOP-FFF-NNN; When the switch sequence flag bit Flag = 13, the switch sequence is designed as: NNN-FFF-NNO-NOP-NNP-NOP-NNO-FFF-NNN; When the switch sequence flag bit Flag = 14, the switch sequence is designed as: NNO-NNU-NNP-PNP-PDP-POP-PDP-PNP-NNP-NNU-NNO; When the switch sequence flag bit Flag = 15, the switch sequence is designed as: PPP-FFF-PNO-PNP-PNO-FFF-PPP; When the switch sequence flag bit Flag = 16, the switch sequence is designed as: PPP-FFF-POP-PNO-PNP-PNO-POP-FFF-PPP; When the switch sequence flag bit Flag = 17, the switch sequence is designed as: PPP-FFF-PNO-PNN-PNO-FFF-PPP; When the switch sequence flag bit Flag = 18, the switch sequence is designed as: PPP-FFF-POO-PNO-PNN-PNO-POO-FFF-PPP.

7. The system of the space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to any one of claims 1-6, characterized in that it includes a sector judgment module, a flag bit calculation module, a DC-side capacitor voltage balance control module, a duty cycle calculation module, and a switch design module; The sector judgment module is configured to: judge the sector where the reference voltage vector is located in the space vector diagram according to the amplitude and phase angle of the reference voltage vector; The flag bit calculation module is configured to: combine the sector where the reference voltage vector is located and the voltage deviation of the two capacitors in the quasi-Z-source network, select the corresponding basic voltage vector, and calculate the switch sequence flag bit; The DC-side capacitor voltage balance control module is configured to: adjust the voltage deviation of the two capacitors in the quasi-Z-source network to obtain the output of the DC-side capacitor voltage balance controller; The duty cycle calculation module is configured to: based on the switch sequence flag bit, select different types of through states to be injected, calculate the duty cycle of the basic voltage vector, and limit the output of the DC-side capacitor voltage balance controller according to the calculated duty cycle; The switch design module is configured to: design the switch sequence according to the switch sequence flag bit and the duty cycle of the basic voltage vector, convert the switch sequence into the PWM drive signal of the power switch tube, and control the operation of the asymmetric quasi-Z-source three-level inverter.

8. A computer-readable storage medium, on which a program is stored, characterized in that when the program is executed by a processor, it implements the steps in the space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to any one of claims 1-6.

9. An electronic device, including a memory, a processor, and a program stored on the memory and executable on the processor, characterized in that when the processor executes the program, it implements the steps in the space vector modulation method of the asymmetric quasi-Z-source three-level inverter according to any one of claims 1-6.

Images