Audio power amplifier circuit

Abstract

The application discloses an audio power amplifier circuit, which comprises an integral amplification module, a signal modulation module, a drive output module, a power limiting module and a gain control module. The integral amplification module is used for obtaining a differential output signal by performing integral operation and amplification on a differential input signal. The signal modulation module is used for generating a first pulse width modulation signal and a second pulse width modulation signal according to the differential output signal. The drive output module is used for amplifying the first pulse width modulation signal and the second pulse width modulation signal respectively to obtain a drive signal for driving a loudspeaker. The power limiting module is used for limiting the level of the differential output signal in a specified level range through clamping. The gain control module is used for synchronously reducing the gain of the integral amplification module in response to the clamping performed by the power limiting module, so that the overall gain of the circuit can be attenuated while limiting the output power, the waveform integrity of the output signal is ensured, the signal wave of the loudspeaker output signal is prevented from being eliminated, and the output sound quality level is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of audio power amplifier, more particularly, to an audio power amplifier circuit. BACKGROUND

[0002] Class-D amplifier circuit is a kind of switch type power amplifier circuit, which has the characteristics of high efficiency and less heat compared with linear power amplifier circuit, so it is widely used as an audio power amplifier circuit in the field of consumer electronics such as smart TV, mobile phone, etc.

[0003] Figure 1 The circuit schematic diagram of an existing two-stage audio power amplifier circuit is shown. As shown in the figure, Figure 1 The audio power amplifier circuit 100 includes an integral amplification module 110, a signal modulation module 120 and a drive output module 130.

[0004] The integral amplification module 110 includes a first-stage error integrator AMP1 and a second-stage error integrator AMP2. A pair of differential signals INA and INB are coupled to the input of the first-stage error integrator AMP1 through a capacitor Cin and a resistor Rin, respectively, and the output signals OPA and OPB are output after full differential amplification through the first-stage error integrator AMP1 and the second-stage error integrator AMP2 in sequence. The output signals OPA and OPB are modulated by a modulating signal RAMP through the comparator CMP1 and the comparator CMP2 in the signal modulation module 120, respectively, to generate pulse width modulation signals PWMA and PWMB. The drive output module 130 performs power amplification on the pulse width modulation signals PWMA and PWMB through the alternate operation of the transistor half-bridge to generate drive signals OUTA and OUTB. The feedback resistors Rfb1 and Rfb2 are used to feedback the drive signals OUTA and OUTB to the input end. In actual application, the drive signals output by the drive output module 130 can be directly transmitted to the loudspeaker to restore the audio signal (the loudspeaker itself has a certain low-pass filtering capability) or transmitted to the loudspeaker to play after being restored to the audio signal via a low-pass filtering circuit.

[0005] In a high-power audio power amplifier circuit, the output power is large, and the loudspeaker needs to be of high quality. If the output power is not limited, the loudspeaker may be damaged. A typical high-power audio power amplifier chip is a 30W / 8Ω audio power amplifier chip with 1% THD (total harmonic distortion), which is applied to a 15W or 10W audio product, and the output power of the audio power amplifier circuit needs to be limited.

[0006] In order to prevent the loudspeaker from being damaged, the high-power audio power amplifier chips on the market currently all adopt the way of directly limiting the output power. However, if the gain of the audio power amplifier circuit is not attenuated accordingly, the output will be attenuated, the THD of the chip will be deteriorated, and the sound quality level of the loudspeaker will be reduced. SUMMARY

[0007] In view of the above problems, the present application aims to provide an audio power amplifier circuit which can attenuate the gain of the circuit while limiting the output power of the circuit, thus ensuring the sound quality level of the loudspeaker.

[0008] According to an embodiment of the present application, an audio power amplifier circuit is provided, comprising: an integral amplification module configured to amplify a differential input signal through integral operation to obtain a differential output signal; a signal modulation module configured to generate a first pulse width modulation signal and a second pulse width modulation signal according to the differential output signal; a drive output module configured to amplify the first pulse width modulation signal and the second pulse width modulation signal respectively to obtain a drive signal for driving a loudspeaker; a power limiting module configured to limit the level of the differential output signal within a specified level range through clamping; and a gain control module configured to reduce the gain of the integral amplification module in synchronization with the clamping performed by the power limiting module.

[0009] Optionally, the audio power amplifier circuit further comprises a high-frequency switch arranged between input resistors of the integral amplification module, the power limiting module is configured to generate an enable control signal while performing the clamping, and the gain control module is configured to reduce the gain of the integral amplification module by increasing the duty cycle of the high-frequency switch in response to the enable control signal.

[0010] Optionally, the power limiting module comprises: a comparison circuit coupled to the output end of the integral amplification module, configured to convert the comparison result of the differential output signal and a threshold voltage into a current signal, and compare the current signal with a reference current; an adjustment current output circuit coupled to the comparison circuit and the input end of the integral amplification module, configured to adjust the input current of the integral amplification module based on the comparison result of the current signal and the reference current; and an enable detection circuit coupled to the comparison circuit, configured to output the enable control signal in synchronization with the control of the comparison circuit.

[0011] Optionally, the power limiting module further comprises: a reference current generation circuit configured to generate the reference current.

[0012] Optionally, the reference current generation circuit comprises: a first P-channel transistor and a first current source coupled in sequence between a power supply voltage and a ground, the control end and the second end of the first P-channel transistor being coupled to each other.

[0013] Optionally, the comparison circuit comprises: a first N-channel transistor, a first end of which is coupled to the first node, a control end of which is coupled to the threshold voltage, and a second end of which is coupled to one of the differential output signals; a second N-channel transistor, a first end of which is coupled to the second node, a control end of which is coupled to the threshold voltage, and a second end of which is coupled to the other of the differential output signals; a second P-channel transistor, a first end of which is coupled to the power supply voltage, a second end of which is coupled to the first node, and a control end of which is coupled to the control end of the first P-channel transistor; and a third P-channel transistor, a first end of which is coupled to the power supply voltage, a second end of which is coupled to the second node, and a control end of which is coupled to the control end of the first P-channel transistor.

[0014] Optionally, the adjustment current output circuit comprises: a tenth P-channel transistor coupled between the power supply voltage and the first node, a control end and a second end of the tenth P-channel transistor being coupled to each other; an eleventh P-channel transistor coupled between the power supply voltage and the second node, a control end and a second end of the eleventh P-channel transistor being coupled to each other; and a current conversion unit for converting a current in the eleventh P-channel transistor or the tenth P-channel transistor into a differential adjustment current applied to an input end of the integration amplification module.

[0015] Optionally, the enable detection circuit comprises: a sixth P-channel transistor coupled between the first node and the first end of the first N-channel transistor, a control end and a second end of the sixth P-channel transistor being coupled to each other; a seventh P-channel transistor coupled between the second node and the first end of the second N-channel transistor, a control end and a second end of the seventh P-channel transistor being coupled to each other; fourth and eighth P-channel transistors coupled in sequence between the power supply voltage and a third node, a control end of the fourth P-channel transistor being coupled to the control end of the first P-channel transistor, and a control end of the eighth P-channel transistor being coupled to the control end of the seventh P-channel transistor; fifth and ninth P-channel transistors coupled in sequence between the power supply voltage and the third node, a control end of the fifth P-channel transistor being coupled to the control end of the first P-channel transistor, and a control end of the ninth P-channel transistor being coupled to the control end of the sixth P-channel transistor; a second current source coupled between the third node and ground; and a Schmitt trigger, an input end of which is coupled to the third node, and an output end of which is used for outputting the enable control signal.

[0016] Optionally, a size ratio of the third P-channel transistor and the second P-channel transistor to the first P-channel transistor is 1.

[0017] Optionally, a size ratio of the fourth P-channel transistor and the fifth P-channel transistor to the first P-channel transistor is n, n being an integer greater than 1.

[0018] In summary, when the input analog signal suddenly increases, the power limiting module of the audio power amplifier circuit according to the embodiment of the present application limits the level of the output signal of the integral amplification module in a specified level range through feedback clamping, and the gain control module simultaneously reduces the gain of the integral amplification module in response to the clamping performed by the power limiting module, so that the overall gain of the circuit can be attenuated while the voltage of the driving signal output by the circuit is limited in a preset voltage range, the waveform of the output signal is guaranteed to be complete, the generation of the wave cancellation of the loudspeaker output signal is avoided, and the output sound quality level is improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0020] Figure 1 a circuit schematic diagram of an existing two-stage audio power amplifier circuit is shown;

[0021] Figure 2 a circuit schematic diagram of an audio power amplifier circuit according to an embodiment of the present application is shown;

[0022] Figure 3 a circuit schematic diagram of a power limiting module according to an embodiment of the present application is shown;

[0023] Figure 4a and Figure 4b output waveform diagrams of the prior art audio power amplifier circuit and the audio power amplifier circuit according to the embodiment of the present application are shown respectively. DETAILED DESCRIPTION

[0024] The present application is described below based on the embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be completely understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, the well-known methods, processes, procedures, elements and circuits are not described in detail.

[0025] In addition, those skilled in the art should understand that the drawings provided herein are for illustrative purposes only, and these drawings are not necessarily drawn to scale.

[0026] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled to another element or there may be intermediate elements. The coupling between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] Figure 2 A circuit diagram of an audio power amplifier circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the audio power amplifier circuit 200 includes an integrating amplifier module 210, a signal modulation module 220, a drive output module 230, a power limiting module 240, and a gain control module 250.

[0029] The audio amplifier circuit 200 generates drive signals OUTA and OUTB, which have positive and negative phases modulated by pulse width modulation in response to the levels of the input analog signals INA and INB, which are input to the input terminals. Loads such as filters and speaker coils are arranged between the output terminals of the audio amplifier circuit 200. Resistors Rin1, Rin2, and Rfb1 are connected in series between the input terminal of the analog input signal INA and the output terminal of the drive signal OUTA. Resistors Rin3, Rin4, and Rfb2 are connected in series between the input terminal of the analog input signal INB and the output terminal of the drive signal OUTB. The analog input signals INA and INB are a pair of differential signals. The analog input signal INA is input to one input terminal (e.g., the positive phase input terminal) of the integrating amplifier module 210 through resistors Rin1 and Rin2, and the analog input signal INB is input to the other input terminal (e.g., the negative phase input terminal) of the integrating amplifier module 210 through resistors Rin3 and Rin4. The drive signal OUTA is fed back to the positive input terminal of the integrating amplifier module 210 through resistor Rfb1, and the drive signal OUTB is fed back to the negative input terminal of the integrating amplifier module 210 through resistor Rfb2. The error integrator AMP integrates the difference between the input analog signals INA and INB and the drive signals OUTA and OUTB, and outputs differential output signals OPA and OPB with positive and negative phases from two output terminals to indicate the integration result.

[0030] Various types of error integrators can be used as integral amplifier modules 210. Figure 2In the example shown in FIG. 2, the integral amplification module 210 includes an error integrator AMP and capacitors CI and C2. The positive input terminal (+ input terminal) and the negative input terminal (- input terminal) of the error integrator AMP are used as the positive input terminal and the negative input terminal of the integral amplification module 210, respectively, and the positive output terminal (+ output terminal) and the negative output terminal (- output terminal) of the error integrator AMP are used as the positive output terminal and the negative output terminal of the integral amplification module 210, respectively. The capacitor CI for integrating the error is coupled between the positive input terminal and the negative output terminal of the error integrator AMP, and the capacitor C2 for integrating the error is also coupled between the negative input terminal and the positive output terminal of the error integrator AMP.

[0031] The signal modulation module 220 is configured to input the corrected differential output signals OP A and OPB, respectively, and generate a first pulse width modulation signal PWMA and a second pulse width modulation signal PWMB according to the differential output signals OP A and OPB. The first pulse width modulation signal PWMA is modulated by the differential output signal OP A, and the second pulse width modulation signal PWMB is modulated by the differential output signal OPB. Specifically, the signal modulation module 220 can include two parallel comparators CMP1 and CMP2. The comparator CMP1 is configured to compare the differential output signal OP A with a modulation signal RAMP and output the first pulse width modulation signal PWMA. The comparator CMP2 is configured to compare the differential output signal OPB with the modulation signal RAMP and output the second pulse width modulation signal PWMB. The modulation signal RAMP is usually a waveform with periodic inclined rising and inclined falling edges, such as a triangular wave or a sawtooth wave. In this way, the two differential signals can be conveniently modulated into PWM signals. Of course, the signal modulation module 220 can also use other circuit structures to implement PWM modulation.

[0032] The drive output module 230 is configured to amplify the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB respectively to obtain the drive signals OUTA and OUTB. The drive output module 230 can be implemented by a half-bridge circuit including two transistors connected in series between a power supply and a ground. When the input pulse width modulation signal is at a high level, the transistor coupled to the power supply is turned on and the transistor coupled to the ground is turned off, so as to output a voltage and current defined by the power supply. When the input pulse width modulation signal is at a low level, the transistor coupled to the ground is turned on and the transistor coupled to the power supply is turned off, so as to amplify the PWM signal. It should be noted that the integral amplification module 210 and the signal modulation module 220 of the present embodiment are usually powered by a low voltage domain power supply VDD generated by a low dropout linear regulator (LDO) (not shown in the figure) inside the chip, and the VDD is usually about 4V-6V. The power supply of the drive output module 230 is usually a high voltage domain power supply PVDD (not shown in the figure) input from outside the chip, which can be as low as 4V and as high as 30V, and is usually about 20V-30V.

[0033] Further, the audio power amplifier circuit 200 of the present embodiment further includes a power limiting module 240 arranged between the output terminal and the input terminal of the integral amplification module 210. The power limiting module 240 is configured to adjust the amplitude of the input current of the input terminal of the integral amplification module 210 according to the output terminal signal of the integral amplification module 210, so as to adjust the amplitude of the output voltage by controlling the input current.

[0034] In the present embodiment, the power limiting module 240 is configured to compare the differential output signals OP A and OPB output by the integral amplification module 210 with a threshold voltage VLIMIT, and adjust the amplitudes of the input currents INA_in and INB_in of the integral amplification module 210 according to the comparison result, so as to limit the levels of the differential output signals OP A and OPB within a preset amplitude range after the integral amplification by the error integrator AMP, thereby adjusting the output power. The amplitude range can be preset according to the requirement of limiting the output power.

[0035] Further, the audio power amplifier circuit 200 of the embodiment further comprises a switch K1 disposed in the input path of the input analog signals INA and INB to the integrative amplification module 210, and a gain control module 250. The switch K1 is disposed between the common coupling point of the resistors Rin1 and Rin2 and the common coupling point of the resistors Rin3 and Rin4. The power limiting module is configured to generate an enable control signal AGC_EN while performing the clamping, and the gain control module 250 adjusts the duty cycle of the switch K1 in response to the enable control signal AGC_EN, so that the gain of the integrative amplification module 210 can be reduced while limiting the output power of the circuit. The switch K1 is configured by, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and when the enable control signal AGC_EN is input to the gain control module 250, the gain control module 250 outputs a PWM signal with gradually increasing duty cycle to the switch K1 to intermittently turn on the switch K1, so as to reduce the gain of the integrative amplification module 210.

[0036] In this embodiment, when the circuit is normally working, the enable control signal AGC_EN is at logic low level "0", the gain control module 250 does not work, at this time the switch K1 remains off, at this time the gain of the circuit is the normal gain. When the circuit triggers power limiting, the enable control signal AGC_EN flips to logic high level "1", the gain control module 250 starts to work, gradually increases the duty cycle of the switch K1 according to the set linearity, so that the output harmonic distortion rate can be reduced to below 0.5%, so that the loudspeaker in the later stage can be protected while the sound quality is ensured.

[0037] Figure 3 A circuit schematic diagram of a power limiting module according to an embodiment of the present application is shown. The power limiting module 300 can be used to implement the power limiting module 240 in Figure 2 . The power limiting module 300 comprises a reference current generation circuit 310, a comparison circuit 320, an adjustment current output circuit 330, and an enable detection circuit 340.

[0038] The reference current generation circuit 310 comprises a P-channel transistor MP1 and a current source 305. The source of the P-channel transistor MP1 is coupled to the power supply voltage VDD, and the gate and the drain are coupled to the first end of the current source 305, and the second end of the current source 305 is grounded. The current source 305 is configured to generate a reference current Iref, and the P-channel transistor MP1 provides the reference current to the comparison circuit 320 and the enable detection circuit 340 by mirroring.

[0039] The comparison circuit 320 includes N-channel transistors MN1 and MN2 and P-channel transistors MP2 and MP3. The sources of the P-channel transistors MP2 and MP3 are coupled to the power supply voltage VDD, the gates of the P-channel transistors MP2 and MP3 are coupled to the gate of the P-channel transistor MP1, the drain of the P-channel transistor MP2 is coupled to the first node 301, and the drain of the P-channel transistor MP3 is coupled to the second node 302. The sources of the N-channel transistors MN1 and MN2 are coupled to the differential output signals OP A and OPB respectively, the gates of the N-channel transistors MN1 and MN2 are coupled to the threshold voltage VLIMIT, the drain of the N-channel transistor MN1 is coupled to the first node 301, and the drain of the N-channel transistor MN2 is coupled to the second node 302.

[0040] The adjustment current output circuit 330 includes P-channel transistors MP11 and MP10 and a current conversion unit 304. The source of the P-channel transistor MP11 is coupled to the power supply voltage VDD, the gate and the drain are coupled to the second node 302, the source of the P-channel transistor MP10 is coupled to the power supply voltage VDD, and the gate and the drain are coupled to the first node 301. The input end of the current conversion unit 304 is coupled to the gate and the drain of the P-channel transistors MP11 and MP10, and the output end is used to output the adjustment currents Iout1 and Iout2.

[0041] The enable detection circuit 340 includes P-channel transistors MP4 to MP9, a current source 306 and a Schmitt trigger 307. The source of the P-channel transistor MP6 is coupled to the first node 301, the gate and the drain are coupled to the drain of the N-channel transistor MN1, the source of the P-channel transistor MP7 is coupled to the second node 302, and the gate and the drain are coupled to the drain of the N-channel transistor MN2. The source of the P-channel transistor MP4 is coupled to the power supply voltage VDD, the gate is coupled to the gate of the P-channel transistor MP1, and the drain is coupled to the source of the P-channel transistor MP8. The gate of the P-channel transistor MP8 is coupled to the gate of the P-channel transistor MP7, and the drain of the P-channel transistor MP8 is coupled to the third node 303. The source of the P-channel transistor MP5 is coupled to the power supply voltage VDD, the gate is coupled to the gate of the P-channel transistor MP1, and the drain is coupled to the source of the P-channel transistor MP9. The gate of the P-channel transistor MP9 is coupled to the gate of the P-channel transistor MP6, and the drain of the P-channel transistor MP9 is coupled to the third node 303. The first end of the current source 306 is coupled to the third node 303, and the second end is grounded. The input end of the Schmitt trigger 307 is coupled to the third node 303, and the output end is used to output the enable control signal AGC EN.

[0042] The following will be described in combination with Figure 3The working process of the power limiting module of the embodiment of the present application is described in detail. When the voltage of the input analog signal is low (i.e. |INA-INB| is low), the differential output signals OPA and OPB of the integral amplification module 210 are both greater than VLIMIT-Vt, wherein Vt is the conduction threshold of the N-channel transistor, the N-channel transistors MN1 and MN2 are both turned off, the P-channel transistors MP6 to MP9 are also turned off, and the branch in which the P-channel transistors MP10 and MP11 are located also has no current, so the adjustment currents Iout1 and Iout2 are both zero, and the third node 303 is also pulled low to logic low level "0" by the current source 306, so the enable control signal AGC_EN is also logic low level "0", at this time the audio power amplifier circuit 200 does not perform clamping, and it also maintains normal gain operation. With the gradual increase of the voltage of the analog input signal, when one of the differential output signals OPA and OPB is lower than VLIMIT-Vt, taking the level of the output signal OPA as an example, at this time the N-channel transistor MN1 is turned off, the N-channel transistor MN2 is turned on, the gate of the P-channel transistor MP7 is pulled low, and then the P-channel transistors MP7 and MP8 are also turned on. The current I1 flows through the P-channel transistor MP7 and the N-channel transistor MN2, and the current I2 is obtained by the P-channel transistor MP3 mirroring the current in the P-channel transistor MP1, because the size ratio of the P-channel transistors MP2 and MP3 to MP1 is 1, so the current I2 = Iref. When the current I1 is greater than the reference current Iref, the second node 302 is pulled low, which is equivalent to the gate of the P-channel transistor MP11 being pulled low, so the P-channel transistor MP11 is turned on, and the current I3 flows through the P-channel transistor MP11. The current conversion unit 304 generates the adjustment currents Iout1 and Iout2 which are equal in size and opposite in direction according to the current I3, and applies them to the input terminal of the integral amplification module 210, so as to achieve the purpose of adjusting the amplitude of the input current of the integral amplification module 210. At the same time, the current I4 is obtained by the P-channel transistor MP4 mirroring the P-channel transistor MP1, so the current I4 flows through the P-channel transistors MP4 and MP8. Because the size ratio of the P-channel transistors MP4 and MP5 to the P-channel transistor MP1 is n, n is an integer greater than 1 (for example, n = 2), so the current I4 = 2*Iref can be obtained.At this time, the third node 303 is pulled high to logic high "1" by the current I4, thus the enable control signal AGC_EN is also flipped to logic high "1", the gain control module 250 outputs the duty cycle of switch K1 gradually increasing according to the set linearity based on the high enable control signal AGC_EN, so that the overall gain of the chip gradually decreases, until the voltage of the differential output signal OP A is greater than VLIMIT-Vt, the N-channel transistor MN2 is turned off, the enable control signal AGC_EN is flipped to logic low "0" again, the duty cycle output by the gain control module 250 starts to gradually decrease, and the overall gain of the chip starts to gradually recover. In further embodiments, the gain of the chip can be maintained at a reasonable dynamic balance point by controlling the time of gain attenuation and recovery of the chip (i.e. the parameters of the gain control module 250), so as to ensure that the THD output in the steady state is maintained below 0.5%.

[0043] In addition, the P-channel transistors MP6 to MP9 in the present embodiment mainly serve the purpose of soft transition between the power limiting mode and the gain adjustment mode. When the input signal suddenly increases, the power limiting mode plays a major role, which can quickly limit the voltage of the output signal to a preset voltage range. At this time, the enable control signal AGC_EN is logic high, but it still takes a certain time (for example, several milliseconds) for the duty cycle of the signal output by the gain control module to increase from 0% to the required value. As the gain of the chip gradually decreases, the current flowing through the N-channel transistors MN1 and MN2 also gradually decreases. When the current is less than the reference current Iref, the currents Iout1 and Iout2 become zero. At this time, only the gain attenuation mode is in effect in the chip, and the output signal is limited by attenuating the gain. Such a design can make the output THD of the circuit optimal, and ensure that the circuit is always in an optimal working state.

[0044] Figure 4a and Figure 4b respectively show the output waveform diagrams of the prior art audio power amplifier circuit and the audio power amplifier circuit of the embodiment of the present application. In the conventional audio power amplifier circuit, when the input analog signal of the chip increases, the output voltage of the integral amplification module also increases. When the voltage value of one of the output signals is lower than the set threshold voltage, the power limiting module generates two-way current feedback to the input terminal of the integral amplification module, which equivalently reduces the input voltage of the chip, thereby limiting the output voltage of the circuit within the voltage range set by the threshold voltage. The waveform diagram is shown in Figure 4a As can be seen from Figure 4a , when the level of the drive signal is limited to a certain voltage range by the threshold voltage, the output signal of the loudspeaker will produce obvious wave cancellation, which will make the THD (harmonic distortion rate) of the circuit output worse, and have a very serious impact on the sound quality. In the audio power amplifier circuit of the embodiment of the present application, as shown inFigure 4b As shown, when the input analog signal suddenly increases, the power limiting module triggers gain attenuation while quickly limiting the voltage of the output drive signal within the preset voltage range, avoiding the generation of the speaker output signal, so that the output THD of the circuit is optimal, and the circuit is always in an optimal working state.

[0045] In summary, when the input analog signal suddenly increases, the power limiting module of the audio power amplifier circuit in the embodiment of the present application limits the level of the output signal of the integral amplification module within the specified level range through the feedback clamping mode, and the gain control module simultaneously reduces the gain of the integral amplification module in response to the clamping performed by the power limiting module, so that the overall gain of the circuit can be attenuated while limiting the voltage of the drive signal output by the circuit within the preset voltage range, ensuring the waveform integrity of the output signal, avoiding the generation of the speaker output signal, and improving the output sound quality level.

[0046] Those of ordinary skill in the art can understand that the words "during", "when", and "when" used in relation to the operation of the circuit in this paper are not strict terms indicating actions that occur immediately at the start of the start action, but there may be some small but reasonable one or more delays between them and the reaction initiated by the start action, such as various transmission delays, etc. The use of the word "about" or "essentially" in this paper means that the element value has a parameter close to the declared value or position. However, as is well known in the art, there is always a slight deviation so that the value or position is difficult to be strictly the declared value. It has been appropriately determined in the art that a deviation of at least ten percent (10%) (at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state (e.g. "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0047] Furthermore, the terminology and phraseology employed herein are for the purpose of describing the exemplary embodiments with the utmost specificity and is not intended to be limiting. It is also noted that the use of "including", "comprising", or "having" and variations thereof in this description are taken open-ended to mean that other additions are possible, but not exclusive. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. In addition, the use of "including" and "comprising" and variations thereof are intended to be broad and encompass the occurrence of zero, one or more of the stated elements. Furthermore, the use of "a" or "an" is intended to mean "one or more" in the context of describing the exemplary embodiments. It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component" can include a plurality of such components. In this context, the term "plurality" means two or more.

[0048] In accordance with the present application, the embodiments as described above are not the only possible implementations of the present application. Numerous modifications and adaptations will be apparent to those skilled in the art without departing from the scope of the present application. The scope of the present application is defined by the following claims.

Claims

1. An audio power amplifier circuit, comprising: The integral amplifier module is used to amplify the differential input signal through integration to obtain the differential output signal; The signal modulation module is used to generate a first pulse width modulation signal and a second pulse width modulation signal based on the differential output signal; The drive output module is used to amplify the first pulse width modulation signal and the second pulse width modulation signal respectively to obtain the drive signal for driving the speaker; A power limiting module is used to limit the level of the differential output signal within a specified level range by clamping; as well as The gain control module, in response to the clamping action performed by the power limiting module, synchronously reduces the gain of the integrating amplifier module. The audio power amplifier circuit also includes a high-frequency switch disposed between the input resistors of the integrating amplifier module. The power limiting module is configured to generate an enable control signal while performing the clamping, and the gain control module, in response to the enable control signal, reduces the gain of the integrating amplifier module by increasing the duty cycle of the high-frequency switch. The power limiting module includes: A comparison circuit, coupled to the output of the integrating amplifier module, is used to convert the comparison result of the differential output signal and the threshold voltage into a current signal, and to compare the current signal with a reference current. An adjustment current output circuit, coupled to the input terminals of the comparator circuit and the integrating amplifier module, is used to adjust the input current of the integrating amplifier module based on the comparison result of the current signal and the reference current; and An enable detection circuit, coupled to the comparator circuit, is used to synchronously output the enable control signal under the control of the comparator circuit.

2. The audio power amplifier circuit according to claim 1, wherein, The power limiting module also includes: A reference current generation circuit is used to generate the reference current.

3. The audio power amplifier circuit according to claim 2, wherein, The reference current generation circuit includes: A first P-channel transistor and a first current source are sequentially coupled between a power supply voltage and ground, and the control terminal and the second terminal of the first P-channel transistor are coupled to each other.

4. The audio power amplifier circuit according to claim 3, wherein, The comparison circuit includes: The first N-channel transistor has a first terminal coupled to a first node, a control terminal coupled to the threshold voltage, and a second terminal coupled to one of the differential output signals. The second N-channel transistor has a first terminal coupled to the second node, a control terminal coupled to the threshold voltage, and a second terminal coupled to another of the differential output signals. A second P-channel transistor has a first terminal coupled to the power supply voltage, a second terminal coupled to the first node, and a control terminal coupled to the control terminal of the first P-channel transistor; and The third P-channel transistor has a first terminal coupled to the power supply voltage, a second terminal coupled to the second node, and a control terminal coupled to the control terminal of the first P-channel transistor.

5. The audio power amplifier circuit according to claim 4, wherein, The adjustable current output circuit includes: A tenth P-channel transistor coupled between the power supply voltage and the first node, wherein the control terminal and the second terminal of the tenth P-channel transistor are coupled to each other. An eleventh P-channel transistor coupled between the power supply voltage and the second node, wherein the control terminal and the second terminal of the eleventh P-channel transistor are coupled to each other; and The current conversion unit is used to convert the current in the eleventh P-channel transistor or the tenth P-channel transistor into a differential adjustment current applied to the input terminal of the integrating amplifier module.

6. The audio power amplifier circuit according to claim 4, wherein, The enable detection circuit includes: A sixth P-channel transistor is coupled between the first node and the first terminal of the first N-channel transistor, and the control terminal and the second terminal of the sixth P-channel transistor are coupled to each other. A seventh P-channel transistor is coupled between the second node and the first terminal of the second N-channel transistor, and the control terminal and the second terminal of the seventh P-channel transistor are coupled to each other. A fourth and an eighth P-channel transistor are sequentially coupled between the power supply voltage and the third node. The control terminal of the fourth P-channel transistor is coupled to the control terminal of the first P-channel transistor, and the control terminal of the eighth P-channel transistor is coupled to the control terminal of the seventh P-channel transistor. A fifth and a ninth P-channel transistor are sequentially coupled between the power supply voltage and the third node. The control terminal of the fifth P-channel transistor is coupled to the control terminal of the first P-channel transistor, and the control terminal of the ninth P-channel transistor is coupled to the control terminal of the sixth P-channel transistor. A second current source coupled between the third node and ground; and A Schmitt trigger, the input of which is coupled to the third node, and the output of which is used to output the enable control signal.

7. The audio power amplifier circuit according to claim 4, wherein, The size ratio of the third P-channel transistor and the second P-channel transistor to the first P-channel transistor is 1.

8. The audio power amplifier circuit according to claim 6, wherein, The size ratio of the fourth P-channel transistor and the fifth P-channel transistor to the first P-channel transistor is n, where n is an integer greater than 1.

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