A synchronous signal selection circuit and module

Abstract

The present application discloses a synchronization signal selection circuit and module, which belongs to the field of electronic circuit technology and can be applied to autonomous driving scenarios. The synchronization signal selection circuit includes a control module, a first high-level module, a second high-level module and a low-level module. The first high-level module outputs a first high-level signal representing a high-level signal of an external synchronization signal under the control of an external synchronization signal and a first control signal sent by the control module, or stops outputting the first high-level signal. The second high-level module outputs a second high-level signal representing a high-level signal of an internal synchronization signal under the control of an internal synchronization signal and a second control signal sent by the control module, or stops outputting the second high-level signal. The low-level module outputs a low-level signal when the first high-level module stops outputting the first high-level signal or when the second high-level module stops outputting the second high-level signal, thereby realizing the selection of a synchronization signal output and improving the flexibility of the system.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic circuit technology, and in particular to a synchronization signal selection circuit and module. Background Art

[0002] With the development of assisted driving and autonomous driving technologies, integrated navigation equipment has become the core equipment for vehicle location acquisition and synchronization of various sensors. As the hardware carrier of autonomous driving technology, the autonomous driving controller is responsible for synchronizing various autonomous driving sensors. In the industry, the pulse-per-second signal (PPS) output by the integrated navigation equipment is generally input into the autonomous driving controller, which uses the PPS as a synchronization signal and outputs it to the autonomous driving sensor for synchronization after internal acquisition and synchronization.

[0003] With the rapid development of the chip industry, combined navigation equipment is also developing towards miniaturization and chipization. At the same time, many manufacturers also tend to integrate combined navigation equipment into the autonomous driving controller as part of the integrated circuit, providing the PPS synchronization signal for the autonomous driving controller and outputting the synchronization signal to the autonomous driving sensor for synchronization.

[0004] In summary, the synchronization signal of the automatic driving controller has two sources, which can be provided by the integrated navigation module inside the automatic driving controller or by the integrated navigation device outside the automatic driving controller. Therefore, when there are two sources of synchronization signals, how to select the synchronization signals from two different sources becomes an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The embodiments of the present application provide a synchronization signal selection circuit and module to solve the problem that the autonomous driving controller cannot select two synchronization signals from different sources.

[0006] In a first aspect, an embodiment of the present application provides a synchronization signal selection circuit, comprising: a control module, a first high level module, a second high level module and a low level module;

[0007] The control module is connected to the first control end of the first high-level module and the first control end of the second high-level module respectively, the second control end of the first high-level module is used to input an external synchronization signal, and the second control end of the second high-level module is used to input an internal synchronization signal, the output end of the first high-level module is connected to the output end of the second high-level module and the output end of the low-level module, and is used to output a target synchronization signal, and the input end of the low-level module is grounded;

[0008] The control module is used to send a first control signal to the first high-level module, and send a second control signal to the second high-level module;

[0009] The first high-level module is used to output a first high-level signal representing a high-level signal of the external synchronization signal, or stop outputting the first high-level signal, under the control of the first control signal and the external synchronization signal;

[0010] The second high level module is used to output a second high level signal representing a high level signal of the internal synchronization signal, or stop outputting the second high level signal, under the control of the second control signal and the internal synchronization signal;

[0011] The low-level module is configured to output a low-level signal when the first high-level module stops outputting the first high-level signal or when the second high-level module stops outputting the second high-level signal.

[0012] In the synchronization signal selection circuit provided in the embodiment of the present application, the control module sends a first control signal to the first high-level module and sends a second control signal to the second high-level module. Since the first high-level module can output a first high-level signal for representing a high-level signal of an external synchronization signal, or stop outputting the first high-level signal under the control of the first control signal and the external synchronization signal, the second high-level module can output a second high-level signal for representing a high-level signal of an internal synchronization signal, or stop outputting the second high-level signal under the control of the second control signal and the internal synchronization signal, and the low-level module can output a low-level signal when the first high-level module stops outputting the first high-level signal, or when the second high-level module stops outputting the second high-level signal. Therefore, the synchronization signal selection circuit disclosed in the embodiment of the present application can realize the selection of external synchronization signals and internal synchronization signals, thereby improving the flexibility of the system.

[0013] In a possible implementation manner, the first high-level module is specifically used to:

[0014] If the first control signal is a high level signal and the external synchronization signal is a high level, outputting the first high level signal;

[0015] If the first control signal is a high level signal and the external synchronization signal is a low level signal, then stop outputting the first high level signal;

[0016] If the first control signal is a low level signal, the output of the first high level signal is stopped.

[0017] By adopting the above method, the first high-level module always stops outputting the first high-level signal when the first control signal is at a low level, and cooperates with the second high-level module to output the second high-level signal used to characterize the internal synchronization signal. When the first control signal is at a high level, if the external synchronization signal is a high electrical frequency, the first high-level signal used to characterize the external synchronization signal is output; if the external synchronization signal is at a low level, it cooperates with the low-level module to output a low-level signal, so that the output target synchronization signal has the same pulse width as the external synchronization signal, thereby realizing the selection of outputting the target synchronization signal with the same pulse width as the external synchronization signal.

[0018] In a possible implementation manner, the second high-level module is specifically used to:

[0019] If the second control signal is a high level signal and the internal synchronization signal is a high level, outputting the second high level signal;

[0020] If the second control signal is a high level signal and the internal synchronization signal is a low level signal, then stop outputting the second high level signal;

[0021] If the second control signal is at a low level, the output of the second high level signal is stopped.

[0022] By adopting the above method, the second high-level module always stops outputting the second high-level signal when the first control signal is at a low level, and cooperates with the first high-level module to output the first high-level signal used to characterize the external synchronization signal. When the second control signal is at a high level, if the internal synchronization signal is at a high electrical frequency, the second high-level signal used to characterize the internal synchronization signal is output; if the internal synchronization signal is at a low level, it cooperates with the low-level module to output a low-level signal, so that the output target synchronization signal has the same pulse width as the internal synchronization signal, thereby realizing the selection of outputting the target synchronization signal with the same pulse width as the internal synchronization signal.

[0023] In a possible implementation, the first high-level module includes a first direct current source and a first conduction unit;

[0024] The negative electrode of the first DC source is grounded, and the positive electrode of the first DC source is connected to the first conducting unit;

[0025] The first conduction unit is used to conduct the path between the positive electrode of the first DC source and the output end of the first conduction unit to output the first high-level signal when the first control signal is a high-level signal and the external synchronization signal is a high-level signal, and to disconnect the path between the positive electrode of the first DC source and the output end of the first conduction unit to stop outputting the first high-level signal when the first control signal is a high-level signal and the external synchronization signal is a low-level signal, and to disconnect the path between the positive electrode of the first DC source and the output end of the first conduction unit to stop outputting the first high-level signal when the first control signal is a low-level signal.

[0026] By adopting the above manner, the outputted first high-level signal is related to the first DC source. Since the voltage outputted by the DC source is relatively stable, the stability of the first high-level signal can be improved.

[0027] In a possible implementation, the first conduction unit includes a first resistor, a first diode, a second diode, and a third diode;

[0028] The first end of the first resistor is connected to the positive electrode of the first DC source, and the second end of the first resistor is connected to the anode of the first diode, the anode of the second diode, and the anode of the third diode;

[0029] The cathode of the first diode serves as the first control terminal of the first high level module;

[0030] The cathode of the second diode serves as the second control terminal of the first high level module;

[0031] The cathode of the third diode serves as the output end of the first high level module.

[0032] By adopting the above method, the first conduction unit is turned on by a diode. Since the diode conducts electricity in a unidirectional manner, the structure of the first conduction unit can be simplified.

[0033] In a possible implementation, the second high-level module includes a second direct current source and a second conduction unit;

[0034] The negative electrode of the second DC source is grounded, and the positive electrode of the second DC source is connected to the second conducting unit;

[0035] The second conduction unit is used to conduct the path between the positive electrode of the second DC source and the output end of the second conduction unit to output the second high-level signal when the second control signal is a high-level signal and the internal synchronization signal is a high-level signal, and to disconnect the path between the positive electrode of the second DC source and the output end of the second conduction unit to stop outputting the second high-level signal when the second control signal is a high-level signal and the internal synchronization signal is a low-level signal, and to disconnect the path between the positive electrode of the second DC source and the output end of the second conduction unit to stop outputting the second high-level signal when the second control signal is a low-level signal.

[0036] By adopting the above manner, the output second high level signal is related to the second DC source. Since the voltage output by the DC source is relatively stable, the stability of the second high level signal can be improved.

[0037] In a possible implementation, the second conduction unit includes a second resistor, a fourth diode, a fifth diode and a sixth diode;

[0038] A first end of the second resistor is connected to the positive electrode of the second DC source, and a second end of the second resistor is connected to the anode of the fourth diode, the anode of the fifth diode, and the anode of the sixth diode;

[0039] The cathode of the fourth diode serves as the first control terminal of the second high level module;

[0040] The cathode of the fifth diode serves as the second control terminal of the second high level module;

[0041] The cathode of the sixth diode serves as the output end of the second high level module.

[0042] By adopting the above method, the conduction of the second conduction unit is achieved through the diode. Since the diode conducts unidirectionally, the structure of the second conduction unit can be simplified.

[0043] In a possible implementation, the low-level module includes a third resistor;

[0044] The first end of the third resistor serves as the output end of the low-level module, and the second end of the third resistor serves as the input end of the low-level module.

[0045] By adopting the above method and using the voltage division performance of the resistor to realize the solution of the low-level module outputting a low level, the design difficulty of the low-level module can be reduced.

[0046] In a possible implementation, a matching unit is also included;

[0047] The matching unit is used to perform preset processing on the target synchronization signal to obtain a processed synchronization signal, wherein the preset processing includes part or all of the following:

[0048] Impedance matching, debouncing, filtering, protection, buffering and level conversion.

[0049] By adopting the above method, the resistance matching is performed on the target synchronization voltage, and the driving capability of the target synchronization signal is improved, thereby improving the application range of the synchronization signal selection circuit.

[0050] In a second aspect, an embodiment of the present application further provides a synchronization signal selection module, comprising a synchronization signal selection circuit as described in any one of the first aspects.

[0051] For the technical effects that may be achieved by the synchronization signal generating module disclosed in the second aspect, please refer to the technical effects that may be achieved by the first aspect or various possible solutions in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 Schematic diagram of application scenarios provided for related technologies;

[0053] Figure 2 A schematic diagram of the structure of a synchronization signal selection circuit provided in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of the structure of another synchronization signal selection circuit provided in an embodiment of the present application;

[0055] Figure 4 A circuit diagram of a synchronization signal selection circuit provided in an embodiment of the present application;

[0056] Figure 5 A circuit diagram of another synchronization signal selection circuit provided in an embodiment of the present application;

[0057] Figure 6 A simulation schematic diagram of a target synchronization signal provided in an embodiment of the present application;

[0058] Figure 7 A simulation schematic diagram of another target synchronization signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] In the related technology, the combined navigation device can output PPS to the automatic driving controller. The PPS is a digital square wave signal and can be used as a synchronization signal of the automatic driving controller. The automatic driving controller samples at the rising edge or falling edge of the PPS.

[0061] As the hardware carrier of autonomous driving technology, the autonomous driving controller is responsible for synchronizing various autonomous driving sensors, such as Figure 1 As shown, currently the synchronization signal of the automatic driving controller 10 has two sources, one is provided by the combined navigation module 101 inside the automatic driving controller 10, and the other is provided by the external combined navigation device 11. When there are two sources of synchronization signals, it is necessary to select one synchronization signal as the target synchronization signal.

[0062] The following describes the data transmission method provided by the exemplary embodiment of the present application in combination with the application scenario described above and with reference to the accompanying drawings. It should be noted that the above application scenario is only shown to facilitate understanding of the spirit and principles of the present application, and the implementation of the present application is not limited in this respect.

[0063] like Figure 2 As shown, a synchronization signal selection circuit provided by an embodiment of the present invention includes: a control module 20, a first high level module 21, a second high level module 22 and a low level module 23;

[0064] The control module 20 is connected to the first control end of the first high-level module 21 and the first control end of the second high-level module 22 respectively, the second control end of the first high-level module 21 is used to input the external synchronization signal Singal_Input1, and the second control end of the second high-level module 22 is used to input the internal synchronization signal Singal_Input2, the output end of the first high-level module 21 is connected to the output end of the second high-level module 22 and the output end of the low-level module 23, and is used to output the target synchronization signal Singal_Output, and the input end of the low-level module 23 is grounded;

[0065] The control module 20 is used to send a first control signal Singal_Ctrl1 to the first high level module 21, and send a second control signal Singal_Ctrl2 to the second high level module 22;

[0066] A first high level module 21 is used to output a first high level signal representing a high level signal of an external synchronization signal, or stop outputting the first high level signal, under the control of a first control signal Singal_Ctrl1 and an external synchronization signal Singal_Input1;

[0067] The second high level module 22 is used to output a second high level signal representing a high level signal of the internal synchronization signal, or stop outputting the second high level signal under the control of the second control signal Singal_Ctrl2 and the internal synchronization signal Singal_Input2;

[0068] The low level module 23 is used to output a low level signal when the first high level module stops outputting the first high level signal or when the second high level module stops outputting the second high level signal.

[0069] In the embodiment of the present application, the control module 20 sends the first control signal Singal_Ctrl1 to the first high-level module 21, and sends the second control signal Singal_Ctrl2 to the second high-level module 22. Since the first high-level module 21 can output a first high-level signal for representing a high-level signal of an external synchronization signal, or stop outputting the first high-level signal under the control of the first control signal Singal_Ctrl1 and the external synchronization signal Singal_Input1, the second high-level module 22 can output a second high-level signal for representing a high-level signal of an internal synchronization signal, or stop outputting the second high-level signal under the control of the second control signal Singal_Ctrl2 and the internal synchronization signal Singal_Input2, and the low-level module 23 can output a low-level signal when the first high-level module 21 stops outputting the first high-level signal, or when the second high-level module 22 stops outputting the second high-level signal. Therefore, the synchronization signal selection circuit disclosed in the embodiment of the present application can realize the selection of the external synchronization signal Singal_Input1 and the internal synchronization signal Singal_Input2, thereby improving the flexibility of the system.

[0070] It should be noted that, in the embodiment of the present application, the first high-level signal and the low-level signal used to characterize the high-level signal of the external synchronization signal can constitute a target synchronization signal, the pulse width of the target synchronization signal is the same as the pulse width of the external synchronization signal, and the high-level signal of the target synchronization signal is related to the high-level signal of the external synchronization signal, that is, the high-level signal of the target synchronization signal can be the same as or different from the high-level signal of the external synchronization signal;

[0071] Similarly, the second high-level signal and the low-level signal used to characterize the high-level signal of the internal synchronization signal can also constitute a target synchronization signal. The pulse width of the target synchronization signal is the same as the pulse width of the internal synchronization signal, and the high-level signal of the target synchronization signal is related to the high-level signal of the internal synchronization signal, that is, the high-level signal of the target synchronization signal and the high-level signal of the internal synchronization signal can be the same or different.

[0072] In the embodiment of the present application, since the target synchronization signal output by the synchronization signal selection circuit is the same as the pulse width of the external synchronization signal, or the same as the pulse width of the internal synchronization signal, the first control signal Singal_Ctrl1 and the second control signal Singal_Ctrl2 output by the control module 20 are different. For example, when the first control signal Singal_Ctrl1 is a high-level signal, the second control signal Singal_Ctrl2 is a low-level signal; when the first control signal Singal_Ctrl1 is a low-level signal, the second control signal Singal_Ctrl2 is a high-level signal.

[0073] In the implementation of this application, the control module 20 may be a micro control unit (Micro o Controller Unit, MCU).

[0074] In a specific implementation, the first high level module 21 is specifically used for:

[0075] If the first control signal Singal_Ctrl1 is a high level signal and the external synchronization signal Singal_Input1 is a high level signal, then a first high level signal is output;

[0076] If the first control signal Singal_Ctrl1 is a high level signal and the external synchronization signal Singal_Input1 is a low level signal, then the output of the first high level signal is stopped;

[0077] If the first control signal Singal_Ctrl1 is a low level signal, the output of the first high level signal is stopped.

[0078] In the embodiment of the present application, the first high-level module 21 inputs the first control signal Singal_Ctrl1 and the external synchronization signal Singal_Input1. If the first control signal Singal_Ctrl1 is a low-level signal, the first high-level module 21 stops outputting the first high-level signal. If the first control signal Singal_Ctrl1 is a high-level signal and the external synchronization signal Singal_Input1 is a high-level signal, the first high-level signal is output. If the first control signal Singal_Ctrl1 is a high-level signal and the external synchronization signal Singal_Input1 is a low-level signal, the first high-level signal is stopped from being output. The first high-level signal is used to characterize the high-level signal of the external synchronization signal. When the first control signal Singal_Ctrl1 is a high-level signal and the external synchronization signal Singal_Input1 is a low-level signal, the first high-level signal is output. gal_Input1 is a low level signal, the first high level module 21 stops outputting the first high level signal, and the low level module 23 outputs a low level signal at this time, that is, when the first control signal Singal_Ctrl1 is a low level signal, the signal output by the first high level module 21 is independent of the external synchronization signal Singal_Input1, and when the first control signal Singal_Ctrl1 is a high level signal, the first high level module 21 outputs the first high level signal when the external synchronization signal Singal_Input1 is a high level signal, and when the external synchronization signal Singal_Input1 is a low level signal, the low level module 23 outputs a low level signal, and the first high level signal and the low level signal constitute a target synchronization signal, and the pulse width of the target synchronization signal is the same as the pulse width of the external synchronization signal Singal_Input1.

[0079] The second high level module 22 is specifically used for:

[0080] If the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a high level signal, then a second high level signal is output;

[0081] If the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a low level signal, then the output of the second high level signal is stopped;

[0082] If the second control signal Singal_Ctrl2 is a low level signal, the output of the second high level signal is stopped.

[0083] In the embodiment of the present application, the second high level module 22 inputs the second control signal Singal_Ctrl2 and the internal synchronization signal Singal_Input2. If the second control signal Singal_Ctrl2 is a low level signal, the second high level module 22 stops outputting the second high level signal. If the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a high level signal, the second high level signal is output. If the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a low level signal, the second high level signal is stopped from being output. The second high level signal is used to characterize the high level signal of the internal synchronization signal. When the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a low level signal, the second high level signal is output. gal_Input2 is a low level signal, the second high level module 22 stops outputting the second high level signal, and the low level module 23 outputs a low level signal at this time, that is, when the second control signal Singal_Ctrl2 is a low level signal, the signal output by the second high level module 22 is independent of the internal synchronization signal Singal_Input2, and when the second control signal Singal_Ctrl2 is a high level signal, the second high level module 22 outputs the second high level signal when the internal synchronization signal Singal_Input2 is a high level signal, and when the internal synchronization signal Singal_Input2 is a low level signal, the low level module 23 outputs a low level signal, and the second high level signal and the low level signal constitute a target synchronization signal, and the pulse width of the target synchronization signal is the same as the pulse width of the internal synchronization signal Singal_Input2.

[0084] In implementation, when the first high-level module 21 stops outputting the first high-level signal, the low-level module 23 outputs a low-level signal; when the second high-level module 22 stops outputting the second high-level signal, the low-level module 23 outputs a low-level signal; when the first control signal Singal_Ctrl1 output by the control module 20 is a high-level signal and the second control signal Singal_Ctrl2 is a low-level signal, no matter what level the internal synchronization signal Singal_Input2 is, the second high-level module 22 stops outputting the second high-level signal; if the external synchronization signal Singal_Input1 is a high-level signal, the output end of the first high-level module 21 outputs the first high-level signal; if the external synchronization signal Singal_Input1 is a low-level signal, the first high-level module 21 stops outputting the first high-level signal, and the low-level module 23 outputs a low-level signal, thereby generating a target synchronization signal, at this time, the pulse width of the target synchronization signal is the same as that of the external synchronization signal Singal_Input1; when the first control signal Singal_Ctrl1 output by the control module 20 is a low-level signal and the second control signal Singal_Ctrl2 is a high-level signal, no matter what level the external synchronization signal Singal_Input1 is, the first high-level module 21 always stops outputting the first high-level signal, if the internal synchronization signal Singal_Input2 is a high-level signal, the output end of the second high-level module 22 outputs the second high-level signal, if the external synchronization signal Singal_Input2 is a low-level signal, the second high-level module 22 stops outputting the second high-level signal, and the low-level module 23 outputs a low-level signal, thereby generating a target synchronization signal, at this time, the target synchronization signal and the internal synchronization signal Singal_Input2 have the same pulse width.

[0085] In the specific implementation, Figure 3 As shown, the first high level module 21 may include a first direct current source DC1 and a first conduction unit 210;

[0086] The negative electrode of the first DC source DC1 is grounded, and the positive electrode of the first DC source DC1 is connected to the first conduction unit 210; the first conduction unit 210 is used to conduct the path between the positive electrode of the first DC source DC1 and the output end of the first conduction unit 210 to output the first high level signal when the first control signal Singal_Ctrl1 is a high level signal and the external synchronization signal Singal_Input1 is a high level signal, and to disconnect the path between the positive electrode of the first DC source DC1 and the output end of the first conduction unit 210 to stop outputting the first high level signal when the first control signal Singal_Ctrl1 is a high level signal and the external synchronization signal Singal_Input1 is a low level signal, and to disconnect the path between the positive electrode of the first DC source DC1 and the output end of the first conduction unit 210 to stop outputting the first high level signal when the first control signal Singal_Ctrl1 is a high level signal and the external synchronization signal Singal_Input1 is a low level signal.

[0087] like Figure 3 As shown, the second high level module 22 includes a second DC source DC2 and a second conduction unit 220;

[0088] The negative electrode of the second DC source DC2 is grounded, and the positive electrode of the second DC source DC2 is connected to the second conduction unit 220;

[0089] The second conduction unit 220 is used to conduct the path between the positive electrode of the second DC source DC2 and the output end of the second conduction unit 220 to output the second high level signal when the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a high level signal, and to disconnect the path between the positive electrode of the second DC source DC2 and the output end of the second conduction unit 220 to stop the second high level signal when the second control signal Singal_Ctrl2 is a high level signal and the internal synchronization signal Singal_Input2 is a low level signal, and to disconnect the path between the positive electrode of the second DC source DC2 and the output end of the second conduction unit 220 to stop outputting the second high level signal when the second control signal Singal_Ctrl2 is a low level signal.

[0090] from Figure 3 It can be seen that the first high-level signal outputted by the embodiment of the present application is related to the voltage outputted by the first DC source DC1, and the second high-level signal outputted is related to the voltage outputted by the second DC source DC2. In a specific implementation, the voltage outputted by the first DC source DC1 and the voltage outputted by the second DC source DC2 can be determined according to actual conditions.

[0091] Specifically, Figure 4As shown, the first conduction unit 210 may include a first resistor R1, a first diode D1, a second diode D2 and a third diode D3;

[0092] A first end of the first resistor R1 is connected to the positive electrode of the first DC source DC1, and a second end of the first resistor R1 is connected to the anode of the first diode D1, the anode of the second diode D2, and the anode of the third diode D3;

[0093] The cathode of the first diode D1 serves as the first control terminal of the first high level module 21;

[0094] The cathode of the second diode D2 serves as the second control terminal of the first high level module 21;

[0095] The cathode of the third diode D3 serves as the output end of the first high level module 21 .

[0096] like Figure 4 As shown, the second conduction unit 220 may include a second resistor R2, a fourth diode D4, a fifth diode D5 and a sixth diode D6;

[0097] A first end of the second resistor R2 is connected to the positive electrode of the second DC source DC2, and a second end of the second resistor R2 is connected to the anode of the fourth diode D4, the anode of the fifth diode D5, and the anode of the sixth diode D6;

[0098] The cathode of the fourth diode D4 serves as the first control terminal of the second high level module 22;

[0099] The cathode of the fifth diode D5 serves as the second control terminal of the second high level module 22;

[0100] The cathode of the sixth diode D6 serves as the output end of the second high level module 22 .

[0101] It should be noted that the diode in the embodiment of the present application may be a Schottky diode.

[0102] like Figure 4 As shown, the low level module 23 may include a third resistor R3;

[0103] A first end of the third resistor R3 serves as an output end of the low level module 23 , and a second end of the third resistor R3 serves as an input end of the low level module 23 .

[0104] The following is combined with Figure 4 The embodiments of the present application are described in detail.

[0105] like Figure 4As shown, the input signals of the synchronization signal selection circuit are Singal_Input1 and Singal_Input2, wherein Signal_Input1 represents the external input second pulse signal, that is, the external synchronization signal, and Signal_Input2 represents the internal second pulse signal, that is, the internal synchronization signal.

[0106] The control module 20 outputs a first control signal Singal_Ctrl1 and a second control signal Singal_Ctrl2, wherein the first control signal Singal_Ctrl1 and the second control signal Singal_Ctrl2 are different. For example, when the first control signal Singal_Ctrl1 is a high level signal, the second control signal Singal_Ctrl2 is a low level signal; when the first control signal Singal_Ctrl1 is a low level signal, the second control signal Singal_Ctrl2 is a high level signal.

[0107] The following two cases are used to illustrate the embodiments of the present application:

[0108] Case 1: the first control signal Singal_Ctrl1 is a low level signal, and the second control signal Singal_Ctrl2 is a high level signal.

[0109] When the first control signal Singal_Ctrl1 is a low level signal, the first diode D1 is turned on, the node Net1 is a low level signal, and the third diode D3 is turned off. At this time, no matter what level the external synchronization signal Signal_Input1 is, the third diode D3 is always in the cut-off state; when the second control signal Singal_Ctrl2 is a high level signal, the fourth diode D4 is turned off, the node Net2 is pulled up by the second DC source DC2 through the second resistor R2 (high level signal), the second diode D6 is turned on, and the node Net3 is a high level signal, that is, the second high level signal, which is the voltage obtained by dividing the voltage output by the second DC source DC2 by the second resistor R2; when the internal synchronization signal Sig When nal_Input2 is a low level signal, the fourth diode D4 is turned on, the node Net2 is pulled down (low level signal), the sixth diode D6 is turned off, and the node Net3 is pulled down by the third resistor R3, that is, Singal_Output is a low level signal. When the internal synchronization signal Signal_Input2 is a high level signal, the fourth diode D4 is turned off, and the node Net2 is pulled up by the second DC source DC2 through the second resistor R2, that is, the second high level signal in the embodiment of the present application. The second high level signal is used to characterize the high level signal of the internal synchronization signal. The second high level signal and the low level signal constitute a target synchronization signal, and the pulse width of the target synchronization signal is the same as the pulse width of the internal synchronization signal Signal_Input2.

[0110] Case 2: the first control signal Singal_Ctrl1 is a high level signal, and the second control signal Singal_Ctrl2 is a low level signal.

[0111] When the second control signal Singal_Ctrl2 is a low level signal, the fifth diode D5 is turned on, the node Net2 is a low level signal, and the sixth diode D6 is turned off. At this time, no matter what level the internal synchronization signal Signal_Input2 is, the sixth diode D6 is always in a cut-off state; when the first control signal Singal_Ctrl1 is a high level signal, the first diode D1 is turned off, the node Net1 is pulled up by the first DC source DC1 through the first resistor R1 (first high level signal), the third diode D3 is turned on, and the node Net3 is a high level signal, that is, the first high level signal; when the external synchronization signal Signal_Input1 is a low level signal, the second diode D2 is turned on, the node Net1 is pulled down (low level signal), the third diode D3 is turned off, and the node Net3 is pulled down by the third resistor R3, That is, Singal_Output is a low-level signal. When the external synchronization signal Signal_Input1 is a high-level signal, the second diode D2 is cut off, and the node Net1 is pulled up by the first DC source DC1 through the first resistor R1, that is, the first high-level signal in the embodiment of the present application. The first high-level signal is used to characterize the high-level signal of the external synchronization signal. Since the node Net2 is a high-level signal, the third diode D3 is turned on, and the level at the node Net3 is the voltage of the first DC source DC1 after the voltage is divided by the first resistor R1. Signal_Output is also the voltage of the first DC source DC1 after the voltage is divided by the first resistor R1, that is, the first high-level signal. The first high-level signal and the low-level signal constitute the target synchronization signal, and the pulse width of the target synchronization signal is the same as the pulse width of the external synchronization signal Signal_Input1.

[0112] In the specific implementation, Figure 5 As shown, the synchronization signal selection circuit provided in the embodiment of the present application may further include a matching unit 24;

[0113] The matching unit 24 is used to perform preset processing on the target synchronization signal to obtain a processed synchronization signal, wherein the preset processing includes part or all of the following: impedance matching, de-jittering, filtering, protection, buffering and level conversion.

[0114] In an embodiment of the present application, impedance matching processing is performed on the target synchronization signal, so that the input amplitude of the target signal can be guaranteed with high input impedance, and the driving capability of the synchronization signal can be guaranteed with low output impedance; the target synchronization signal is de-jittered, filtered, protected and buffered, so that the processed synchronization signal can be made more stable; the target synchronization signal is level-converted, so that the target synchronization signal can be output as synchronization signals of different levels to meet different needs.

[0115] In one embodiment, if Figure 5 As shown, the matching unit 24 can be a buffer U1, the input end of the buffer U1 is connected to the output end of the first high level module 21, the output end of the second high level module 22 and the output end of the low level module 23, and the output end of the buffer U1 is used to output the processed synchronization signal.

[0116] In another embodiment, the matching unit 24 may also be a level conversion chip, which may output the target synchronization signal as synchronization signals of different levels.

[0117] The system performance was evaluated by Multisim simulation tool, and relevant parameters were set at the input end to simulate the real second pulse signal, with a signal frequency of 1Hz, a rising edge and a falling edge of 10ns, and a 3.3V power supply. There are two input signals for the second pulse signal, the second pulse signal Signal_Input1 with a duty cycle of 10%, and the second pulse signal Signal_Input2 with a duty cycle of 50%.

[0118] like Figure 6 As shown, when the first control signal Signal_Ctrl1 is a low level signal and the second control signal Signal_Ctrl2 is a high level signal, Figure 6 The pulse width of Signal_Output is the same as that of Signal_Input2, that is, Signal_Input2 output is selected;

[0119] like Figure 7 As shown, when the first control signal Signal_Ctrl1 is a high level signal and the second control signal Signal_Ctrl2 is a low level signal, Figure 7 The pulse width of Signal_Output is the same as that of Signal_Input1, that is, Signal_Input1 output is selected.

[0120] pass Figure 6 and Figure 7 It can be seen that the present application solves the problem of flexible configuration of pulse-per-second signals. The selection of pulse-per-second signals can be realized through a microcontroller unit, and the delay caused by signal processing is very small and is controlled at the order of ns, so the delay can be ignored.

[0121] Based on the same inventive concept, an embodiment of the present application also provides a synchronization signal selection module, including any of the above-mentioned synchronization signal selection circuits.

[0122] Those skilled in the art may make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A synchronization signal selection circuit, characterized in that: include: A control module, a first high level module, a second high level module and a low level module; The control module is connected to the first control end of the first high-level module and the first control end of the second high-level module respectively, the second control end of the first high-level module is used to input an external synchronization signal, and the second control end of the second high-level module is used to input an internal synchronization signal, the output end of the first high-level module is connected to the output end of the second high-level module and the output end of the low-level module, and is used to output a target synchronization signal, and the input end of the low-level module is grounded; The control module is used to send a first control signal to the first high-level module, and send a second control signal to the second high-level module; The first high-level module is used to output a first high-level signal representing a high-level signal of the external synchronization signal, or stop outputting the first high-level signal, under the control of the first control signal and the external synchronization signal; The second high level module is used to output a second high level signal representing a high level signal of the internal synchronization signal, or stop outputting the second high level signal, under the control of the second control signal and the internal synchronization signal; The low-level module is configured to output a low-level signal when the first high-level module stops outputting the first high-level signal or when the second high-level module stops outputting the second high-level signal.

2. The circuit according to claim 1, characterized in that The first high level module is specifically used for: If the first control signal is a high level signal and the external synchronization signal is a high level, outputting the first high level signal; If the first control signal is a high level signal and the external synchronization signal is a low level signal, then stop outputting the first high level signal; If the first control signal is a low level signal, the output of the first high level signal is stopped.

3. The circuit according to claim 1, characterized in that The second high level module is specifically used for: If the second control signal is a high level signal and the internal synchronization signal is a high level, outputting the second high level signal; If the second control signal is a high level signal and the internal synchronization signal is a low level signal, then stop outputting the second high level signal; If the second control signal is at a low level, the output of the second high level signal is stopped.

4. The circuit according to claim 2, characterized in that The first high-level module includes a first DC source and a first conduction unit; The negative electrode of the first DC source is grounded, and the positive electrode of the first DC source is connected to the first conducting unit; The first conduction unit is used to conduct the path between the positive electrode of the first DC source and the output end of the first conduction unit to output the first high-level signal when the first control signal is a high-level signal and the external synchronization signal is a high-level signal, and to disconnect the path between the positive electrode of the first DC source and the output end of the first conduction unit to stop outputting the first high-level signal when the first control signal is a high-level signal and the external synchronization signal is a low-level signal, and to disconnect the path between the positive electrode of the first DC source and the output end of the first conduction unit to stop outputting the first high-level signal when the first control signal is a low-level signal.

5. The circuit according to claim 4, characterized in that The first conduction unit includes a first resistor, a first diode, a second diode and a third diode; The first end of the first resistor is connected to the positive electrode of the first DC source, and the second end of the first resistor is connected to the anode of the first diode, the anode of the second diode, and the anode of the third diode; The cathode of the first diode serves as the first control terminal of the first high level module; The cathode of the second diode serves as the second control terminal of the first high level module; The cathode of the third diode serves as the output end of the first high level module.

6. The circuit according to claim 3, characterized in that The second high level module includes a second DC source and a second conduction unit; The negative electrode of the second DC source is grounded, and the positive electrode of the second DC source is connected to the second conducting unit; The second conduction unit is used to conduct the path between the positive electrode of the second DC source and the output end of the second conduction unit to output the second high-level signal when the second control signal is a high-level signal and the internal synchronization signal is a high-level signal, and to disconnect the path between the positive electrode of the second DC source and the output end of the second conduction unit to stop outputting the second high-level signal when the second control signal is a high-level signal and the internal synchronization signal is a low-level signal, and to disconnect the path between the positive electrode of the second DC source and the output end of the second conduction unit to stop outputting the second high-level signal when the second control signal is a low-level signal.

7. The circuit according to claim 6, characterized in that The second conduction unit includes a second resistor, a fourth diode, a fifth diode and a sixth diode; A first end of the second resistor is connected to the positive electrode of the second DC source, and a second end of the second resistor is connected to the anode of the fourth diode, the anode of the fifth diode, and the anode of the sixth diode; The cathode of the fourth diode serves as the first control terminal of the second high level module; The cathode of the fifth diode serves as the second control terminal of the second high level module; The cathode of the sixth diode serves as the output end of the second high level module.

8. The circuit according to claim 1, characterized in that The low level module includes a third resistor; The first end of the third resistor serves as the output end of the low-level module, and the second end of the third resistor serves as the input end of the low-level module.

9. The circuit according to any one of claims 1 to 8, characterized in that: Also included is a matching unit; The matching unit is used to perform preset processing on the target synchronization signal to obtain a processed synchronization signal, wherein the preset processing includes part or all of the following: Impedance matching, debouncing, filtering, protection, buffering and level conversion.

10. A synchronization signal selection module, characterized in that: It comprises the synchronization signal selection circuit as claimed in any one of claims 1 to 9.

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