Improved layout techniques and optimization for power transistors

Abstract

Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. The transistors may include drain metal portions elevated from the surface of a substrate, drain metal with a notched region, a gate manifold body with an angled gate tab extending from the gate manifold, and / or a source connection shield. The transistors may include high electron mobility transistors (HEMTs), gallium nitride (GaN) on silicon transistors, GaN on silicon carbide transistors, or other types of transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 16 / 874,098, filed May 14, 2020, which is hereby incorporated by reference in its entirety. Background Art

[0003] The multi-finger planar field-effect transistor (FET) layout consists of interdigitated contacts for the gate, drain, and source metals. Parasitic output capacitance forms between the drain contact and the substrate, and between the drain contact and the backside ground plane of the die. These parasitic output capacitances can adversely affect the device's radio frequency (RF) performance, for example, by reducing device efficiency. Summary of the Invention

[0004] Various embodiments are disclosed for improved and structurally optimized transistors, such as GaN-on-silicon power transistors and others to be described.

[0005] In a first aspect, a field effect transistor includes a drain metal portion elevated from a surface of a substrate. The field effect transistor includes a substrate, a first source metal, a second source metal, and a drain metal positioned between the first source metal and the second source metal. The drain metal includes a first drain metal forming a first drain metal pillar and a second drain metal pillar, and the field effect transistor includes the second drain metal. The first drain metal pillar is positioned below the second drain metal on a first distal end of the second drain metal, and the second drain metal pillar is positioned below the second drain metal on a second distal end of the second drain metal, such that the second drain metal is elevated from the substrate. A hole is defined between the first drain metal pillar and the second drain metal pillar and below the second drain metal.

[0006] The field effect transistor may further include a first source metal and a source-connected field plate (SFP), a second source metal and a source-connected field plate (SFP), a first gate finger, and a second gate finger. The first source metal and the SFP, and the second source metal and the SFP are each sized and positioned to include an overhang defining an overhang hole, wherein the gate finger is positioned in the overhang hole.

[0007] In a second aspect, a field-effect transistor includes a drain metal having a notch region. The field-effect transistor includes a first source metal, a second source metal, and a drain metal positioned between the first and second source metals. The drain metal includes a drain metal body having a notch region defining a first protrusion and a second protrusion of the drain metal body. The first and second protrusions of the drain metal body are positioned on respective sides of the notch region. In various examples, the notch region is a triangular or U-shaped notch region.

[0008] In a third aspect, a field-effect transistor includes a gate manifold body having an angled gate tab extending from the gate manifold. The field-effect transistor includes source metal, a gate manifold including the gate manifold body, a first angled gate tab, and a second angled gate tab; and drain metal including a first drain metal contact and a second drain metal contact. The first angled gate tab extends from the gate manifold body at a first angle, and the second angled gate tab extends from the gate manifold body at a second angle.

[0009] The first angled gate tab includes a first region and a second region, the first region contacting and extending from a first corner of the gate manifold body; the second region extends from the first region of the first angled gate tab; and the second angled gate tab includes a first region and a second region, the first region contacting and extending from the second corner of the gate manifold body; and the second region extends from the first region of the second angled gate tab. The first angled gate tab and the second angled gate tab are sized and positioned such that the respective contact regions are positioned wider than the drain metal.

[0010] In some embodiments, the second region of the first angled gate tab is positioned parallel to and offset from the first side of the gate manifold body, and the second region of the second angled gate tab is positioned parallel to and offset from the second side of the gate manifold body.

[0011] In a fourth aspect, a field-effect transistor with a source connection shield is described. The field-effect transistor includes a gate manifold, a first source metal, a second source metal, a drain metal, and a shield, wherein the drain metal is positioned between the first source metal and the second source metal; the shield has a first end connected to the first source metal and a second end connected to the second source metal, and is positioned between the gate manifold and the drain contact. The shield can have a width of approximately 10 μm to approximately 15 μm, but the embodiments described herein are not limited to these dimensions.

[0012] In some embodiments, the shield may include a first step region, a second step region, and a recessed region positioned between the first step region and the second step region. The recessed region may be in direct contact with the substrate. The first step region and the second step region may be elevated from the surface of the substrate.

[0013] The gate manifold may include a gate manifold body, a first angled gate tab, and a second angled gate tab. The first angled gate tab may be positioned in a recess defined by a first stepped region of the shield such that the shield does not contact the first angled gate tab. The second angled gate tab may be positioned in a recess defined by a second stepped region of the shield such that the shield does not contact the second angled gate tab.

[0014] The additional transistors may include various combinations of the first, second, third, fourth, and / or additional aspects described herein. Furthermore, the field-effect transistors may include high electron mobility transistors (HEMTs). Furthermore, the field-effect transistors may include transistors based on various typical microwave semiconductor materials, including but not limited to gallium arsenide (GaAs) and gallium nitride (GaN). BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Many aspects of the present disclosure may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on clearly illustrating the principles of the present disclosure. Additionally, in the drawings, like reference numerals indicate corresponding parts throughout the several views.

[0016] Figure 1 It is a three-dimensional diagram of a field effect transistor in the prior art.

[0017] Figure 2 and Figure 3 is a perspective view of a field effect transistor according to various embodiments of the present disclosure.

[0018] Figure 4 is a circuit diagram illustrating parasitic capacitance occurring in a field effect transistor according to various embodiments of the present disclosure.

[0019] Figure 5 is a side view of a field effect transistor relative to a top-down view of the field effect transistor according to various embodiments of the present disclosure.

[0020] Figure 6 is another side view of a field effect transistor relative to the top view of the field effect transistor according to various embodiments of the present disclosure.

[0021] Figure 7 is a bird's-eye view of a field effect transistor according to various embodiments of the present disclosure.

[0022] Figure 8 This is an overhead view of a field effect transistor in the prior art.

[0023] Figures 9 to 12 is a bird's-eye view of a field effect transistor according to various embodiments of the present disclosure.

[0024] Figure 13 are diagrams illustrating various combinations of components of a field effect transistor according to various embodiments of the present disclosure.

[0025] Figure 14 and Figure 15 is a graph showing electromagnetic (EM) simulation results of a field effect transistor according to various embodiments of the present disclosure.

[0026] Figure 16 is an example of a die layout of transistors having multiple fingers of field effect transistors positioned in parallel according to various embodiments of the present disclosure.

[0027] Figures 17 to 20 is a graph showing measurement results of a field effect transistor according to various embodiments of the present disclosure.

[0028] Figure 21 A die with transistors comprising multiple fingers of a conventional field effect transistor is shown.

[0029] Figure 22 A die having transistors including multiple fingers of a field effect transistor as described in accordance with various embodiments of the present disclosure is shown.

[0030] Figure 23 is an enlarged bird's-eye view of a field effect transistor according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] The present disclosure relates to layout techniques and optimizations for semiconductor devices. The concepts described herein are applicable to various types of field effect transistors and other semiconductor devices formed using a variety of different semiconductor processes and technologies. In some non-limiting examples, the layout techniques and optimizations are applied to gallium nitride (GaN) high electron mobility transistors (HEMTs), gallium arsenide (GaAs) pseudomorphic high electron mobility transistors (pHEMTs), metamorphic high electron mobility transistors (mHEMTs), and / or GaN-on-silicon power amplifier transistors. Although the various embodiments described herein are described with respect to GaN-on-silicon power transistors, it should be understood that, as will become apparent, the principles and embodiments described herein can be applied to other types of transistors.

[0032] As mentioned above, parasitic output capacitance can form between the drain contact and the substrate, as well as between the drain contact and the backside ground plane of the die. These parasitic capacitances can have an adverse effect on the overall RF performance of the device, for example, reducing device gain, power, and efficiency. Therefore, it is beneficial to increase the RF gain of GaN-on-silicon transistors or other similar transistors without changing the fundamental physics of how the transistors operate. For example, it is possible to change how the transistors connect to other devices without changing the intrinsic layout design of the transistors or the properties of the semiconductor materials. These connections are often referred to as embedded networks or metallization.

[0033] There are three main connections to the FET: the gate contact, the drain contact, and the source contact. Metallization is provided to electrically couple the connections of one finger to the other fingers across multiple FET channels. Without changing the actual structure of the FET, changes in metallization can be relied upon to improve many different performance characteristics of the FET.

[0034] Various embodiments of improved and structurally optimized transistors (such as GaN power transistors) for use on any suitable substrate, as well as other devices to be described, are disclosed. In a first aspect, a field effect transistor includes a drain metal portion elevated from a surface of a substrate. The field effect transistor includes a substrate, a first source metal, a second source metal, and a drain metal positioned between the first source metal and the second source metal. The drain metal includes a first drain metal forming a first drain metal pillar and a second drain metal pillar, and the field effect transistor includes the second drain metal. The first drain metal pillar is positioned below the second drain metal on a first distal end of the second drain metal, and the second drain metal pillar is positioned below the second drain metal on a second distal end of the second drain metal, such that the second drain metal is elevated from the substrate. A hole is defined between the first drain metal pillar and the second drain metal pillar and below the second drain metal.

[0035] The field effect transistor may further include a first source metal and a source connection field plate (SFP), a second source metal and the SFP, a first gate finger, and a second gate finger. The first source metal and the SFP and the second source metal and the SFP are each sized and positioned to include an overhang defining an overhang hole, in which the gate finger is positioned.

[0036] In a second aspect, a field-effect transistor includes a drain metal having a notch region. The field-effect transistor includes a first source metal, a second source metal, and a drain metal positioned between the first and second source metals. The drain metal includes a drain metal body having a notch region defining a first protrusion and a second protrusion of the drain metal body. The first and second protrusions of the drain metal body are positioned on respective sides of the notch region. In various examples, the notch region is a triangular or U-shaped notch region.

[0037] In a third aspect, a field effect transistor includes a gate manifold body having an angled gate tab extending from the gate manifold. The field effect transistor includes: a source metal, a gate manifold, and a drain metal; the gate manifold includes the gate manifold body, a first angled gate tab, and a second angled gate tab; and the drain metal includes a first drain metal contact and a second drain metal contact.

[0038] The first angled gate tab includes a first region that contacts and extends from a first corner of the gate manifold body, and a second region that extends from the first region of the first angled gate tab. The second angled gate tab includes a first region that contacts and extends from a second corner of the gate manifold body, and a second region that extends from the first region of the second angled gate tab. The first and second angled gate tabs are sized and positioned such that the respective contact regions are positioned wider than the drain metal.

[0039] In some embodiments, the second region of the first angled gate tab is positioned parallel to and offset from the first side of the gate manifold body, and the second region of the second angled gate tab is positioned parallel to and offset from the second side of the gate manifold body.

[0040] In a fourth aspect, a field-effect transistor includes a source connection shield. The field-effect transistor includes a gate manifold, a first source metal, and a second source metal. The transistor also includes a drain metal and a shield positioned between the first source metal and the second source metal. The shield has a first end connected to the first source metal and a second end connected to the second source metal, and is positioned between the gate manifold and the drain contact. The shield may have a width of approximately 10 μm to approximately 15 μm.

[0041] In some embodiments, the shield may include a first step region, a second step region, and a recessed region positioned between the first step region and the second step region. The recessed region may be in direct contact with the substrate. The first step region and the second step region may be elevated from the surface of the substrate.

[0042] The gate manifold may include a gate manifold body, a first angled gate tab, and a second angled gate tab. The first angled gate tab may be positioned in a recess defined by a first stepped region of the shield such that the shield does not contact the first angled gate tab. The second angled gate tab may be positioned in a recess defined by a second stepped region of the shield such that the shield does not contact the second angled gate tab.

[0043] Additional transistors may include various combinations of the first aspect, the second aspect, the third aspect, the fourth aspect, and / or additional aspects described herein. Furthermore, the field effect transistors described herein may be embodied as high electron mobility transistors (HEMTs). Furthermore, the field effect transistors described herein may be embodied as gallium nitride (GaN) transistors on silicon, GaN transistors on silicon carbide, or GaN transistors formed on other suitable types of substrates.

[0044] Now go to Figure 1 , which shows a perspective view of the field effect transistor 10. Figure 1 Field effect transistor 10 is provided in FIG as a reference to a more conventional structure to highlight the differences compared to the structural features described below. Figure 1 , the features of field effect transistor 10 are not necessarily drawn to scale. Field effect transistor 10 may vary in size, shape, proportions, and other aspects compared to what is shown while still adhering to and incorporating the benefits of the concepts described herein. Field effect transistor 10 may include Figure 1 Other structural features may not be shown, or in some cases, one or more of the structural features shown may be omitted.

[0045] In one example, field effect transistor 10 can be embodied as, for example, a GaN-on-silicon power transistor, although it can be formed on other suitable substrates. As shown, field effect transistor 10 includes source metal 15, drain metal 25, and gate manifold 30 (also referred to as a gate). In some examples, source metal 15 includes a first source metal 15a and a second source metal 15b disposed at different locations on substrate 5.

[0046] Field effect transistor 10 may be embodied as a multi-finger planar field effect transistor. The layout of the multi-finger planar field effect transistor consists of interdigitated contacts for the gate manifold 30, drain metal 25, and source metal 15. Conventional transistor layouts use a manifold structure to connect all gate contacts on one side of the die, and a similar manifold structure to connect all drain contacts on the opposite side of the die. The proximity of the gate manifold to the drain contact metal results in parasitic capacitance, which is referred to as gate-drain capacitance (C GD), which reduces the available and stable gain of the semiconductor device.

[0047] Next, let’s refer to Figure 2 and Figure 3 , shows a perspective view of a non-limiting example of a field effect transistor 100 according to various embodiments described herein. Field effect transistor 100 includes a substrate 105, a source metal 115, a drain metal 125, and a gate manifold 130 or gate. In some examples, source metal 115 includes a first source metal 115a and a second source metal 115b, wherein drain metal 125 is positioned between first source metal 115a and second source metal 115b. First source metal 115a and second source metal 115b can be positioned on different sides of drain metal 125. In some embodiments, gate manifold 130 is formed of a first metal, and first source metal 115a, second source metal 115b, and drain metal 125 are formed of a second metal.

[0048] like Figure 2 and Figure 3 As shown, drain metal 125 includes a drain metal body having a notch region 135, which defines a first protrusion 140 and a second protrusion 145 of the drain metal body. As can be appreciated, notch region 135 can include an absence of drain metal 125. First protrusion 140 and second protrusion 145 are positioned on respective sides of notch region 135. In various embodiments, notch region 135 is a triangular notch region. However, in alternative embodiments, notch region 135 is a U-shaped notch region or other suitable shape.

[0049] It has been observed that most of the current in the drain metal 125 flows toward the drain manifold (e.g., in a direction D1 opposite to the gate manifold 130), and therefore the portion of the drain metal 125 on the opposite side of the drain manifold does not contribute to the flow of current. Therefore, when the drain metal 125 does not include a notch, insignificant current flows in the area of the notch region 135 of the drain metal 125. Therefore, removing the portion of the drain metal 125 in the notch region 135 has a negligible effect on the overall performance of the drain metal 125, but significantly reduces the area of the drain metal 125, and therefore reduces the capacitance C. DS .

[0050] also, Figure 2 and Figure 3 The gate manifold 130 is shown with Figure 1 The structure of the gate manifold 30 is different from the structure of the gate manifold 30. More specifically, in one or more embodiments, Figure 2The gate manifold 130 may include a gate manifold body 150, a first angled gate tab 155, and a second angled gate tab 160. Because the drain metal 125 includes at least a first drain metal contact (not shown) and a second drain metal contact (not shown), the first angled gate tab 155 extends from the gate manifold body 150 at a first angle. Similarly, the second angled gate tab 160 extends from the gate manifold body at a second angle. In some embodiments, the gate manifold body 150 is square or rectangular.

[0051] The first angled gate tab 155 may include a first rectangular region in contact with and extending from a first corner of the gate manifold body 150 and a second rectangular region extending from the first rectangular region. The second rectangular region is positioned parallel to and offset from a first side of the gate manifold body 150. Similarly, the second angled gate tab 160 may include a first rectangular region in contact with and extending from a second corner of the gate manifold body 150 that is opposite the first corner. The second angled gate tab 160 may also include a second rectangular region extending from the first rectangular region, wherein the second rectangular region is positioned parallel to and offset from a second side of the gate manifold body 150.

[0052] Furthermore, in one or more embodiments, the field effect transistor 100 can include a shield 170. In some embodiments, the shield 170 can be positioned between the gate manifold 130 and the drain contact, or in other words, between the gate manifold 130 and the drain metal 125. For example, the shield 170 can have (or be sized and positioned so as to) be long enough to contact the first source metal 115a and the second source metal 115b without contacting the drain metal 125. Therefore, in some examples, the shield 170 can be referred to as a source connection shield 170.

[0053] Additionally, in some embodiments, the shield 170 is positioned between the gate manifold 130 and the gate fingers 190a, 190b ( Figure 3), and thus, the shield 170 does not touch or make contact with the gate manifold 130 (or more specifically, the first angled gate tab 155 and the second angled gate tab 160 of the gate manifold 130) or the gate fingers 190. Thus, in some embodiments, the shield 170 includes a first step region 175, a second step region 180, and a recessed region 185 positioned between the first step region 175 and the second step region 180. For example, the first angled gate tab 155 can be positioned in a recess defined by the first step region 175 of the shield 170, and similarly, the second angled gate tab 160 can be positioned in a recess defined by the second step region 180 of the shield 170. The recessed region 185 can directly touch or be in direct contact with the substrate 105, while the first step region 175 and the second step region 180 are elevated from the surface of the substrate 105.

[0054] In some embodiments, the recessed region 185 can include a length that is the same as or similar to the length of the drain metal 125, wherein the recessed region 185 of the shield 170 is positioned directly between the drain metal 125 and the gate manifold 130. In one example, the width of the shield 170 is about 10 μm to about 15 μm (±2 μm), although any suitable dimensions can be used to reduce parasitic capacitance.

[0055] In various embodiments, Figure 2 The field effect transistor 100 may include a HEMT. Therefore, Figure 2 Field effect transistor 100 may include a GaN HEMT, a GaAs pHEMT, an mHEMT, or other types of transistors. In some embodiments, field effect transistor 100 may be incorporated into a power amplifier (such as a GaN power amplifier), but field effect transistor 100 may be used as a device component in other circuit designs and for other purposes.

[0056] Figure 2 and Figure 3 The solution shown significantly reduces parasitic capacitance by introducing a source connection shield 170 between the gate manifold 130 and the drain contact. The embodiments described herein result in electrical, thermal, and reliability improvements through layout changes without imposing material costs. The shield 170 can be implemented in any standard semiconductor process that provides multiple interconnect metal layers with low-capacitance crossover capability. The solution can be implemented through simple process-independent layout modifications, allowing it to be implemented in a variety of technologies and semiconductor processes.

[0057] Next reference Figure 4, a circuit diagram 200 is shown which illustrates various parasitic capacitances that occur in the field effect transistor 10. More specifically, the capacitances may include parasitic capacitances that are undesirable in many applications. For example, the intrinsic transistor 205 is shown as having three internal parasitic capacitances Cgs_int, Cds_int, and Cgd_int, where Cgs_int is an internal capacitance occurring between the gate and the source, Cds_int is an internal capacitance occurring between the drain and the source, and Cgd_int is an internal capacitance occurring between the gate and the drain. External to the intrinsic transistor 205, additional parasitic capacitances such as Cgs_ext, Cgd_ext, and Cds_ext are generated, where Cgs_ext is an external capacitance occurring between the gate and the source, Cds_ext is an external capacitance occurring between the drain and the source, and Cgd_ext is an external capacitance occurring between the gate and the drain. By reducing Figure 4 The parasitic capacitance shown in Figure 3 can improve the device efficiency of GaN power amplifiers or other similar devices.

[0058] Go to Figure 5 , shows a side view of the field effect transistor 100 relative to a top view of the field effect transistor 100 according to various embodiments of the present disclosure. It is worth noting that Figure 5 An embodiment is depicted in which drain metal 125 and source metal 115 are elevated from the ohmic contact and / or the surface of substrate 105 to reduce parasitic capacitance. Field effect transistor 100 includes a first drain metal 125a of a first metallic material and a second drain metal 125b of a second metallic material, which may be different from the first metallic material.

[0059] Field effect transistor 100 also includes a first source metal 115a and a second source metal 115b, which can be made of the same metal material. Below the first source metal 115a, the first source metal and a source connection field plate (SFP) 210a can be positioned above a first ohmic contact 215a. Similarly, below the second source metal 115b, the second source metal and the SFP 210b can be positioned above a second ohmic contact 215b. As can be appreciated, the first ohmic contact 215a and the second ohmic contact 215b can comprise source ohmic contacts.

[0060] In addition, a third ohmic contact 215c is positioned below a first distal end of the first drain metal 125a, and a fourth ohmic contact 215d is positioned below a second distal end (opposite to the first distal end) of the first drain metal 125a, thereby defining a hole between the third ohmic contact 215c and the fourth ohmic contact 215d. The hole is also positioned below the first drain metal 125a and the second drain metal 125b. As can be appreciated, the third ohmic contact 215c and the fourth ohmic contact 215d can include drain ohmic contacts.

[0061] In conventional field effect transistors 10, as will be appreciated, the ohmic contact spans the entire width of the drain metal 125. However, as Figure 5 As shown, the widths of the first ohmic contact 215a and the second ohmic contact 215b are smaller than the bottom widths of the first source metal and SFP 210a and the second source metal and SFP 210b, respectively. For example, by raising the source metal and SFP 210 and the drain metal 125 from the substrate 105 and / or the ohmic contacts 215, parasitic capacitance in the field effect transistor 100 is reduced.

[0062] Now refer to Figure 6 , shows another side view of the field effect transistor 100 relative to the top view of the field effect transistor 100 according to various embodiments of the present disclosure. Specifically, Figure 6 An embodiment is depicted in which the drain metal 125 and the source metal 115 are elevated from the surface of the ohmic contact and / or substrate 105 to reduce parasitic capacitance. Figure 5 Compared to the field effect transistor 100, the first drain metal 125a is divided into a first drain metal pillar 220a and a second drain metal pillar 220b, wherein a hole 225 is defined between the first drain metal pillar 220a and the second drain metal pillar 220b. The field effect transistor 100 includes the first drain metal 125a of a first metal material and the second drain metal 125b of a second metal material, wherein, in some embodiments, the second metal material may be different from the first metal material.

[0063] Similar to Figure 5 , Figure 6 Field effect transistor 100 also includes a first source metal 115a and a second source metal 115b, which may be made of the same metal material. Below first source metal 115a, the first source metal and SFP 210a may be positioned above first ohmic contact 215a. Similarly, below second source metal 115b, the second source metal and SFP 210b may be positioned above second ohmic contact 215b.

[0064] In addition, a third ohmic contact 215c is positioned below a first distal end of the first drain metal 125a, and a fourth ohmic contact 215d is positioned below a second distal end (opposite to the first distal end) of the first drain metal 125a, thereby defining a hole between the third ohmic contact 215c and the fourth ohmic contact 215d. The hole is also positioned below the first drain metal 125a and the second drain metal 125b. In conventional field effect transistors 10, as will be appreciated, the ohmic contacts span the entire width of the drain metal 125.

[0065] Notably, the widths of the first ohmic contact 215a and the second ohmic contact 215b are smaller than the bottom widths of the first source metal and SFP 210a and the second source metal and SFP 210b, respectively. In some embodiments, the third ohmic contact 215a has a width that is the same as or substantially similar to the width of the first source metal pillar 215c. For example, by raising the source metal and SFP 210 and the drain metal 125 from the substrate 105 and / or the ohmic contacts 215, parasitic capacitance in the field effect transistor 100 is reduced.

[0066] Common Reference Figure 5 and Figure 6 The source metal and SFP 210 are sized and positioned to include overhangs 230a, 230b, respectively. Each overhang 230 defines an overhang hole 235a, 235b, in which the gate fingers 190a, 190b are positioned, respectively, so that the source metal and SFP 210 do not contact the gate fingers 190a, 190b while not interfering with the normal operation of the gate fingers 190a, 190b.

[0067] Advance reference Figure 23 , for example, shows a magnified top view of field-effect transistor 100. Looking at the magnified labeled area 23, gate manifold 130 is shown as not contacting source metal 115b. More specifically, a noticeable gap can be observed between gate finger 190b and source metal 115b. Additionally, SFP 210b may overlap gate manifold 130; however, SFP 210b does not contact or connect to gate manifold 130.

[0068] Now refer to Figure 7 , shows a bird's-eye view of a field effect transistor 100 according to various embodiments of the present disclosure. For example, Figure 7 A top view of a semiconductor die with GaN or similar type transistors is shown. For example, Figure 7 Multiple cells as shown in FIG can be stacked on top of one another to form a larger field effect transistor 100. Parasitic capacitance occurs in two areas of note. The drain contact is traditionally coupled to the backside ground plane of the semiconductor, which creates a parasitic drain-source capacitance C DS Another notable capacitance occurs between the gate manifold 130 on the left side of the diagram and the drain metal 125 on the right side. The proximity of these metals creates a parasitic capacitance, called C GD .

[0069] exist Figure 7 In FIG. 1 , a conventional type of gate manifold 130 is shown with a gate contact region 240. In addition, source connections 245a, 245b of the field effect transistor 100 are shown. The parasitic output capacitance (CDS ) is formed between the drain contacts (e.g., ohmic contact 215c and fourth ohmic contact 215d) and the substrate 105 and / or backside ground plane of the die. This output capacitance has an adverse effect on the overall device RF performance, i.e., reduces the efficiency and bandwidth of the device. By raising the drain metal 125 from the substrate 105, the magnitude of the parasitic capacitance is minimized by reducing the proximity of the drain metallization to the substrate 105 and the backside ground plane. This embodiment can be implemented with very simple process-independent layout modifications, allowing the solution to be implemented in a variety of technologies and semiconductor processes. Although the above embodiment is shown in which the drain metal 125 is raised from the substrate 105, the shield 170 and the notched region 135 of the drain metal 125 are not included in the Figure 7 In the embodiment of .

[0070] Go to Figure 8 , shows a top view of a conventional field effect transistor 10 in the prior art. It is noteworthy that the ohmic contacts 215a, 215b and 215c respectively span the entire first source metal 115a, the second source metal 115b and the drain metal 125, thereby generating large parasitic capacitance that affects the efficiency of the semiconductor device.

[0071] Now go to Figure 9 , shows an overhead view of a field effect transistor 100 according to various embodiments of the present disclosure. Specifically, Figure 9 An embodiment of the field effect transistor 100 includes a drain metal 125 elevated from the substrate 105, such as Figure 5 or Figure 6 In addition, Figure 9 The embodiment of the field effect transistor 100 shows a notch region 135 provided in the drain metal 125. A conventional type of gate manifold 130 is shown, and Figure 9 The examples do not include reference Figure 2 and Figure 3 Shield 170 is depicted.

[0072] Go to Figure 10 and Figure 11 , which shows a bird's-eye view of a field effect transistor 100 according to various embodiments of the present disclosure. Figure 10 and Figure 11 An embodiment of the field effect transistor 100 includes a drain metal 125 elevated from the substrate 105, such as Figure 5 or Figure 6 In addition, Figure 10 and Figure 11The embodiment of the field effect transistor 100 of FIG. 1 shows a shield 170 disposed therein. The shield 170 is shown positioned between the gate manifold 130 and the drain contact, or in other words, between the gate manifold 130 and the drain metal 125. The shield 170 can have (or be sized and positioned to) be long enough to contact the first source metal 115a and the second source metal 115b without contacting the drain metal 125. Therefore, in some examples, the shield 170 can be referred to as a source connection shield 170. A conventional type of gate manifold 130 is shown in the field effect transistor 100, and Figure 10 and Figure 11 The examples do not include reference Figure 2 and Figure 3 The notched region 135 is depicted.

[0073] The shield 170 may pass over the connection of the gate manifold 130 to the gate fingers 190a, 190b, and thus, the shield 170 does not touch or come into contact with the gate manifold 130 or the gate fingers 190. However, the gate manifold 130 may form a connection with the gate fingers 190. Specifically, Figure 10 In the embodiment of FIG. 1 , the width W of the shield 170 is about 10 μm, while in FIG. Figure 11 In the embodiment of FIG. 5 , the width W of the shield 170 is approximately 15 μm, but other suitable widths may be employed. However, it has been observed that 10 μm to 15 μm is a desirable range for the width of the shield 170 .

[0074] Now refer to Figure 12 , shows an overhead view of a field effect transistor 100 according to various embodiments of the present disclosure. Specifically, Figure 12 An embodiment of the field effect transistor 100 includes a drain metal 125 elevated from the substrate 105, such as Figure 5 or Figure 6 In addition, Figure 12 An embodiment of a field effect transistor 100 is shown having Figures 8 to 11 The structure of the gate manifold 130 is different from the structure of the gate manifold 130.

[0075] More specifically, in one or more embodiments, the gate manifold 130 includes a gate manifold body 150, a first angled gate tab 155, and a second angled gate tab 160. When the drain metal 125 is positioned on the third ohmic contact 215c (e.g., the first drain metal contact) and the fourth ohmic contact (e.g., the second drain metal contact), the first angled gate tab 155 extends from the gate manifold body 150 at a first angle and can contact the first drain metal contact. Similarly, the second angled gate tab 160 extends from the gate manifold body 150 at a second angle and contacts the second drain metal contact. In some embodiments, the gate manifold body 150 is square or rectangular.

[0076] The first angled gate tab 155 may include a first rectangular region 250 in contact with and extending from a first corner of the gate manifold body 150 and a second rectangular region 255 extending from the first rectangular region 250. The second rectangular region 255 is positioned parallel to and offset from the gate manifold body 150. Similarly, the second angled gate tab 160 may include a first rectangular region 260 in contact with and extending from a second corner of the gate manifold body 150, opposite the first corner. The second angled gate tab 160 may also include a second rectangular region 265 extending from the first rectangular region, wherein the second rectangular region is positioned parallel to and offset from the gate manifold body 150.

[0077] In some embodiments, the first angled gate tab 155 includes a contact area 270 that can be square or rectangular in shape. Similarly, in some embodiments, the second angled gate tab 160 includes a contact area 275 that can be square or rectangular in shape. The first angled gate tab 155 and the second angled gate tab 160 are sized and positioned such that the contact areas 270, 275 are positioned wider than the drain metal 125.

[0078] Figure 13 1 is a diagram illustrating various combinations of components of field effect transistor 100 according to various embodiments of the present disclosure. For example, various combinations of: (a) drain metal 125 and / or source metal 115 elevated from substrate 105; (b) gate manifold 130 with angled gate tabs 155, 160; (c) drain metal 125 with notched region 135; and / or (d) shield 170 positioned between gate manifold 130 and drain and source metals are illustrated. It should be understood that the present disclosure is intended to disclose all combinations of these embodiments.

[0079] Figure 14 and Figure 15is a graph showing electromagnetic (EM) simulation results for various combinations of embodiments of the field effect transistor 100 described herein according to the present disclosure. Specifically, Figure 14 Shows S 12 Scattering parameter (S 12 [db]), and Figure 15 shows the ground drain capacitance C measured in pF / mm GD Mark m1 and mark m3 show values at 5 GHz.

[0080] from Figure 14 and Figure 15 It can be observed that all modifications reduce S 12 / C GD . Notably, the angled gate tabs 155, 160 are approximately twice as effective as the notched region 135 of the drain metal 125. The shield 170 is approximately four times as effective as the notched region 135 of the drain metal 125. The difference between a shield 170 having a width of 10 μm and a shield 170 having a width of 15 μm is negligible. However, the combination of the shield 170, the notched region 135 of the drain metal 125, and the angled gate tabs 155, 160 produces the best results.

[0081] Figure 16 is an example of a die layout of a single transistor including multiple "fingers" of field effect transistors 100a, 100b according to various embodiments of the present disclosure. More specifically, an example of 28V conversion for a standard 0.22mm driver die is shown.

[0082] Figures 17-20 is a graph showing measurement results of the field effect transistor 100 according to various embodiments of the present disclosure. Specifically, Figure 17 is the amplitude relative to the frequency S 12 Improved the graph by approximately 1.5dB. Figure 18 Including parasitic capacitance C shown in pF GD Graph with respect to frequency reduction of approximately twenty percent. Figure 19 Including parasitic capacitance C shown in pF DS Graph with respect to frequency reduction of approximately eight percent. Figure 20 Included shows the maximum gain (G max ) with respect to a graph showing an increase of approximately 1 dB with respect to frequency.

[0083] Figure 21 A die comprising a transistor having multiple fingers of a conventional field effect transistor 10 is shown, while Figure 22FIG. 1 shows a die having a transistor with multiple fingers of a field effect transistor 100 according to various embodiments of the present disclosure. Figure 21 When compared to a bare die of a conventional field effect transistor 10 , the drain metal 125 elevated from the substrate 105 can be observed, as well as the notched region 135 , the angled gate tabs 155 , 160 , and the shield 170 .

[0084] Although some of the embodiments described herein are described with reference to GaN-on-silicon transistors, it should be understood that the embodiments described herein may also be applied to GaN-on-silicon carbide (GaN-on-SiC) transistors as well as other types of transistors. In any case, the techniques and optimizations for GaN-on-power transistor design described in various embodiments of the present disclosure will improve basic device performance. For example, the raised and notched drain metallization will reduce C DS , thereby improving efficiency and bandwidth. The use of a field plate around the source will reduce C GS , thereby improving gain and bandwidth. The use of shield 170 and angled gate tabs 155, 160 will provide a shielded gate manifold to reduce CGD, thereby providing stable gain and stability for the semiconductor device. Modifying the gate-drain spacing to optimize R D , thereby providing improvements in gain, power, and efficiency.

[0085] The above features, structures or characteristics can be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in various embodiments are interchangeable. In the following description, many specific details are provided in order to fully understand the embodiments of the present disclosure. However, it will be understood by those skilled in the art that the technical solutions of the present disclosure can be practiced without one or more specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0086] Although relative terms such as "upper," "lower," "upper," and "lower" are used in this specification to describe the relative relationship of one component to another, these terms are used for convenience only, for example, as a reference to directions in the examples shown in the drawings. It should be understood that if the device is inverted, the "upper" component described above will become a "lower" component. When one structure is "on" another structure, the structure can be integrally formed on the other structure, or the structure can be "directly" disposed on the other structure, or the structure can be "indirectly" disposed on the other structure through another structure.

[0087] In this specification, terms such as "a," "an," "the," and "said" are used to indicate the presence of one or more elements and components. Unless otherwise indicated in the appended claims, the terms "include," "comprising," "having," "containing," and their variations are used to be open-ended and mean that additional elements, components, etc. are included in addition to the listed elements, components, etc. The terms "first," "second," etc. are used merely as labels and do not limit the quantity of the objects.

[0088] The above-described embodiments of the present disclosure are merely possible examples of implementations set forth for a clear understanding of the principles of the present disclosure. Numerous variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the present disclosure. All such modifications and variations are intended to be included within the scope of the present disclosure and to be protected by the following claims.

Claims

1. A field effect transistor comprising: a first source metal; a second source metal; a gate manifold comprising a gate manifold body, a first angled gate tab, and a second angled gate tab; as well as A drain metal positioned above the drain ohmic contacts and between the first source metal and the second source metal, wherein the drain metal comprises a drain metal body having a notch region positioned between the drain ohmic contacts and between the first source metal and the second source metal, the notch region defining a first protrusion and a second protrusion of the drain metal body, the first protrusion and the second protrusion being positioned on respective sides of the notch region.

2. The field effect transistor according to claim 1, wherein The notch area is a triangular notch area.

3. The field effect transistor according to claim 1, wherein The notch area is a U-shaped notch area.

4. The field effect transistor according to claim 1, wherein: The drain metal includes a first drain metal column and a second drain metal column; The field effect transistor includes a second drain metal; The first drain metal pillar and the second drain metal pillar are positioned below the second drain metal, on a first distal end and a second distal end of the second drain metal, respectively; and A hole is defined below the second drain metal and between the first drain metal pillar and the second drain metal pillar.

5. The field effect transistor according to claim 1 , further comprising: A first source metal and source connection field plate (SFP), a second source metal and source connection field plate (SFP), a first gate finger, and a second gate finger. The field effect transistor according to claim 1 , wherein: The field effect transistor is a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), or a metamorphic high electron mobility transistor (mHEMT).

7. A field effect transistor comprising: a first source metal; a second source metal; a gate manifold comprising a gate manifold body, a first angled gate tab extending to a first gate contact region at an end of the first source metal, and a second angled gate tab extending to a second gate contact region at an end of the second source metal; as well as a drain metal comprising a first drain ohmic contact and a second drain ohmic contact, the first drain ohmic contact and the second drain ohmic contact being positioned below the drain metal with a hole between the first drain ohmic contact and the second drain ohmic contact below the drain metal; The first angled gate tab extends from the gate manifold body at a first angle, and the second angled gate tab extends from the gate manifold body at a second angle.

8. The field effect transistor according to claim 7, wherein: the first angled gate tab including a first region contacting and extending from a first corner of the gate manifold body and a second region extending from the first region of the first angled gate tab to the first gate contact region; the second angled gate tab includes a first region contacting and extending from a second corner of the gate manifold body and a second region extending from the first region of the second angled gate tab to the second gate contact region; and The first and second angled gate tabs are sized and positioned such that the first and second gate contact regions are positioned wider than an end of the drain metal between the ends of the first and second source metals.

9. The field effect transistor according to claim 8, wherein: a second region of the first angled gate tab is positioned parallel to and offset from the first side of the gate manifold body; and A second region of the second angled gate tab is positioned parallel to and offset from a second side of the gate manifold body.

10. The field effect transistor according to claim 7, wherein: The field effect transistor includes a substrate; The drain metal includes a first drain metal column and a second drain metal column; The field effect transistor includes a second drain metal; and The first drain metal pillar and the second drain metal pillar are positioned below the second drain metal, on a first distal end and a second distal end of the second drain metal, respectively.

11. The field effect transistor according to claim 10, wherein A hole is defined below the second drain metal and between the first drain metal pillar and the second drain metal pillar.

12. The field effect transistor according to claim 7, further comprising: a first source metal and source connection field plate (SFP), a second source metal and source connection field plate (SFP), a first gate finger, and a second gate finger, wherein The first source metal and SFP and the second source metal and SFP are respectively sized and positioned to include overhangs that define overhang holes, respectively, in which the first gate finger and the second gate finger are respectively positioned.

13. The field effect transistor according to claim 7, wherein The field effect transistor is a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), or a metamorphic high electron mobility transistor (mHEMT).

14. The field effect transistor according to claim 7, wherein The field effect transistor is a gallium nitride (GaN) transistor on silicon or a GaN transistor on silicon carbide.

15. A field effect transistor comprising: a gate manifold, a first source metal, and a second source metal; a drain metal positioned over the drain ohmic contacts and between the first source metal and the second source metal, wherein the drain metal comprises a drain metal body having a gap region positioned between the drain ohmic contacts and between the first source metal and the second source metal; as well as a shield having a first end connected to an end of the first source metal and a second end connected to an end of the second source metal, the shield being positioned between the gate manifold and the end of the drain metal and extending along the end of the drain metal between the gate manifold and the end of the drain metal.

16. The field effect transistor according to claim 15, wherein The width of the shield is between 10 μm and 15 μm.

17. The field effect transistor according to claim 15, wherein The shield includes a first step region, a second step region, and a recessed region positioned between the first step region and the second step region, the recessed region being in direct contact with the substrate, the first step region and the second step region being elevated from a surface of the substrate.

18. The field effect transistor according to claim 17, wherein: The gate manifold includes a gate manifold body, a first angled gate tab, and a second angled gate tab; the first angled gate tab is positioned in a recess defined by a first stepped region of the shield such that the shield does not contact the first angled gate tab; and The second angled gate tab is positioned in a recess defined by the second step region of the shield such that the shield does not contact the second angled gate tab.

19. The field effect transistor according to claim 15, wherein: The field effect transistor includes a substrate; The drain metal includes a first drain metal column and a second drain metal column; The field effect transistor includes a second drain metal; The first drain metal pillar and the second drain metal pillar are positioned below the second drain metal, on a first distal end and a second distal end of the second drain metal, respectively; defining a hole below the second drain metal and between the first drain metal pillar and the second drain metal pillar; The field effect transistor further comprises: a first source metal and a source connection field plate (SFP), a second source metal and a source connection field plate (SFP), a first gate finger, and a second gate finger; and The first source metal and SFP and the second source metal and SFP are respectively sized and positioned to include overhangs that define overhang holes, respectively, in which the first gate finger and the second gate finger are respectively positioned.

20. The field effect transistor according to claim 15, wherein The field effect transistor is a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), or a metamorphic high electron mobility transistor (mHEMT).

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