A multi-beam sonar signal source signal generation circuit and device

Abstract

The present invention discloses a multi-beam sonar source signal generation circuit and device. The device includes: a host computer, a digital coding circuit module, a multi-channel signal conversion circuit, a power amplification circuit, and a transducer. By converting the original signal generated by the host computer into coded data, and then transmitting the coded data through a bus to the multi-channel signal conversion circuit to generate positive and negative half-cycle signals. Finally, each path of the transmitted signal is processed in parallel by the power amplification circuit module, and the final sonar transducer transmitted source signal is generated through the method of driving and amplification. This circuit and device can provide source signals with different signal systems according to actual needs, solve the problem of insufficient adaptability of the sonar signal transmitter to provide source signals due to changes in different detection environment requirements, and do not use high-cost solutions such as conventional digital frequency synthesis chips and cache memory chips, reducing the cost while meeting the usage requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of sonar electronic systems, and in particular to a multi-beam sonar source signal generating circuit and device. Background Art

[0002] Multi-beam sonar is a device based on hydroacoustic technology used to perform underwater observation and detection tasks. It plays an important role in anti-frogman intrusion, underwater vehicle monitoring, offshore surveillance and protection, etc. In the process of performing underwater security tasks, the main task of the sonar transmitter is to generate one or more specific forms (waveforms) of signals and amplify their power, driving the lower-level transducer to convert the amplified electrical signals into sound waves and radiate them into the water. It is usually required that the signal source of the multi-beam sonar can be adjusted accordingly according to the different detection environments, so that better detection effects can be obtained for different targets in different scenarios. This puts forward the need for an adjustable signal source for the multi-beam sonar.

[0003] At present, in most application scenarios such as offshore oil platform security and dock ports, different types of pulse signals have their own advantages and disadvantages in detection and positioning for different detection targets. For example, the use of CW signals for high-speed target detection under a high reverberation background, the high distance resolution of FM pulse signals and the comprehensive advantages of PRN pulses, etc., require adjusting the system parameter size of the electrical signal generated by the transmitting signal source to achieve this.

[0004] Most of the existing technologies use direct digital synthesis (DDS) digital signal processing, in which voltage amplitudes are given by different phases and filtered after phase-amplitude conversion. The frequency, phase and amplitude of the DDS output signal can be accurately and quickly converted under the control of the processor. This method has the advantages of high resolution and fast conversion time. However, with the increase in the number of transmission channels and the increase in the types of required signal forms, the DDS output frequency band is limited by the operating speed of the internal DAC and waveform memory. Due to its fully digital design, the output signal has spurious signals (caused by truncation errors of the phase accumulator, amplitude quantization errors due to limited word length of the memory, and irrational characteristics of the DAC, etc.). Considering the influence of spurious signals, combining PLL frequency synthesis technology with DDS can solve the problem, but it will invisibly increase the volume and cost of hardware resources, making it difficult for multi-beam sonar to adapt to more scene requirements. Summary of the invention

[0005] In response to the above problems, the inventors provide a multi-beam sonar source signal generation circuit and device, which can generate sonar signals of different signal systems to meet actual usage needs.

[0006] According to a first aspect, the present invention provides a multi-beam sonar source signal generating circuit, characterized in that it comprises:

[0007] A digital encoding circuit module is disposed inside an underwater sonar. It is used to decode the received original signal data packet into multi-channel analog signals, convert the multi-channel analog signals into multiplexed encoded digital signals, and also used to copy the multiplexed encoded digital signals into two sets of signals with timing synchronization.

[0008] A multi-channel signal conversion circuit is signal-connected to the output end of the digital encoding circuit module. It is used to convert the first set of signals into positive half-cycle signals and the second set of signals into negative half-cycle signals.

[0009] A power amplification circuit is signal-connected to the output end of the multi-channel signal conversion circuit. The output end of the power amplification circuit is connected to a transducer. It is used to amplify the positive half-cycle signals and negative half-cycle signals and then connect them to the transducer to drive the transducer to emit source signals.

[0010] Further, the multi-channel signal conversion circuit includes: multiple sets of latch flip-flop groups. Each set of latch flip-flop groups includes multiple flip-flop chips, and each flip-flop chip processes multiple signals in parallel.

[0011] Further, the power amplification circuit includes:

[0012] A drive circuit, whose input end is connected to a pull-down resistor and the output end of the multi-channel signal conversion circuit;

[0013] A push-pull amplification circuit, whose input end is provided with an absorption circuit composed of diodes V3, V4 and resistors R3, R4.

[0014] Further, the push-pull amplification circuit includes: an absorption high-order harmonic circuit composed of capacitors C5, C6 and resistors R5, R6.

[0015] Further, the digital encoding circuit module is also used for: when the enable signal of the digital encoding circuit module changes from low to high, sampling the analog signal of each channel through a clock sampling signal and performing analog-to-digital conversion at the same time.

[0016] Further, the multi-channel signal conversion circuit includes: latch flip-flop group A1, latch flip-flop group A2 and latch flip-flop group B1;

[0017] The input end of the latch flip-flop group A1 is connected to the first set of signals and the clock signal CLKA. It is used to trigger the first set of signals by the clock signal CLKA and perform timing caching when the transmit enable signal is at a low level to obtain a cached area signal;

[0018] The latch flip-flop group A2 is connected to the cached area signal and the clock signal CLKB. It is used to directly trigger the cached area signal by the clock signal CLKB when the transmit enable signal is valid again to obtain positive half-cycle signals;

[0019] The input end of the latch flip-flop group B1 is connected to the second group of signals and the clock signal CLKB, and is used to directly output a negative half-cycle signal when the transmission enable signal is valid.

[0020] Furthermore, the clock signals CLKA and CLKB have the same frequency and a phase difference of 1 / 4 clock cycle.

[0021] Furthermore, the latch flip-flop group A1, the latch flip-flop group A2, and the latch flip-flop group B1 are all composed of 8 trigger chips. Each latch flip-flop chip processes 16 signals in parallel, and the latch flip-flop group A1, the latch flip-flop group A2, and the latch flip-flop group B1 can all process 128 multi-channel signals.

[0022] According to a second aspect, the present invention further provides a multi-beam sonar source signal generation device, including: a host computer, a transducer, and the multi-beam sonar source signal generation circuit as described in the above claims. The host computer is located above the water and is network-connected to the digital coding circuit module, and is used to set the transmission signal parameters, synchronously generate a specified signal according to the transmission signal parameters, and convert and pack the specified signal into a data packet and send it to the digital coding circuit module.

[0023] Furthermore, the host computer is also used to limit the amplitude of the specified signal through a threshold, convert the amplitude-limited specified signal into a binary signal, pack it into a data packet, and send it to the digital coding circuit module.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] (1) The multi-beam sonar source signal generation circuit and device provided by the present invention can provide source signals with different signal systems according to actual needs, and can solve the problem of insufficient adaptability of the sonar signal transmitter to provide source signals due to changes in different detection environment requirements.

[0026] (2) It meets the design requirements of low cost. It does not use high-cost solutions such as digital frequency synthesis chips and cache memory chips. Instead, it uses trigger chips, which have the advantages of buffer storage, low trigger delay, strong anti-interference ability, long service life, and low cost, and meet the design requirements of safety, stability, and high efficiency of the multi-beam sonar signal source system. Description of the Drawings

[0027] Figure 1 It is a schematic diagram of the multi-beam sonar source signal generation device in Embodiment 1;

[0028] Figure 2 It is a schematic diagram of the multi-channel signal conversion circuit in Embodiment 1;

[0029] Figure 3Schematic diagram of the power amplifier circuit in Embodiment 1;

[0030] Figure 4 is Figure 3 schematic diagram of the drive circuit in;

[0031] Figure 5 Schematic diagram of the original signal waveform generated by the host computer and the binary processing in Embodiment 1;

[0032] Figure 6 Schematic diagram of the generation of timing encoded data of the FPGA encoding circuit module in Embodiment 1;

[0033] Figure 7 Timing diagrams of each node of the multi-channel signal conversion circuit module in Embodiment 1. Detailed implementation manners

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific implementation manners.

[0035] Embodiment 1

[0036] As Figure 1 shown, the present invention provides a multi-beam sonar source signal generation device, including a water surface dry end and an underwater wet end. The water surface dry end is a host computer 1, which is built with signal generation software, mainly completes the configuration of multi-beam sonar transmission signal parameters, and sends the original waveform data to the underwater sonar head electronic cabin through the RS serial port. This program is an existing program and will not be elaborated here. The underwater wet end is located inside the underwater sonar head, and includes: an FPGA digital encoding circuit module 2, a multi-channel signal conversion circuit 3, a power amplifier circuit 4 and a transducer, which are sequentially connected by signals.

[0037] The FPGA digital encoding circuit module 2 is connected to the host computer 1 through an optical fiber, and the optical fiber transmits the data packet generated by the host computer 1 to the FPGA digital encoding circuit module 2 for encoding conversion through a network transmission protocol. The multi-channel signal conversion circuit 3 is signal-connected to the output end of the FPGA digital encoding circuit module 2, and is used to convert the multiplexed encoded digital signals DATA sent by the FPGA digital encoding circuit module 2 into a positive half-cycle signal and a negative half-cycle signal Specifically, as Figure 2 shown, the multi-channel signal conversion circuit 3 includes: latch flip-flop groups A1, A2 and B1. Among them, the latch flip-flop groups A1, A2 and B1 are all composed of 8 flip-flop chips, and each latch flip-flop chip processes 16 signals in parallel. Therefore, each group of latch flip-flop groups A1, A2 and B1 can process 128 multi-channel signals. In actual use, corresponding adjustments can be made according to actual situations to realize the processing of multi-channel signals such as 256 / 512.

[0038] As shown Figure 3 in the figure, the power amplifier circuit 4 includes a driving circuit and a push-pull amplifier circuit. The input INA / INB of the driving circuit is connected to the positive half-cycle signal and the negative half-cycle signal while connecting 10KΩ pull-down resistors R1 and R2 to ensure that the input end of the push-pull amplifier circuit is at a low level when there is no input signal. The power amplifier circuit 4 is connected to 12VDC to supply power to the driving circuit, and connected to 200VDC to supply power to the push-pull amplifier circuit and perform voltage conversion. The driving circuit uses a dual-power high-speed MOSFET driving chip, and the maximum output peak current can reach 1.5A. The input supply voltage has a wide range of 4.5V - 18V. The input end of the push-pull amplifier circuit is provided with an absorption circuit composed of diodes V3, V4 and resistors R3, R4 to prevent the push-pull amplifier circuit from causing signal crosstalk to the driving circuit. The input signal terminal of the driving circuit is connected to the driving pin with high impedance, and is also compatible with TTL / CMOS input. The output terminals OUTA and OUTB of the driving circuit are in a low-impedance state and are also CMOS push-pull outputs. The output terminals OUTA and OUTB are connected to the push-pull amplifier circuit for amplification after passing through a direct absorption circuit. The push-pull amplifier circuit includes: MOSFET transistors V1, V2, diodes V7, V8, transformer TRANS, and a harmonic absorption circuit composed of capacitors C5, C6 and resistors R5, R6. The setting of the harmonic absorption circuit can eliminate the peak-end spike interference of the reverse voltage induced by the transformer TRANS. The push-pull amplifier circuit enables the transducer to obtain the maximum electric power signal required for sonar detection. The output transformer TRANS of the output terminal uses a high-frequency power transformer for step-up, and the turns ratio is N1∶N2 = 5∶8. The positive and negative half-cycle signals after voltage conversion are connected to the positive and negative terminals of the transducer. Further, the maximum current that the MOSFET transistors V1 and V2 can pass through is limited to:

[0039]

[0040] In the formula, P0 is the theoretical power of the transmitter, and the estimation process is calculated according to 1.5 times the theoretical value of the output power of the signal transmitter (the transformer loss in the actual operation of the sonar needs to be considered), V CC is the turn-off voltage of the MOSFET transistor, and V CE is the turn-on voltage of the MOSFET transistor. If it is considered that the output of the sonar transmission signal source is a square wave with a duty cycle of 50%, the conduction time of the MOSFET transistor is:

[0041] t on = 1 / 2f0

[0042] where f0 is the center frequency of the sonar-generated transmission signal.

[0043] When selecting the MOSFET transistor, it should satisfy the turn-on time t r and the turn-off time tf The sum is less than the conduction time t on / 10 to avoid a large signal delay. When the MOSFET V1 is conducting, the voltage applied to the drain of the MOSFET V2 becomes 2V CC ; when the MOSFET V2 is conducting, the voltage applied to the drain of the MOSFET V1 is also 2V CC . At the same time, considering that the transformer TRANS usually introduces spike pulse effects, a certain margin is reserved when selecting the maximum drain-source voltage of the MOSFET.

[0044] This push-pull amplifier circuit has a high degree of anti-latch-up property. Because of the conditions within its power and voltage ratings, when a noise spike (either polarity) up to 5V appears on the ground terminal GND, the circuit function is not easily damaged. When a reverse current (either polarity) reaches 500mA and is applied to the circuit, it can be directly accepted and forced to feedback to the output terminal, so that the logic is not damaged. All inputs and outputs in the drive circuit can be protected against electrostatic discharge (ESD) up to 4 kV, while enhancing the power amplification ability of the subsequent push-pull amplifier circuit.

[0045] Specifically, the process of generating the multi-beam sonar source signal includes the following steps:

[0046] Step of issuing the original signal: Manually set the transmission signal parameters on the host computer 1. The host computer 1 synchronously generates a specified signal according to the transmission signal parameters, and converts and packs the specified signal into a data packet and issues it to the FPGA digital encoding circuit module 2. The way that the host computer 1 simulates the original signal data can ignore the interference brought by the hardware noise of the signal generation circuit, ensuring the stability of the signal timing data. Specifically, taking the original single-frequency signal with the center frequency of f0 and the initial phase of t ∈ [0, T], e(t) is the signal envelope, and the duration is T. Define the signal amplitude threshold as T th , and perform the threshold-crossing processing on s ori (t) continuously, that is

[0047]

[0048] where s h , s l correspond to the logic high level and low level states respectively. The waveform of the converted signal is as Figure 5 shown. In the figure, a single-frequency signal mode with 3 cycles is taken as an example for illustration, and the signal period T = 1 / f0. The signal is amplitude-limited through the threshold T th and converted into binary state data, where the high level state s h (High level) can be amplitude-limited to but not limited to the threshold T th , and the low level state sl (Low level) can be limited to but not limited to T th . The processed binary state data will be sent to the FPGA digital encoding circuit module 2 in the form of data packets through the fiber optic network.

[0049] Encoding step: After receiving the data packet, the FPGA digital encoding circuit module 2 decodes it into multi-channel analog signals and converts the multi-channel analog signals into multiplexed encoded digital signals DATA. Specifically, after receiving the data packet sent by the host computer 1 through the network communication protocol, when the enable signal is detected to change from low to high, the FPGA digital encoding circuit module 2 samples the analog signals of 128 channels through the high-frequency clock sampling signal and simultaneously performs analog-to-digital conversion. The sampling signal frequency f s , the number of signal sample points N = Tf s , the digital signal after encoding conversion of the pulse train within one period by the FPGA encoding circuit module 2 is as Figure 6 shown. The 128-channel encoded signal pulse trains are stored in the ARM core after synchronization processing for subsequent processing by the multi-channel signal conversion circuit 3.

[0050] Signal conversion step: The multiplexed encoded digital signal DATA is copied into two groups of signals with time sequence synchronization. The multi-channel signal conversion circuit 3 converts the first group of signals into positive half-cycle signals and converts the second group of signals into negative half-cycle signals

[0051] Specifically, the 128-channel encoded data DATA output by the FPGA encoding circuit module 2 is represented in matrix form and copied into two groups of signals with time sequence synchronization as known The first group of signals is converted into positive half-cycle signals The specific conversion process is as follows:

[0052] The first group of signals and the clock signal CLKA are input to the latch flip-flop group A1. The latch flip-flop group A2 is input with the clock signal CLKB. The frequencies of the clock signals CLKA and CLKB are and there is a phase difference of 1 / 4 clock cycle. When the transmission enable signal is at a low level, the clock signal CLKA triggers the first group of signals and performs time sequence caching to obtain the buffered signal When the transmission enable signal becomes valid again, the buffered signal is input to the latch flip-flop group A2, and the clock signal CLKB directly triggers the buffered signal to obtain the positive half-cycle signal

[0053] The second group of signals is converted into a negative half-cycle signal The specific process is as follows:

[0054] The second group of signals and the clock signal CLKB are input into the latch flip-flop group B1. When the transmission enable signal is valid, the negative half-cycle signal is directly output

[0055] The transmission permission enable signal controls the triggering timing of the two groups of signals at the same time. The two transmitted signals (i.e., known ) that have undergone the logic triggering process of the latch flip-flop group meet the requirements of synchronization, the same period, and not outputting a high-level state simultaneously.

[0056] As Figure 7 shown, the output signals and overlap with each other. The dead time is controlled by the PWM output. It is a protection period set to prevent the upper and lower half-bridges of the H-bridge from conducting simultaneously due to the on and off delay problems. When the dead time is set larger, the module can work more reliably, but it will cause distortion of the output waveform and a decrease in the output efficiency. When the dead time is designed to be small, the output waveform is better. For the purpose of not blowing up the MOSFET tubes and not short-circuiting the output, the present invention controls the dead time within 200 ns through a timing control method.

[0057] Power amplification step: The power amplification circuit 4 amplifies the positive half-cycle signal and the negative half-cycle signal and then connects them to the transducer to drive the transducer to emit the source signal. There is the following constraint relationship between the pulse width TP of the source signal and the minimum detection distance Rmin of the sonar and the sonar distance resolution ΔR:

[0058] T P ≤2R min / c

[0059] T P ≤2ΔR / c

[0060] where c is the speed of sound.

[0061] The above uses specific examples to illustrate the present invention, which is only used to help understand the present invention and does not limit the present invention. For those skilled in the art of the present invention, according to the idea of the present invention, several simple deductions, deformations or substitutions can also be made.

Claims

1. A multi-beam sonar source signal generation circuit, characterized in that Comprising: A digital encoding circuit module, disposed inside an underwater sonar, for decoding a received original signal data packet into multi-channel analog signals, converting the multi-channel analog signals into multiplexed encoded digital signals, and further replicating the multiplexed encoded digital signals into two groups of signals with timing synchronization; A multi-channel signal conversion circuit, signal-connected to the output end of the digital encoding circuit module, for converting the first group of signals into positive half-cycle signals and the second group of signals into negative half-cycle signals; A power amplification circuit, signal-connected to the output end of the multi-channel signal conversion circuit, with the output end of the power amplification circuit connected to a transducer, for amplifying the positive half-cycle signals and the negative half-cycle signals and then connecting them to the transducer to drive the transducer to emit a source signal; The multi-channel signal conversion circuit includes: a latch flip-flop group A1, a latch flip-flop group A2, and a latch flip-flop group B1; The input end of the latch flip-flop group A1 is connected to the first group of signals and a clock signal CLKA, and is used for, when the transmission enable enable signal is at a low level, triggering the first group of signals by the clock signal CLKA and performing timing caching to obtain a cached area signal; The latch flip-flop group A2 is connected to the cached area signal and a clock signal CLKB, and is used for, when the transmission enable signal becomes valid again, directly triggering the cached area signal by the clock signal CLKB to obtain positive half-cycle signals; The input end of the latch flip-flop group B1 is connected to the second group of signals and a clock signal CLKB, and is used for directly outputting negative half-cycle signals when the transmission enable signal is valid.

2. The multi-beam sonar source signal generation circuit according to claim 1, characterized in that, The power amplification circuit includes: A drive circuit, whose input end is connected to a pull-down resistor and the output end of the multi-channel signal conversion circuit; A push-pull amplification circuit, whose input end is provided with an absorption circuit composed of diodes V3, V4 and resistors R3, R4.

3. The multi-beam sonar signal source signal generation circuit according to claim 2, wherein, The push-pull amplification circuit includes: an absorption high-order harmonic circuit composed of capacitors C5, C6 and resistors R5, R6.

4. The multi-beam sonar source signal generation circuit according to claim 1, characterized in that, The digital encoding circuit module is further used for: when the enable signal of the digital encoding circuit module changes from low to high, sampling the analog signal of each channel by a clock sampling signal and simultaneously performing analog-to-digital conversion.

5. The multi-beam sonar source signal generation circuit according to claim 1, characterized in that, The clock signals CLKA and CLKB have the same frequency and a phase difference of 1 / 4 clock cycle.

6. The multi-beam sonar signal source signal generation circuit according to claim 1, wherein The latch flip-flop group A1, the latch flip-flop group A2, and the latch flip-flop group B1 are each composed of 8 trigger chips, and each trigger chip processes 16 channels of signals in parallel. The latch flip-flop group A1, the latch flip-flop group A2, and the latch flip-flop group B1 can all process 128 channels of multi-channel signals.

7. A multi-beam sonar signal source signal generation device, comprising: An upper computer and a transducer, characterized in that it further includes a multi-beam sonar source signal generation circuit as described in any one of claims 1-6. The upper computer is located above water and is network-connected to the digital encoding circuit module, and is used for setting transmission signal parameters, synchronously generating a specified signal according to the transmission signal parameters, and converting and packing the specified signal into a data packet and sending it to the digital encoding circuit module.

8. The device according to claim 7, characterized in that, The upper computer is further used for limiting the amplitude of the specified signal through a threshold, converting the amplitude-limited specified signal into a binary signal, packing it into a data packet and sending it to the digital encoding circuit module.

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