Display panel

Abstract

A display panel includes a substrate and a pixel circuit. The pixel circuit is disposed on the substrate, wherein the pixel circuit is configured to drive a light-emitting unit, and the pixel circuit includes a first wire, a second wire disposed adjacent to the first wire, a third wire, and a fourth wire. The first wire and the second wire are disposed between the third wire and the fourth wire. The first wire, the second wire, the third wire, and the fourth wire extend in the same direction. A first distance Y1 between the first wire and the second wire and a second distance Y2 between the third wire and the fourth wire satisfy the following relationship: 0 ≦ Y1 / Y2 ≦ 0.25.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display panel, and in particular, to a display panel with different distances between wires. Background Art

[0002] It is known that a display panel of an electronic device uses a relatively large number of signal lines to drive light-emitting components to generate light corresponding to a brightness. However, when an electronic device uses a relatively large number of signal lines, it will occupy more space, resulting in larger pixels of the display panel. Therefore, problems such as a decrease in the resolution of the display panel may occur, which may reduce the display quality of the electronic device. Therefore, a new display panel is needed to change the arrangement of the signal lines to improve the resolution of the display panel and solve the foregoing problems. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display panel, including a substrate and a pixel circuit. The pixel circuit is disposed on the substrate, wherein the pixel circuit is configured to drive a light-emitting unit, and the pixel circuit includes a first wire, a second wire disposed adjacent to the first wire, a third wire, and a fourth wire. The first wire and the second wire are disposed between the third wire and the fourth wire. The first wire, the second wire, the third wire, and the fourth wire extend in the same direction. A first distance Y1 between the first wire and the second wire and a second distance Y2 between the third wire and the fourth wire satisfy the following relationship: 0 ≦ Y1 / Y2 ≦ 0.25.

[0004] Embodiments of the present disclosure provide a display panel, including a substrate, a first wire, and a second wire. The substrate has a sensing area and a non-sensing area adjacent to the sensing area. The first wire and the second wire are disposed on the substrate and extend in the same direction. The second wire is disposed adjacent to the first wire. A first distance between the first wire and the second wire in the sensing area is different from a second distance between the first wire and the second wire in the non-sensing area. Description of the Drawings

[0005] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings, wherein:

[0006] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0007] Figure 2 Schematic circuit diagram of a pixel of an electronic device according to an embodiment of the present disclosure.

[0008] Figure 3 Schematic diagram of the arrangement of wires of a pixel circuit of an electronic device according to an embodiment of the present disclosure.

[0009] Figure 4 is Figure 3 a sectional view taken along line A-A’ of

[0010] Figure 5 a schematic diagram of a wire according to an embodiment of the present disclosure.

[0011] Figure 6 a schematic diagram of a wire according to another embodiment of the present disclosure.

[0012] Figure 7A a schematic diagram of a wire according to another embodiment of the present disclosure.

[0013] Figure 7B a schematic diagram of a wire according to another embodiment of the present disclosure.

[0014] Figure 8A a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0015] Figure 8B a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0016] Figure 9A a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0017] Figure 9B a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0018] Figure 10A a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0019] Figure 10B a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0020] Figure 11A a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0021] Figure 11B a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0022] Figure 12A a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0023] Figure 12B a schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0024] Figure 13A a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0025] Figure 13B Schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0026] Figure 13C Schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure.

[0027] Figure 14A Schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0028] Figure 14B Schematic diagram of a display panel according to an embodiment of the present disclosure.

[0029] Figure 15A Schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 15B For Figure 15A Cross-sectional view of line B-B'.

[0031] Figure 16A Top view of the arrangement relationship between the semiconductor layer and the wire of a display panel according to an embodiment of the present disclosure.

[0032] Figure 16B For Figure 16A Cross-sectional view of line C-C'.

[0033] Figure 17A Cross-sectional view of the semiconductor layer and the light-shielding layer arrangement in the sensing area and the non-sensing area of a display panel according to an embodiment of the present disclosure.

[0034] Figure 17B Cross-sectional view of the semiconductor layer and the light-shielding layer arrangement in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure.

[0035] Figure 17C Cross-sectional view of the semiconductor layer and the light-shielding layer arrangement in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure.

[0036] Figure 17D Cross-sectional view of the semiconductor layer and the light-shielding layer arrangement in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure.

[0037] Figure 17E Cross-sectional view of the semiconductor layer and the light-shielding layer arrangement in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure.

[0038] Figure 17FA cross-sectional view of the semiconductor layer and the light-shielding layer in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure.

[0039] Description of Reference Numerals

[0040] 100, 1300, 1400, 1500: Electronic device

[0041] 110, 1310, 1510, 1600, 1700, 1701, 1702, 1703, 1704, 1705, 1706: Display panel

[0042] 111, 1311, 1511, 1650, 1711: Substrate

[0043] 112, 1312, 1313, 1512, 1513: Pixel

[0044] 113, 13121, 13131: Pixel circuit

[0045] 114, 1514: Light-emitting unit

[0046] 120, 120_1, 120_2, 130, 130_1, 130_2, 140: Driving circuit

[0047] Vini1, Vini2, SN11-1~SN11-5, SN12-1~SN12-2, EM1~EM2, SN21-1~SN21-5, SN22-1, LDATA, LVDD, LVSS, 510, 620, 630, 710, 720, LDATA1, LDATA2, 1630, 1640, 1732, 1752: Conductive wire

[0048] C1: Capacitor

[0049] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11: Transistor

[0050] 1: First end

[0051] 2: Second end

[0052] VDD, VSS: Reference voltage

[0053] Y1, Y2, Y1-1, Y1-2: Distance

[0054] 511, 621, 631: Non-linear part

[0055] 5111: Protrusion

[0056] 5112: Concave part

[0057] 512,622,632: Straight line part

[0058] 623,633: Virtual extension line

[0059] 1320,1520,1720: Sensing area

[0060] 1330,1530,1710: Non - sensing area

[0061] 1516,1517: Area

[0062] 1610,1620,1730,1740,1750,1760: Semiconductor layer

[0063] 1731,1751,1761,1770: Light - shielding layer

[0064] 1780: Connection component Detailed implementation manners

[0065] To make the purpose, features or advantages of the present disclosure more obvious and understandable, specific embodiments are given below and detailed descriptions are made in conjunction with the accompanying drawings. For the convenience of readers' understanding and the simplicity of the drawings, multiple drawings in the present disclosure may only show a part of the entire device, and specific components in the drawings are not drawn according to the actual scale.

[0066] This specification of the present disclosure provides different embodiments to illustrate the technical features of different implementation manners of the present disclosure. Among them, the configuration, quantity and size of each component in the embodiments are for illustrative purposes and are not used to limit the present disclosure. In addition, if there are repetitions in the component numbers between the embodiments and the drawings, it is for the sake of simplifying the description and does not imply the relevance between different embodiments.

[0067] Furthermore, the ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify the components of the claims. They do not themselves imply or represent that the claimed component has any previous ordinal number, nor do they represent the order between one claimed component and another claimed component, or the order in the manufacturing method. The use of these multiple ordinal numbers is only to clearly distinguish one claimed component with a certain name from another claimed component with the same name.

[0068] In the present disclosure, as long as the features between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily combined and used.

[0069] The term "comprising" mentioned throughout the specification and claims is an open - ended term and should be interpreted as "including but not limited to".

[0070] Furthermore, "connect" and "couple" herein include any direct and indirect connection means. Therefore, when a component or a film layer is referred to as "connected" to another component or film layer, it can be directly connected to this other component or film layer, or there are intervening components or film layers between the two. When a component is referred to as "directly connected" to another component or film layer, there are no intervening components or film layers between the two. If it is described in the text that a first device on a circuit is coupled to a second device, it means that the first device can be directly electrically connected to the second device. When the first device is directly electrically connected to the second device, the first device and the second device are connected only through wires or passive components (such as resistors, capacitors, etc.), and there are no other electronic components connected between the first device and the second device.

[0071] Direction terms mentioned in this document, such as "upper", "lower", "front", "rear", "left", "right", etc., are only with reference to the directions in the accompanying drawings. Therefore, the direction terms used are for illustration purposes and not for limiting the present disclosure. In the accompanying drawings, each drawing shows the general characteristics of the methods, structures, and / or materials used in specific embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of each film layer, region, and / or structure may be reduced or enlarged.

[0072] It should be understood that when a component or a film layer is referred to as "on" another component or film layer, it can be directly on this other component or film layer, or there are intervening components or film layers between the two (non-direct case). Conversely, when a component is referred to as "directly" "on" another component or film layer, there are no intervening components or film layers between the two. Terms regarding joining and connection can also include cases where both structures can move, or both structures are fixed.

[0073] In the present disclosure, the thickness, length, and width can be measured by using optical microscopy (OM), and the thickness or length can be measured from the cross-sectional images in a scanning electron microscope (SEM), but not limited thereto. Additionally, there may be a certain error between any two numerical values or directions used for comparison.

[0074] It should be understood that although terms such as first, second, etc. may be used herein to describe various components, parts, regions, layers, or / and portions, the various components, parts, regions, layers, or / and portions should not be limited by these terms. These terms are only used to distinguish one component, part, region, layer, or / and portion from another component, part, region, layer, or / and portion. Thus, without departing from the teachings of the present disclosure, the first component, first part, first region, first layer, or first portion discussed below may also be referred to as the second component, second part, second region, second layer, or second portion.

[0075] In addition, phrases such as "in the range between a first value and a second value" or "in the range from a first value to a second value" mean that the range includes the first value, the second value, and other values therebetween.

[0076] The terms "about", "equal to", "equivalent to" or "the same as", "substantially" or "substantially the same as" generally represent within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0077] In one embodiment, the electronic device may include liquid crystal (LC), organic light emitting diode (OLED), inorganic light emitting diode (LED), quantum dot (QD), fluorescent material, phosphorescent material, other suitable materials, or a combination of the above materials, but the present disclosure is not limited thereto. The inorganic light emitting diode may include, for example, a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (QLED), but the present disclosure is not limited thereto.

[0078] In some embodiments, the electronic device may be a display device, a sensing device, a touch device, a curved device, a tiled device, or a free shape device, or may also be a bendable or flexible tiled device, but is not limited thereto.

[0079] It should be noted that the electronic device can be any of the foregoing permutations and combinations, but is not limited thereto. In addition, the outer shape of the electronic device can be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device can have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. to support the display device.

[0080] In one embodiment, the electronic device can be a display device, but the present disclosure is not limited thereto. Please refer to Figure 1 、 Figure 2 、 Figure 3 and Figure 4 , Figure 1 which is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. Figure 2 which is a circuit schematic diagram of a pixel 112 of the electronic device 100 according to an embodiment of the present disclosure. Figure 3 which is a schematic diagram of the arrangement of the wires of the pixel circuit 113 of the electronic device 100 according to an embodiment of the present disclosure. Figure 4 which is Figure 3 a cross-sectional view taken along line A-A' of. The electronic device 100 can include a display panel 110, and the display panel 110 can at least include a substrate 111, pixels 112, a driving circuit 120, a driving circuit 130, and a driving circuit 140.

[0081] In addition, in Figure 1 , only one pixel 112 is shown, but the present disclosure is not limited thereto. In some embodiments, the number of pixels 112 can be multiple, arranged in a matrix form, and disposed on the substrate 111. Please refer to Figure 2 , the pixel 112 includes a pixel circuit 113 and a light-emitting unit 114 coupled to the pixel circuit 113. The pixel circuit 113 can be disposed on the substrate 111, and the pixel circuit 113 is configured to drive the light-emitting unit 114.

[0082] The first end of the light-emitting unit 114 can be coupled to the pixel circuit 113, and the second end of the light-emitting unit 114 can be coupled to a wire LVSS to receive a reference voltage VSS (such as a ground voltage). In this embodiment, the light-emitting unit 114 can be an organic light-emitting diode, an inorganic light-emitting diode, other suitable materials, or a combination of the above materials, but the present disclosure is not limited thereto. The first end of the light-emitting unit 114 can be an anode, and the second end can be a cathode, but the present disclosure is not limited thereto.

[0083] The pixel circuit 113 may include a capacitor C1, transistors T1, T2, T3, T4, T5, T6, T7, a wire Vini1, wires SN11-1, SN12-1, a wire EM1, wires SN21-1, SN22-1, a wire LDATA, a wire LVDD, as Figure 2 shown, but the present disclosure is not limited thereto.

[0084] The capacitor C1 has a first terminal and a second terminal. The first terminal of the capacitor C1 is coupled to the wire LVDD to receive a reference voltage VDD (e.g., an operating voltage).

[0085] Each of the transistors T1, T2, T3, T4, T5, T6, T7 includes a gate, a channel region, a source region, and a drain region. The channel region, the source region, and the drain region may be formed of a semiconductor layer. The channel region overlaps with the gate. In one embodiment, a conductor layer may be coupled to the source region and the drain region through a hole to form a source electrode and a drain electrode. The semiconductor layer may include a silicon semiconductor, an oxide semiconductor, other suitable materials, or a combination of the foregoing materials, and the present disclosure is not limited thereto. The silicon semiconductor may include an amorphous silicon semiconductor, a single crystalline silicon semiconductor, a poly-silicon semiconductor, or other suitable materials, and the present disclosure is not limited thereto. The oxide semiconductor may include an indium gallium zinc oxide (IGZO) semiconductor or other suitable materials, and the present disclosure is not limited thereto. The transistor may include a bottom gate transistor, a top gate transistor, a double gate transistor, or a combination of the foregoing transistors, and the present disclosure is not limited thereto. In addition, when the transistor includes different semiconductor layers, its source region and drain region (or source electrode and drain electrode) may be interchanged, and the present disclosure is not limited thereto.

[0086] In one embodiment, the pixel circuit 113 may include at least a portion of a conductor layer. The conductor layer may include wires and may be coupled to the gate of a transistor, and signals may be present on the wires to control the transistor through the gate. Additionally, if different transistors can share semiconductors, that is, the drain region of one transistor is coupled to the source region of another transistor, then half of the region between the two channel regions belongs to the drain region of one transistor and the other half belongs to the source region of the other transistor.

[0087] The transistor T1 has a gate, a first terminal 1, and a second terminal 2. The gate of the transistor T1 is coupled to the second terminal of the capacitor C1. In this embodiment, the transistor T1 may be a low temperature poly-silicon (LTPS) semiconductor P-type thin film transistor, but the present disclosure is not limited thereto. At this time, the first terminal 1 of the transistor T1 is, for example, a drain region, and the second terminal 2 of the transistor T1 is, for example, a source region. However, it is also possible that the first terminal 1 is, for example, a source region and the second terminal 2 of the transistor T1 is, for example, a drain region. The present disclosure is not limited thereto. In some embodiments, the transistor T1 may also be a low temperature poly-silicon semiconductor N-type thin film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin film transistor. The present disclosure is not limited thereto.

[0088] The transistor T2 has a gate, a first terminal 1, and a second terminal 2. The gate of the transistor T2 is coupled to the wire SN11-1 to receive a control signal (such as a scan driving signal). The first terminal 1 of the transistor T2 is coupled to the wire LDATA to receive a data signal. The second terminal 2 of the transistor T2 is coupled to the first terminal 1 of the transistor T1. In this embodiment, the transistor T2 may be a low temperature poly-silicon semiconductor P-type thin film transistor. The first terminal 1 of the transistor T2 is, for example, a drain region, and the second terminal 2 of the transistor T2 is, for example, a source region, or the first terminal 1 is a source region and the second terminal 2 is a drain region. The present disclosure is not limited thereto. In some embodiments, the transistor T2 may also be a low temperature poly-silicon semiconductor N-type thin film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin film transistor. The present disclosure is not limited thereto.

[0089] The transistor T3 has a gate, a first terminal 1 and a second terminal 2. The gate of the transistor T3 is coupled to the wire SN22-1 to receive a control signal (such as a scan driving signal). The first terminal 1 of the transistor T3 is coupled to the gate of the transistor T1. The second terminal 2 of the transistor T3 is coupled to the wire Vini to receive a reference signal (such as a common signal), for example, a signal that can be used to reset the light-emitting unit 114. In this embodiment, the transistor T3 may be an indium gallium zinc oxide semiconductor P-type thin-film transistor, but the present disclosure is not limited thereto. The first terminal 1 of the transistor T3 is, for example, a source region, and the second terminal 2 of the transistor T3 is, for example, a drain region, or the first terminal 1 is a drain region and the second terminal 2 is a source region, and the present disclosure is not limited thereto. In some embodiments, the transistor T3 may also be an indium gallium zinc oxide semiconductor N-type thin-film transistor, or a silicon semiconductor (such as a low-temperature polycrystalline silicon semiconductor) thin-film transistor, and the present disclosure is not limited thereto.

[0090] The transistor T4 has a gate, a first terminal 1 and a second terminal 2. The gate of the transistor T4 is coupled to the wire EM1 to receive a control signal (such as an emission signal). The first terminal 1 of the transistor T4 is coupled to the wire LVDD to receive a reference voltage VDD (such as an operating voltage). The second terminal 2 of the transistor T4 is coupled to the second terminal 2 of the transistor T2. In this embodiment, the transistor T4 may be a low-temperature polycrystalline silicon semiconductor P-type thin-film transistor. The first terminal 1 of the transistor T4 is, for example, a drain region, and the second terminal 2 of the transistor T4 is, for example, a source region, or the first terminal 1 is a source region and the second terminal 2 is a drain region, and the present disclosure is not limited thereto. In some embodiments, the transistor T4 may also be a low-temperature polycrystalline silicon semiconductor N-type thin-film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin-film transistor, and the present disclosure is not limited thereto.

[0091] The transistor T5 has a gate, a first terminal 1 and a second terminal 2. The gate of the transistor T5 is coupled to the gate of the transistor T4 and the wire EM1. The first terminal 1 of the transistor T5 is coupled to the second terminal 2 of the transistor T1. The second terminal 2 of the transistor T5 is coupled to the first terminal of the light-emitting unit 114. In this embodiment, the transistor T5 may be a low-temperature polycrystalline silicon semiconductor P-type thin-film transistor. The first terminal 1 of the transistor T5 is, for example, a drain region, and the second terminal 2 of the transistor T5 is, for example, a source region, or the first terminal 1 is a source region and the second terminal 2 is a drain region, and the present disclosure is not limited thereto. In some embodiments, the transistor T5 may also be a low-temperature polycrystalline silicon semiconductor N-type thin-film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin-film transistor, and the present disclosure is not limited thereto.

[0092] The transistor T6 has a gate, a first terminal 1 and a second terminal 2. The gate of the transistor T6 is coupled to the wire SN21-1 to receive a control signal (such as a scan driving signal). The first terminal 1 of the transistor T6 is coupled to the gate of the transistor T1. The second terminal 2 of the transistor T6 is coupled to the second terminal 2 of the transistor T1. In this embodiment, the transistor T6 may be an indium gallium zinc oxide semiconductor P-type thin film transistor. The first terminal 1 of the transistor T6 is, for example, a drain region, and the second terminal 2 of the transistor T6 is, for example, a source region, or the first terminal 1 is a source region and the second terminal 2 is a drain region. The present disclosure is not limited thereto. In some embodiments, the transistor T6 may also be an indium gallium zinc oxide semiconductor N-type thin film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin film transistor. The present disclosure is not limited thereto.

[0093] The transistor T7 has a gate, a first terminal 1 and a second terminal 2. The gate of the transistor T7 is coupled to the wire SN12-1 to receive a control signal (such as a scan driving signal). The first terminal 1 of the transistor T7 is coupled to the wire Vini1 to receive a reference signal (such as a common signal). The second terminal 2 of the transistor T7 is coupled to the second terminal of the transistor T5. In this embodiment, the transistor T7 may be a low temperature polycrystalline silicon semiconductor P-type thin film transistor. The first terminal 1 of the transistor T7 is, for example, a drain region, and the second terminal 2 of the transistor T7 is, for example, a source region, or the first terminal 1 is a source region and the second terminal 2 is a drain region. The present disclosure is not limited thereto. In some embodiments, the transistor T7 may also be a low temperature polycrystalline silicon semiconductor N-type thin film transistor, or an oxide (such as indium gallium zinc oxide) semiconductor thin film transistor. The present disclosure is not limited thereto.

[0094] The wire SN11-1 and the wire SN12-1 are coupled to the driving circuit 120, and the driving circuit 120 is configured to provide corresponding control signals (such as scan driving signals). The wire SN21-1 and the wire SN22-1 are coupled to the driving circuit 130, and the driving circuit 130 is configured to provide corresponding control signals (such as scan driving signals). The wire LDATA and the wire LVDD are coupled to the driving circuit 140, and the driving circuit 140 is configured to provide a data signal and a reference voltage VDD (such as an operating voltage).

[0095] In some embodiments, the wire SN11-1, the wire SN12-1, the wire EM1, the wire Vini1, the wire Vini2, the wire SN21-1 and the wire SN22-1 may be disposed on different layers and made of different metal layers, such as Figure 4As shown. For example, wire SN11-1, wire SN12-1, and wire EM1 are, for example, disposed on the first layer and made of the first metal layer. Wire Vini1 and wire Vini2 are, for example, disposed on the second layer and made of the second metal layer. Wire SN21-1 and wire SN22-1 are disposed on, for example, the third layer and made of the third metal layer. The above-mentioned first layer, second layer, and third layer are different layers, but the present disclosure is not limited thereto. In some embodiments, when multiple pixels are arranged along the Y direction, wire Vini1 and wire Vini2 can be shared with adjacent pixels. However, depending on the arrangement of the wires, different wires can be shared with adjacent pixels, and the present disclosure is not limited thereto.

[0096] In some embodiments, wire SN11-1, wire SN12-1, wire EM1, wire Vini1, wire SN21-1, and wire SN22-1 can receive different signals. In this embodiment, for example, signals can be distinguished as different signals according to the results generated on the electronic device 100 (such as turning on or off a transistor; or making a light-emitting unit emit light or not emit light, etc.), uses (such as being used as a switching transistor; or being used as a fixed voltage potential; or being used as a driving voltage signal; or being used as a data signal, etc.), voltage value magnitudes, or frequency levels, but the present disclosure is not limited thereto.

[0097] In some embodiments, wire SN11-1, wire SN12-1, wire EM1, wire Vini1, wire Vini2, wire SN21-1, and wire SN22-1 can extend in the same direction, such as the X direction, but the present disclosure is not limited thereto.

[0098] In some embodiments, the wire SN11-1 may be the first wire, the wire SN21-1 may be the second wire, the wire Vini1 may be the third wire, and the wire Vini2 may be the fourth wire, but the present disclosure is not limited thereto. Among them, the wire SN11-1 and the wire SN21-1 may be arranged adjacent to each other, and the wire SN11-1 and the wire SN21-1 are, for example, arranged between the wire Vini1 and the wire Vini2. Here, the wire SN11-1 and the wire SN21-1 being arranged adjacent to each other means that no other wire is arranged between the two wires. Additionally, in the Y direction, the distance between the wire SN11-1 and the wire SN21-1 may be a distance Y1 (such as a first distance), and the distance between the wire Vini1 and the wire Vini2 may be a distance Y2 (such as a second distance). For example, the distance Y1 is, for example, the distance between the same sides of the wire SN11-1 and the wire SN21-1 in the direction perpendicular to the extension direction of the wire SN11-1 and the wire SN21-1 (such as the X direction), that is, the distance between the same sides of the wire SN11-1 and the wire SN21-1 in the Y direction, and the distance Y2 is, for example, the distance between the same sides of the wire Vini1 and the wire Vini2 in the Y direction. Further, the distance Y1 is, for example, the distance between the sides of the wire SN11-1 and the wire SN21-1 close to the chip bonding area, and the distance Y2 is, for example, the distance between the sides of the wire Vini1 and the wire Vini2 close to the chip bonding area, but the present disclosure is not limited thereto.

[0099] Please refer to Figure 3 , in the top view direction (the normal direction of the substrate 111, for example, the Z direction), the wire SN11-1, the wire SN12-1, the wire EM1, the wire Vini1, the wire SN21-1, and the wire SN22-1 may be made of metal layers of different layers. Therefore, the distance between the metal layers of different layers in the Y direction can be shortened, or they can be arranged overlappingly.

[0100] In addition, the distance Y1 and the distance Y2, for example, satisfy the following relationship: 0 ≤ Y1 / Y2 ≤ 0.25. Further, the distance Y1 and the distance Y2, for example, satisfy the following relationship: 0 ≤ Y1 / Y2 ≤ 0.102. Additionally, the distance Y2 is, for example, 40 micrometers (um), 50 micrometers, 70 micrometers, or 98 micrometers, etc., but the present disclosure is not limited thereto. In this way, when the distance between the wires is shortened, the pixel density (pixels per inch, PPI) of the display panel can be increased under the same size; or the area of the display panel that is not shielded by the wires can be increased.

[0101] In some embodiments, the wire SN11-1 may be the first wire, the wire SN22-1 may be the second wire, the wire Vini1 may be the third wire, and the wire Vini2 may be the fourth wire, but the present disclosure is not limited thereto. Among them, the wire SN11-1 and the wire SN22-1 may be arranged adjacent to each other, and the wire SN11-1 and the wire SN22-1 are, for example, arranged between the wire Vini1 and the wire Vini2. Here, the wire SN11-1 and the wire SN22-1 being arranged adjacent to each other means that there is no other wire arranged between the two wires. In addition, in the Y direction, the distance between the wire SN11-1 and the wire SN22-1 may be a distance Y1 (not shown in the figure), and the distance between the wire Vini1 and the wire Vini2 may be a distance Y2.

[0102] In Figure 3 the side extension directions of the wire Vini1, the wire SN11-1, the wire SN12-1, the wire EM1, the wire SN21-1, and the wire SN22-1 are substantially parallel to the extension direction of the wire, but the present disclosure is not limited thereto. In some embodiments, it may be as Figure 5 the wire 510 shown or Figure 6 the wires 620 and 630 shown, where the edge curvature of the side of a partial region of the wire changes, so the extension direction of a partial region thereof is not parallel to the extension direction of the wire. In Figure 5 it can be seen that the wire 510 includes a non-linear part 511 and a linear part 512. The edge curvature of the non-linear part 511 changes (for example, there is a protrusion 5111 or a recess 5112), so when measuring the distance, the linear part 512 of the wire 510 is used as a basis. In addition, as Figure 6 shown, the linear parts 622 and 632 of the two wires 620 and 630 may not be correspondingly arranged. For example, the linear part 622 of the wire 620 may correspond to the non-linear part 631 of the wire 630, and the non-linear part 621 of the wire 620 may correspond to the linear part 632 of the wire 630. Therefore, when measuring the distance, an extension line 623 on one side of the linear part 622 of the wire 620 and an extension line 633 on one side of the linear part 632 of the wire 630 can be used as a basis for measuring the distance.

[0103] In addition, in some embodiments, when the wire 710 and the wire 720 at least partially overlap, it means that the distance between the wire 710 and the wire 720 is 0, as shown in Figure 7A (fully overlapping) or Figure 7B (partially overlapping) respectively.

[0104] Figure 8A It is a schematic diagram of the arrangement of the wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 8AIn the pixel circuit 113, the wire SN11-1 and the wire SN22-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance (e.g., 0) between the wire SN11-1 and the wire SN22-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers), or the distance between the wire SN11-1 and the wire SN21-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers). The distance Y2 can be the distance between the wire Vini1 and the wire Vini2 (e.g., the third wire and the fourth wire that receive the same type of signal).

[0105] Figure 8B Schematic diagram of the arrangement of wires in a pixel circuit according to another embodiment of the present disclosure. In Figure 8B In the pixel circuit 113, the wire SN11-1 and the wire SN21-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance (e.g., 0) between the wire SN11-1 and the wire SN21-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers), or the distance between the wire SN11-1 and the wire SN22-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers). The distance Y2 can be the distance between the wire Vini1 and the wire Vini2 (e.g., the third wire and the fourth wire that receive the same type of signal).

[0106] Figure 9A Schematic diagram of the arrangement of wires in a pixel circuit according to another embodiment of the present disclosure. In Figure 9A In the pixel circuit 113, the wire Vini2 and the wire SN12-2 overlap at least partially in the Z direction, and the wire SN11-1 and the wire SN21-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance (e.g., 0) between the wire SN11-1 and the wire SN21-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers), or the distance between the wire SN11-1 and the wire SN22-1 (e.g., the first wire and the second wire that receive different signals or are located in different layers), or the distance between the wire Vini2 and the wire SN12-2 (e.g., the first wire and the second wire that receive different signals or are located in different layers) (e.g., 0). The distance Y2 can be the distance between the wire EM1 and the wire EM2 (e.g., the third wire and the fourth wire that receive the same type of signal).

[0107] Figure 9B Schematic diagram of the arrangement of wires in a pixel circuit according to another embodiment of the present disclosure. In Figure 9BIn the pixel circuit 113, the wire Vini1 and the wire EM1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance between the wire SN11-1 and the wire SN21-1 (for example, the first wire and the second wire that receive different signals or are located on different layers), or the distance between the wire SN11-1 and the wire SN22-1 (for example, the first wire and the second wire that receive different signals or are located on different layers), or the distance between the wire Vini1 and the wire EM1 (for example, the first wire and the second wire that receive different signals or are located on different layers) (for example, 0). The distance Y2 can be the distance between the wire SN12-1 and the wire SN12-2 (for example, the third wire and the fourth wire that receive the same type of signal).

[0108] Figure 10A Schematic diagram of the arrangement of wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 10A the pixel circuit 113, the wire Vini1 and the wire SN12-1 overlap at least partially in the Z direction, and the wire SN11-1 and the wire SN22-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance between the wire SN11-1 and the wire SN21-1 (for example, the first wire and the second wire that receive different signals or are located on different layers), or the distance between the wire SN11-1 and the wire SN22-1 (for example, the first wire and the second wire that receive different signals or are located on different layers) (for example, 0), or the distance between the wire Vini1 and the wire SN12-1 (for example, the first wire and the second wire that receive different signals or are located on different layers) (for example, 0). The distance Y2 can be the distance between the wire Vini1 and the wire Vini2 (for example, the third wire and the fourth wire that receive the same type of signal).

[0109] Figure 10B Schematic diagram of the arrangement of wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 10B the pixel circuit 113, the wire Vini1 and the wire EM1 overlap at least partially in the Z direction, and the wire SN11-1 and the wire SN22-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance between the wire SN11-1 and the wire SN21-1 (for example, the first wire and the second wire that receive different signals or are located on different layers), or the distance between the wire SN11-1 and the wire SN22-1 (for example, the first wire and the second wire that receive different signals or are located on different layers) (for example, 0), or the distance between the wire Vini1 and the wire EM1 (for example, the first wire and the second wire that receive different signals or are located on different layers) (for example, 0). The distance Y2 can be the distance between the wire SN12-1 and the wire SN12-2 (for example, the third wire and the fourth wire that receive the same type of signal).

[0110] Figure 11A Schematic diagram of the arrangement of wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 11A the pixel circuit 113, wire Vini1 and wire SN12-1 overlap at least partially in the Z direction, and wire SN11-1 and wire SN21-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance between wire SN11-1 and wire SN22-1 (for example, the first wire and the second wire receiving different signals or located on different layers), or the distance between wire SN11-1 and wire SN21-1 (for example, the first wire and the second wire receiving different signals or located on different layers) (for example, 0), or the distance between wire Vini1 and wire SN12-1 (for example, the first wire and the second wire receiving different signals or located on different layers) (for example, 0). The distance Y2 can be the distance between wire Vini1 and wire Vini2 (for example, the third wire and the fourth wire receiving the same type of signal).

[0111] Figure 11B Schematic diagram of the arrangement of wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 11B the pixel circuit 113, wire Vini1 and wire EM1 overlap at least partially in the Z direction, and wire SN11-1 and wire SN21-1 overlap at least partially in the Z direction. In this embodiment, the distance Y1 can be the distance between wire SN11-1 and wire SN22-1 (for example, the first wire and the second wire receiving different signals or located on different layers), or the distance between wire SN11-1 and wire SN21-1 (for example, the first wire and the second wire receiving different signals or located on different layers) (for example, 0), or the distance between wire Vini1 and wire EM1 (for example, the first wire and the second wire receiving different signals or located on different layers) (for example, 0). The distance Y2 can be the distance between wire SN12-1 and wire SN12-2 (for example, the third wire and the fourth wire receiving the same type of signal).

[0112] Figure 12A Schematic diagram of the arrangement of wires of a pixel circuit according to another embodiment of the present disclosure. In Figure 12AIn the pixel circuit 113, the pixel circuit 113 further includes a wire SN23-1 and a wire SN24-1, which can be formed by a conductor layer disposed under the semiconductor layer. The wires SN21-1 and SN23-1 overlap at least partially in the Z direction, and the wires SN21-1 and SN23-1 can be of different layers and are respectively coupled to the gates of the transistors T6 of the pixel circuit 113, such that the transistor T6 has the function of a dual gate, which can reduce the leakage current of the transistor T6. The wires SN22-1 and SN24-1 overlap at least partially in the Z direction, and the wires SN22-1 and SN24-1 can be of different layers and are respectively coupled to the gates of the transistors T3 of the pixel circuit 113, such that the transistor T3 has the function of a dual gate, which can reduce the leakage current of the transistor T3. Additionally, in Figure 12A it can also be seen that the wire SN11-1 overlaps at least partially with the wires SN22-1 and SN24-1 in the Z direction.

[0113] In this embodiment, the distance Y1 can be the distance between the wire SN11-1 and the wire SN21-1 (e.g., a first wire and a second wire that receive different signals or are of different layers), or the distance between the wire SN11-1 and the wire SN22-1 (e.g., a first wire and a second wire that receive different signals or are of different layers) (e.g., 0). The distance Y2 can be the distance between the wires Vini1 and Vini2 (e.g., a third wire and a fourth wire that receive the same type of signal).

[0114] Figure 12B FIG. is a schematic diagram of the arrangement of the wires of a pixel circuit according to another embodiment of the present disclosure. Figure 12B And Figure 12A is similar, and the descriptions of the wires SN21-1 and SN23-1 and the wires SN22-1 and SN24-1 can refer to the embodiment of Figure 12A and will not be repeated here. Additionally, in Figure 12B it can also be seen that the wire SN11-1 overlaps at least partially with the wires SN21-1 and SN23-1 in the Z direction. In this embodiment, the distance Y1 can be the distance between the wire SN11-1 and the wire SN21-1 (e.g., a first wire and a second wire that receive different signals or are of different layers), or the distance between the wire SN11-1 and the wire SN22-1 (e.g., a first wire and a second wire that receive different signals or are of different layers) (e.g., 0). The distance Y2 can be the distance between the wires Vini1 and Vini2 (e.g., a third wire and a fourth wire that receive the same type of signal).

[0115] Figure 13A FIG. is a schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 13BSchematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure. Figure 13C Schematic diagram of the wire arrangement of a pixel circuit according to another embodiment of the present disclosure. Figure 13A The electronic device 1300 is similar to Figure 1 the electronic device 100. Please refer to Figure 13A , Figure 13B and Figure 13C , the electronic device 1300 includes a display panel 1310, and the display panel 1310 may at least include a substrate 1311, pixels 1312 and 1313, driving circuits 120, 130 and 140. In this embodiment, the driving circuits 120, 130 and 140 are the same as or similar to Figure 1 the driving circuits 120, 130 and 140 of Figure 1 . For the description of the embodiment, please refer to Figure 1 , and details will not be repeated here. In this embodiment, the pixels 1312 and 1313 are the same as or similar to Figure 1 the pixel 112 of

[0116] Please refer to Figure 13A and Figure 13B together. The display panel 1310 includes a sensing area 1320 and a non-sensing area 1330 adjacent to the sensing area 1320, and both the sensing area 1320 and the non-sensing area 1330 are disposed on the substrate 1311. A sensing component (not shown) may be disposed below the sensing area 1320, that is, the sensing area may overlap with the sensing component. The sensing component may be, for example, an infrared sensor, a camera, a light sensor, etc., but the present disclosure is not limited thereto. The sensing area 1320 may have a relatively high transparency to improve the light signal that passes through the display panel and can be sensed by the sensing component. In addition, the non-sensing area 1330 and a part of the sensing area 1320 may be, for example, the display area of the display panel 1310.

[0117] The pixel 1312 may be disposed in the sensing area 1320 of the display panel 1310, and the pixel 1313 may be disposed in the non-sensing area 1330 of the display panel 1310. The pixel 1312 may include a pixel circuit 13121 and a light-emitting unit (not shown) coupled to the pixel circuit 13121. The pixel 1313 may include a pixel circuit 13131 and a light-emitting unit (not shown) coupled to the pixel circuit 13131. In this embodiment, the pixel circuits 13121 and 13131 are the same as or similar to Figure 2 the pixel circuit 113 of Figure 2Descriptions of the embodiments are not repeated here. The pixel circuit 13121 and the pixel circuit 13131 may each include at least a wire Vini1, a wire SN12-1, a wire EM1, a wire SN21-1, a wire SN11-1, and a wire SN22-1. In this embodiment, the wire Vini1, the wire SN12-1, the wire EM1, the wire SN21-1, the wire SN11-1, and the wire SN22-1 are the same as or similar to Figures 2 to 4 the wire Vini1, the wire SN12-1, the wire EM1, the wire SN21-1, the wire SN11-1, and the wire SN22-1, and reference can be made to Figures 2 to 4 the descriptions of the embodiments, so they are not repeated here. Similarly, the wire SN11-1, the wire SN12-1, the wire EM1, the wire Vini1, the wire Vini2 (shared with the next pixel), the wire SN21-1, and the wire SN22-1 may extend in the same direction, for example, in the X direction, but the present disclosure is not limited thereto.

[0118] In some embodiments, the wire SN11-1 may be a first wire, and the wire SN21-1 may be a second wire, but the present disclosure is not limited thereto. Additionally, in the Y direction, the distance between the wire SN11-1 and the wire SN21-1 of the pixel circuit 13121 in the sensing area 1320 may be a distance Y1-1 (e.g., a first distance), and the distance between the wire SN11-1 and the wire SN21-1 of the pixel circuit 13131 in the non-sensing area 1330 may be a distance Y1-2 (e.g., a second distance). Among them, the measurement method of the distance Y1-1 and the distance Y1-2 can refer to the embodiments of the aforementioned distances Y1 and Y2, so they are not repeated here.

[0119] In this embodiment, the distance Y1-1 and the distance Y1-2 may be different. Further, in some embodiments, the distance Y1-1 may be less than the distance Y1-2, as Figure 13B shown. Additionally, in some embodiments, as Figure 13C shown, the distance Y1-1 may also be set to be greater than the distance Y1-2. In this way, by adjusting the relationship between the distance Y1-1 and the distance Y1-2, different area ranges can be adjusted for use by sensing components (such as infrared sensors, cameras, light sensors, etc.), improving the sensing performance of the sensing components.

[0120] Figure 14A Schematic diagram of an electronic device according to another embodiment of the present disclosure. Figure 14B Schematic diagram of a display panel according to an embodiment of the present disclosure. Figure 14A the electronic device 1400 and Figure 13Ais similar to the electronic device 1300 and will not be elaborated here. The electronic device 1400 includes a display panel 1310, and the display panel 1310 may at least include a substrate 1311, pixels 1312, driving circuits 120_1, 120_2, 130_1, 130_2, and 140. The driving circuits 120_1 and 120_2 are the same as or similar to the Figure 13A driving circuit 120, the driving circuits 130_1 and 130_2 are the same as or similar to the Figure 13A driving circuit 130, and the driving circuit 140 is the same as or similar to the Figure 13A driving circuit 140. For details, please refer to the description of the embodiments in Figure 13A and will not be elaborated here.

[0121] Please refer to Figure 14A and Figure 14B collectively. The display panel 1310 includes a sensing area 1320 and a non-sensing area 1330. Sensing components such as infrared sensors, cameras, and light sensors may be provided in the sensing area 1320, but the present disclosure is not limited thereto. In addition, the non-sensing area 1330 and a part of the sensing area 1320, for example, may be the display area of the display panel 1310.

[0122] In addition, the wires SN11-1 to SN11-7 may be correspondingly coupled to the driving circuits 120_1 and 120_2. For example, the wire SN11-2 may be coupled to the driving circuit 120_1, and the wire SN11-6 may be coupled to the driving circuit 120_2, but the present disclosure is not limited thereto. The wires SN21-1 to SN21-7 may be correspondingly coupled to the driving circuits 130_1 and 130_2. For example, the wire SN21-2 may be coupled to the driving circuit 130_1, and the wire SN21-6 may be coupled to the driving circuit 130_2, but the present disclosure is not limited thereto. The wires LDAT1, LDATA2, and LVDD may be correspondingly coupled to the driving circuit 140.

[0123] Figure 15A Schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 15B is Figure 15A cross-sectional view taken along line B-B' of Figure 15A The electronic device 1500 is similar to the Figure 13A electronic device 1300 and will not be elaborated here. Please refer to Figure 15A and Figure 15B, the electronic device 1500 includes a display panel 1510, and the display panel 1510 may at least include a substrate 1511, pixels 1512 and pixels 1513. The substrate 1511 includes a sensing region 1520 and a non-sensing region 1530. The sensing region 1520 may be provided with sensing components, such as an infrared sensor, a camera, a light sensor, etc., and is disposed below the substrate 1511, but the present disclosure is not limited thereto. Additionally, the non-sensing region 1530 is, for example, the display region of the display panel 1510.

[0124] The pixel 1512 may be disposed within the sensing region 1520, and the pixel 1513 may be disposed within the non-sensing region 1530. The pixel 1512 may at least include a transistor T8, a transistor T9, and a light-emitting unit 1514, where the region 1516 is the light-emitting region of the light-emitting unit 1514. The light-emitting unit 1514 may be, for example, an organic light-emitting diode, including an upper electrode TE, a lower electrode BE, and a light-emitting layer EL located between the upper electrode TE and the lower electrode BE, but the present disclosure is not limited thereto. The transistors T8 and T9 may be partially overlapped in the Z direction and are located below the light-emitting unit 1514. In this way, the light-blocking regions in the sensing region 1520 can be reduced to improve the light transmittance, and the external light L (as shown by the arrow in Figure 15B ) can pass through the light-transmitting region of the sensing region 1520 and can be received by the sensing component. Additionally, the pixel 1513 may at least include a transistor T10, a transistor T11, and a light-emitting unit (not shown), where the region 1517 is the light-emitting region of the light-emitting unit. The transistors T10 and T11 may be respectively disposed in the Z direction, the transistors T10 and T11 may not be overlapped in the Z direction, and the transistors T10 and T11 are located below the light-emitting unit (not shown), but the present disclosure is not limited thereto.

[0125] In some embodiments, the transistors T8 and T10 are, for example, P-type or N-type thin-film transistors of an oxide semiconductor (such as indium gallium zinc oxide semiconductor), and the transistors T9 and T11 are, for example, P-type or N-type thin-film transistors of a silicon semiconductor (such as low-temperature polycrystalline silicon semiconductor), but the present disclosure is not limited thereto.

[0126] Figure 16A It is a top view of the arrangement relationship between the semiconductor layer and the wire of the display panel according to an embodiment of the present disclosure. Figure 16B is Figure 16A The cross-sectional view taken along the line C-C' of. Please refer to Figure 16A and Figure 16B, the display panel 1600 may include a semiconductor layer 1610, a semiconductor layer 1620, a wire 1630, and a wire 1640. The wire 1630 and the wire 1640 may be overlapped in the Z direction. In addition, on the substrate 1650, the semiconductor layer 1610, the wire 1630, the semiconductor layer 1620, and the wire 1640 are sequentially arranged. In this embodiment, the semiconductor layer 1610 is, for example, a silicon semiconductor (such as a low-temperature polycrystalline silicon semiconductor layer), the wire 1630 is, for example, a scan line for driving a silicon semiconductor transistor, the semiconductor layer 1620 is, for example, an oxide (such as indium gallium zinc oxide) semiconductor layer, and the wire 1640 is, for example, a scan line for driving an oxide (such as indium gallium zinc oxide) transistor, but the present disclosure is not limited thereto. Since the wire 1630 and the wire 1640 can be partially overlapped in the Z direction, the area of the light-blocking region can be reduced to improve the light transmittance.

[0127] Figure 17A A cross-sectional view of the semiconductor layer and the light-shielding layer in the sensing region and the non-sensing region of a display panel according to an embodiment of the present disclosure. Please refer to Figure 17A , the substrate 1711 includes a sensing region 1720 and a non-sensing region 1710 adjacent to the sensing region 1720. The semiconductor layer 1730, the semiconductor layer 1740, and the light-shielding layer 1731 are disposed in the non-sensing region 1710. The semiconductor layer 1750, the semiconductor layer 1760, the light-shielding layer 1751, and the light-shielding layer 1761 are disposed in the sensing region 1720. The semiconductor layer 1730 and the semiconductor layer 1740 may be disposed on different layers. The light-shielding layer 1731 may be located below the semiconductor layer 1730. The semiconductor layer 1750 and the semiconductor layer 1760 may be disposed on different layers. The light-shielding layer 1751 may be located below the semiconductor layer 1750. The light-shielding layer 1761 may be located below the semiconductor layer 1760.

[0128] In this embodiment, the semiconductor layer 1730 and the semiconductor layer 1750 are, for example, oxide semiconductor (such as indium gallium zinc oxide semiconductor) layers and are disposed on the same layer. The semiconductor layer 1740 and the semiconductor layer 1760 are, for example, silicon semiconductor (such as low-temperature polycrystalline silicon semiconductor) layers and are disposed on the same layer. The light-shielding layer 1731 and the light-shielding layer 1751 may be disposed on the same layer, and the light-shielding layer 1761 may be disposed on a different layer from the light-shielding layer 1731 and the light-shielding layer 1751. The light-shielding layer 1731, the light-shielding layer 1751, and the light-shielding layer 1761 may be a conductor layer with optical rotation shielding properties (such as a metal material) or an organic layer (such as a black matrix) or other suitable materials or a combination of the foregoing, and the present disclosure is not limited thereto.

[0129] Figure 17B A cross-sectional view of the semiconductor layer and the light-shielding layer in the sensing region and the non-sensing region of a display panel according to another embodiment of the present disclosure. Figure 17BThe display panel 1701 is similar to Figure 17A the display panel 1700, and for the same parts, reference can be made to Figure 17A the description of the embodiments in Figure 17B In

[0130] Figure 17C FIG. is a cross-sectional view showing the arrangement of the semiconductor layer and the light-shielding layer in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure. Figure 17C The display panel 1703 is similar to Figure 17A the display panel 1700, and for the same parts, reference can be made to Figure 17A the description of the embodiments in Figure 17C In

[0131] Figure 17D FIG. is a cross-sectional view showing the arrangement of the semiconductor layer and the light-shielding layer in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure. Figure 17D The display panel 1704 is similar to Figure 17C the display panel 1703, and for the same parts, reference can be made to Figure 17C the description of the embodiments in Figure 17D In

[0132] Figure 17E FIG. is a cross-sectional view showing the arrangement of the semiconductor layer and the light-shielding layer in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure. Figure 17E The display panel 1705 is similar to Figure 17D the display panel 1704, and for the same parts, reference can be made to Figure 17D the description of the embodiments in Figure 17E In

[0133] Figure 17F FIG. is a cross-sectional view showing the arrangement of the semiconductor layer and the light-shielding layer in the sensing area and the non-sensing area of a display panel according to another embodiment of the present disclosure. Figure 17F The display panel 1706 is similar toFigure 17E is similar to the display panel 1705, and for the same parts, reference can be made to Figure 17E the description of the embodiments. In Figure 17F , the wire 1752 can serve as the upper gate of the semiconductor layer 1750. When the material of the light-shielding layer 1751 is a conductive material (such as metal), it can serve as the lower gate of the semiconductor layer 1750. In addition, the wire 1752 can also be coupled to the light-shielding layer 1751 through the connection component 1780.

[0134] In the Figures 17A to 17F embodiments of the present disclosure, the distance between the light-shielding layers can be adjusted to increase the area of the display panel that is not shielded by the light-shielding layers, and this area can be provided for use by sensing components (such as infrared sensors, cameras, light sensors, etc.), but the present disclosure is not limited thereto.

[0135] In summary, for the display panel of the embodiments of the present disclosure, by arranging the first wire and the second wire of the pixel circuit adjacent to each other, and arranging the first wire and the second wire between the third wire and the fourth wire, and the first wire, the second wire, the third wire, and the fourth wire extend in the same direction, and the first distance Y1 between the first wire and the second wire and the second distance Y2 between the third wire and the fourth wire satisfy the following relationship: 0 ≦ Y1 / Y2 ≦ 0.25. In addition, in the embodiments of the present disclosure, the display panel can also have a sensing area and a non-sensing area adjacent to the sensing area. The sensing area and the non-sensing area are both arranged on the substrate, and the first wire and the second wire are arranged on the substrate and extend in the same direction. The second wire is arranged adjacent to the first wire, and the first distance between the first wire and the second wire in the sensing area is different from the second distance between the first wire and the second wire in the non-sensing area. In this way, the distance between the wires can be shortened, thereby increasing the pixel density, or some areas can be vacated for use by sensing components (such as infrared sensors, cameras, light sensors, etc.).

[0136] Although the present disclosure is disclosed as above with embodiments, it is not intended to limit the scope of the present disclosure. Any person skilled in the art can replace, reorganize, mix the features in several different embodiments, or make some adjustments, combinations, changes, and refinements without departing from the spirit and scope of the present disclosure to complete other embodiments. Therefore, the protection scope of the present disclosure shall be subject to that defined by the appended patent application scope.

[0137] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate; And A pixel circuit disposed on the substrate, wherein the pixel circuit is configured to drive a light-emitting unit, and the pixel circuit includes: A first wire and a second wire disposed adjacent to the first wire, wherein the first wire and the second wire are located in different layers; and A third wire and a fourth wire; Wherein, the first wire and the second wire are disposed between the third wire and the fourth wire; Wherein, the first wire, the second wire, the third wire and the fourth wire extend in the same first direction; Wherein, a first distance Y1 between the first wire and the second wire in a second direction and a second distance Y2 between the third wire and the fourth wire in the second direction satisfy the following relationship: 0≦Y1 / Y2≦0.25, and the second direction is perpendicular to the first direction and a normal direction of the substrate; and Wherein, the first wire is coupled to a gate of a first transistor, and the second wire is coupled to a gate of a second transistor.

2. The display panel according to claim 1, wherein The first transistor and the second transistor have different semiconductor materials.

3. The display panel according to claim 2, wherein The first wire receives a first signal, the second wire receives a second signal, and the second signal is different from the first signal.

4. The display panel according to claim 3, characterized in that, The first signal and the second signal are control signals.

5. A display panel, comprising: A substrate having a sensing region and a non-sensing region adjacent to the sensing region; A first wire and a second wire disposed on the substrate and extending in the same first direction, wherein the first wire and the second wire are located in different layers; And A third wire and a fourth wire; Wherein, the first wire and the second wire are disposed between the third wire and the fourth wire; wherein, a first distance Y1 between the first wire and the second wire in a second direction and a second distance Y2 between the third wire and the fourth wire in the second direction satisfy the following relationship: 0≦Y1 / Y2≦0.25, and the second direction is perpendicular to the first direction and a normal direction of the substrate; Wherein, the second wire is disposed adjacent to the first wire, and the first distance between the first wire and the second wire in the second direction on the sensing region is different from the first distance between the first wire and the second wire in the second direction on the non-sensing region; and Wherein, the first wire is coupled to a gate of a first transistor, and the second wire is coupled to a gate of a second transistor.

6. The display panel according to claim 5, wherein, The first distance on the sensing region is greater than the first distance on the non-sensing region.

7. The display panel according to claim 5, wherein The first distance on the sensing region is less than the first distance on the non-sensing region.

Images