Display device

Abstract

The present invention discloses a display device. The display device includes: a first pixel configured to be located in a first pixel region and configured to be connected to a first scan line; a first scan stage circuit configured to be located in a first peripheral region disposed outside the first pixel region and configured to supply a first scan signal to the first scan line; a second pixel configured to be located in a second pixel region and configured to be connected to a second scan line; and a second scan stage circuit configured to be located in a second peripheral region disposed outside the second pixel region and configured to supply a second scan signal to the second scan line. A gap between adjacent second scan stage circuits is greater than a gap between adjacent first scan stage circuits.

Description

[0001] This application is a divisional application of the patent application with the application number 201710816355.1 and the title "Display Device" filed on September 12, 2017.

[0002] Related Application

[0003] This application claims the priority and benefit of Korean Patent Application No. 10-2016-0117555, filed with the Korean Intellectual Property Office on September 12, 2016, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] An exemplary embodiment according to the present disclosure relates to a display device. Background Art

[0005] With the development of information technology, the importance of display devices for providing an interface between users and information has been highlighted. Various types of display devices, including liquid crystal display devices, organic light emitting display devices, etc., have been widely used.

[0006] A display device includes a plurality of pixels and a driver for driving the pixels.

[0007] The driver may be embedded in the display device, in which case dead zones may be formed in the display device. Summary of the Invention

[0008] Exemplary embodiments of the present disclosure are provided to provide a display device capable of effectively utilizing dead zones.

[0009] In addition, exemplary embodiments of the present disclosure are provided to provide a display device having improved uniformity.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a first pixel configured to be located in a first pixel region and configured to be connected to a first scan line; a first scan stage circuit configured to be located in a first peripheral region provided outside the first pixel region and configured to supply a first scan signal to the first scan line; a second pixel configured to be located in a second pixel region and configured to be connected to a second scan line; and a second scan stage circuit configured to be located in a second peripheral region provided outside the second pixel region and configured to supply a second scan signal to the second scan line, wherein a gap between adjacent second scan stage circuits is greater than a gap between adjacent first scan stage circuits.

[0011] In some exemplary embodiments, the second pixel region may have a width smaller than the width of the first pixel region.

[0012] In some exemplary embodiments, the gaps between adjacent second scan stage circuits may be set differently from each other according to the position.

[0013] In some exemplary embodiments, the display device may further include: dummy scan stage circuits configured to be located between adjacent second scan stage circuits.

[0014] In some exemplary embodiments, the number of dummy scan stage circuits may be set differently according to the position.

[0015] In some exemplary embodiments, the second scan stage circuits may include: a first pair of adjacent second scan stage circuits and a second pair of adjacent second scan stage circuits, and the gap between the second pair of adjacent second scan stage circuits may be greater than the gap between the first pair of adjacent second scan stage circuits.

[0016] In some exemplary embodiments, the display device may further include: at least one first dummy scan stage circuit disposed between the first pair of adjacent second scan stage circuits; and a second dummy scan stage circuit disposed between the second pair of adjacent second scan stage circuits, wherein the number of the second dummy scan stage circuits may be greater than the number of the first dummy scan stage circuits.

[0017] In some exemplary embodiments, the second pair of adjacent second scan stage circuits may be farther from the first peripheral region than the first pair of adjacent second scan stage circuits.

[0018] In some exemplary embodiments, the first pixel region may include a first sub-pixel region and a second sub-pixel region, the first peripheral region may include a first sub-peripheral region located outside the first sub-pixel region and a second sub-peripheral region located outside the second sub-pixel region, and the gap between a pair of adjacent first scan stage circuits in the second sub-peripheral region may be greater than the gap between a pair of adjacent first scan stage circuits in the first sub-peripheral region.

[0019] In some exemplary embodiments, the first sub-pixel region may be located between the second pixel region and the second sub-pixel region, and the first sub-peripheral region may be located between the second peripheral region and the second sub-peripheral region.

[0020] In some exemplary embodiments, the first scan stage circuits may be electrically connected to the first scan lines through first scan wirings, the second scan stage circuits may be electrically connected to the second scan lines through second scan wirings, and the length of the second scan wirings may be greater than the length of the first scan wirings.

[0021] In some exemplary embodiments, the display device may further include: a third pixel configured to be located in a third pixel region and configured to be connected to a third scan line; and a third scan stage circuit configured to be located in a third peripheral region outside the third pixel region and configured to supply a third scan signal to the third scan line.

[0022] In some exemplary embodiments, the third pixel region may have a width smaller than the width of the first pixel region and may be located at a position separated from the second pixel region.

[0023] In some exemplary embodiments, the gap between adjacent third scan stage circuits may be greater than the gap between adjacent first scan stage circuits.

[0024] In some exemplary embodiments, the gap between adjacent third scan stage circuits may be set differently according to position.

[0025] In some exemplary embodiments, the display device may further include: dummy scan stage circuits configured to be located between adjacent third scan stage circuits.

[0026] In some exemplary embodiments, the number of dummy scan stage circuits may be set differently according to position.

[0027] In some exemplary embodiments, the first scan stage circuit may be electrically connected to the first scan line through a first scan wiring, the second scan stage circuit may be electrically connected to the second scan line through a second scan wiring, the third scan stage circuit may be electrically connected to the third scan line through a third scan wiring, and the lengths of the second scan wiring and the third scan wiring may be greater than the length of the first scan wiring.

[0028] In some exemplary embodiments, the display device may further include: a first emission stage circuit configured to be located in a first peripheral region and configured to supply a first emission control signal to the first pixel through a first emission control line; and a second emission stage circuit configured to be located in a second peripheral region and configured to supply a second emission control signal to the second pixel through a second emission control line.

[0029] In some exemplary embodiments, the gap between adjacent second emission stage circuits may be greater than the gap between adjacent first emission stage circuits.

[0030] In some exemplary embodiments, the gap between adjacent second emission stage circuits may be set differently according to position.

[0031] In some exemplary embodiments, the display device may further include: dummy emission stage circuits configured to be located between adjacent second emission stage circuits.

[0032] In some exemplary embodiments, the number of dummy emission stage circuits may be set differently according to position.

[0033] According to an exemplary embodiment of the present disclosure, a display device capable of effectively utilizing dead angles may be provided.

[0034] In addition, according to another exemplary embodiment of the present disclosure, a display device having improved uniformity may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a diagram showing a pixel region of a display device according to an embodiment of the present disclosure.

[0036] Figure 2 is a diagram showing a display device according to an embodiment of the present disclosure.

[0037] Figure 3 is a more detailed diagram of a display device according to an embodiment of the present disclosure.

[0038] Figure 4 is Figure 3 a more detailed diagram of the illustrated scan driver and emission driver.

[0039] Figure 5 is a diagram showing a layout structure of a scan stage circuit and an emission stage circuit according to an embodiment of the present disclosure.

[0040] Figure 6A and Figure 6B is a diagram showing a layout structure of a second scan stage circuit and a second emission stage circuit according to various embodiments of the present disclosure.

[0041] Figure 7 is a diagram showing a second scan driver and a second emission driver according to another embodiment of the present disclosure.

[0042] Figure 8 is a diagram showing a layout structure of a dummy stage circuit according to an embodiment of the present disclosure.

[0043] Figure 9A and Figure 9B is a diagram showing a layout structure of a dummy stage circuit according to various embodiments of the present disclosure.

[0044] Figure 10 is a diagram showing a layout structure of a first scan stage circuit and a first emission stage circuit according to an embodiment of the present disclosure.

[0045] Figure 11 is a diagram showing a scan stage circuit according to an embodiment of the present disclosure.

[0046] Figure 12 It shows Figure 11 a waveform diagram of a driving method of the scanning stage circuit shown.

[0047] Figure 13 It is a diagram showing an emitter stage circuit according to an embodiment of the present disclosure.

[0048] Figure 14 It shows Figure 13 a waveform diagram of a driving method of the emitter stage circuit shown.

[0049] Figure 15 It is a diagram showing a pixel according to an embodiment of the present disclosure.

[0050] Figure 16 It is a diagram showing a pixel region of a display device according to another embodiment of the present disclosure.

[0051] Figure 17 It is a diagram showing a display device according to another embodiment of the present disclosure.

[0052] Figure 18 It is a more detailed diagram of a display device according to another embodiment of the present disclosure.

[0053] Figure 19 It is Figure 18 a more detailed diagram of the third scanning driver and the third emission driver shown.

[0054] Figure 20 It is a diagram showing a layout structure of a third scanning stage circuit and a third emitter stage circuit according to an embodiment of the present disclosure.

[0055] Figure 21 It is a diagram showing a layout structure of a dummy stage circuit according to an embodiment of the present disclosure. Detailed Description of the Embodiment

[0056] The specific content of this embodiment will be described with reference to the specification and the drawings.

[0057] In view of the drawings and the embodiments to be described in detail, the advantages and features of the present disclosure and the methods for realizing them will become more apparent. However, the present disclosure is not limited to the embodiments to be described below and can be implemented in various forms that are different from each other. In the case where it is described below that one unit is connected to another unit, this connection includes not only a direct connection but also an electrical connection through a certain element. In addition, in order to make the description of the present disclosure clear, parts irrelevant to the present disclosure are omitted in the drawings, and the same symbols or reference numerals are attached to similar configuration elements throughout the specification.

[0058] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the embodiments of the present disclosure and the related drawings.

[0059] Figure 1 It is a diagram showing a pixel region of a display device according to an embodiment of the present disclosure.

[0060] As Figure 1 shown, a display device 10 according to an embodiment of the present disclosure may include pixel regions AA1 and AA2 and peripheral regions NA1 and NA2.

[0061] The pixel regions AA1 and AA2 may include a plurality of pixels PXL1 and PXL2 to display a predetermined image. Accordingly, the pixel regions AA1 and AA2 may be referred to as display regions.

[0062] The peripheral regions NA1 and NA2 may include configuration elements (e.g., drivers and wires) for driving the pixels PXL1 and PXL2. The peripheral regions NA1 and NA2 may not include the pixels PXL1 and PXL2. Accordingly, the peripheral regions NA1 and NA2 may be referred to as non-display regions.

[0063] For example, the peripheral regions NA1 and NA2 may be located outside the pixel regions AA1 and AA2 and may have a shape surrounding at least a part of the pixel regions AA1 and AA2.

[0064] The pixel regions AA1 and AA2 may include a first pixel region AA1 and a second pixel region AA2.

[0065] The second pixel region AA2 may be located on one side of the first pixel region AA1 and may have an area smaller than that of the first pixel region AA1.

[0066] For example, the width W2 of the second pixel region AA2 may be set to be smaller than the width W1 of the first pixel region AA1, and the length L2 of the second pixel region AA2 may be set to be smaller than the length L1 of the first pixel region AA1.

[0067] The peripheral regions NA1 and NA2 may include a first peripheral region NA1 and a second peripheral region NA2.

[0068] The first peripheral region NA1 may be located around the first pixel region AA1 and may have a shape surrounding at least a part of the first pixel region AA1.

[0069] The width of the first peripheral region NA1 may be set to be substantially uniform along the periphery surrounding the first pixel region AA1. The width of the first peripheral region NA1 is not limited thereto and may also be set differently according to the position.

[0070] The second peripheral region NA2 may be located at the periphery of the second pixel region AA2 and may have a shape surrounding at least a part of the second pixel region AA2.

[0071] The width of the second peripheral region NA2 may be set to be substantially uniform along the periphery surrounding the second pixel region AA2. The width of the second peripheral region NA2 is not limited thereto and may be set differently according to the position.

[0072] The pixels PXL1 and PXL2 may include a first pixel PXL1 and a second pixel PXL2.

[0073] For example, the first pixel PXL1 may be located in the first pixel region AA1, and the second pixel PXL2 may be located in the second pixel region AA2.

[0074] Under the control of the driver, the pixels PXL1 and PXL2 may emit light with a predetermined luminance and may include one or more light-emitting elements (e.g., organic light-emitting diodes) for emitting light.

[0075] The pixel regions AA1 and AA2 and the peripheral regions NA1 and NA2 may be defined on the substrate 100 of the display unit 10.

[0076] The substrate 100 may be formed in various forms capable of setting the pixel regions AA1 and AA2 and the peripheral regions NA1 and NA2.

[0077] For example, the substrate 100 may include a planar base substrate 101 and an auxiliary plate 102 protruding from one end of the base substrate 101 and extending to one side.

[0078] According to one embodiment, the auxiliary plate 102 may have an area smaller than that of the base substrate 101. For example, the width of the auxiliary plate 102 may be set to be smaller than the width of the base substrate 101, and the length of the auxiliary plate 102 may be set to be smaller than the length of the base substrate 101.

[0079] The auxiliary plate 102 may have the same or a similar shape as the shape of the second pixel region AA2, but is not limited thereto and may have a shape different from the shape of the second pixel region AA2.

[0080] The substrate 100 may be made of an insulating material such as glass, resin, etc. In addition, the substrate 100 may be made of a flexible material so as to be bent or folded, and may have a single-layer structure or a multi-layer structure.

[0081] For example, the substrate 100 may include at least one of: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0082] The material constituting the substrate 100 can be variously changed and can be constituted by, for example, glass fiber reinforced plastic (FRP) or the like.

[0083] The first pixel region AA1 and the second pixel region AA2 can have various shapes. For example, each of the first pixel region AA1 and the second pixel region AA2 can have a shape such as a polygonal shape, an annular shape, or the like.

[0084] Figure 1 Exemplarily shown is a case where each of the first pixel region AA1 and the second pixel region AA2 has a quadrilateral shape.

[0085] According to one embodiment, at least a part of the first pixel region AA1 can have a curved shape.

[0086] For example, the corner of the first pixel region AA1 can have a curved shape having a predetermined curvature.

[0087] In this case, the first peripheral region NA1 can include at least a part having a curved shape so as to correspond to the curved shape of the first pixel region AA1.

[0088] According to the shape change of the first pixel region AA1, the number of the first pixels PXL1 located in one line (row or column) can be changed according to the position.

[0089] In addition, at least a part of the second pixel region AA2 can have a curved shape. For example, the corner of the second pixel region AA2 can have a curved shape having a predetermined curvature.

[0090] In this case, the second peripheral region NA2 can include at least a part having a curved shape so as to correspond to the curved shape of the second pixel region AA2.

[0091] According to the shape change of the second pixel region AA2, the number of the second pixels PXL2 located in one line (row or column) can be changed according to the position.

[0092] Figure 2 It is a diagram showing a display device according to an embodiment of the present disclosure.

[0093] As Figure 2As shown, the display unit 10 may include: a substrate 100, a first pixel PXL1, a second pixel PXL2, a first scan driver 210, a second scan driver 220, a first emission driver 310, and a second emission driver 320.

[0094] The first pixel PXL1 may be located in the first pixel region AA1 and may be connected to a first scan line S1, a first emission control line E1, and a first data line D1, respectively.

[0095] The first scan driver 210 may supply a first scan signal to the first pixel PXL1 through the first scan line S1.

[0096] For example, the first scan driver 210 may sequentially supply the first scan signal to the first scan line S1.

[0097] The first scan driver 210 may be located in the first peripheral region NA1.

[0098] For example, the first scan driver 210 may be located in the first peripheral region NA1 provided on one side (e.g., the left side as Figure 2 shown) of the first pixel region AA1.

[0099] A first scan wiring R1 may be connected between the first scan driver 210 and the first scan line S1.

[0100] Accordingly, the first scan driver 210 may be electrically connected to the first scan line S1 located in the first pixel region AA1 through the first scan wiring R1.

[0101] The first emission driver 310 may supply a first emission control signal to the first pixel PXL1 through the first emission control line E1.

[0102] For example, the first emission driver 310 may sequentially supply the first emission control signal to the first emission control line E1.

[0103] The first emission driver 310 may be located in the first peripheral region NA1.

[0104] For example, the first emission driver 310 may be located in the first peripheral region NA1 provided on one side (e.g., the left side as Figure 2 shown) of the first pixel region AA1.

[0105] Figure 2 It is shown that the first emission driver 310 is located outside the first scan driver 210. However, in another embodiment, the first emission driver 310 may be located inside the first scan driver 210.

[0106] The third emission wiring R3 can be connected between the first emission driver 310 and the first emission control line E1.

[0107] Accordingly, the first emission driver 310 can be electrically connected to the first emission control line E1 located in the first pixel region AA1 through the third emission wiring R3.

[0108] Meanwhile, if the first pixel PXL1 has a structure that does not require the first emission control signal, the first emission driver 310, the third emission wiring R3, and the first emission control line E1 can be omitted.

[0109] The second pixel PXL2 can be located in the second pixel region AA2 and can be connected to the second scan line S2, the second emission control line E2, and the second data line D2.

[0110] The second scan driver 220 can supply a second scan signal to the second pixel PXL2 through the second scan line S2.

[0111] For example, the second scan driver 220 can sequentially supply the second scan signal to the second scan line S2.

[0112] The second scan driver 220 can be located in the second peripheral region NA2.

[0113] For example, the second scan driver 220 can be located in the second peripheral region NA2 provided on one side (for example, Figure 2 the left side as shown) of the second pixel region AA2.

[0114] The second scan wiring R2 can be connected between the second scan driver 220 and the second scan line S2.

[0115] Accordingly, the second scan driver 220 can be electrically connected to the second scan line S2 located in the second pixel region AA2 through the second scan wiring R2.

[0116] The second emission driver 320 can supply a second emission control signal to the second pixel PXL2 through the second emission control line E2.

[0117] For example, the second emission driver 320 can sequentially supply the second emission control signal to the second emission control line E2.

[0118] The second emission driver 320 can be located in the second peripheral region NA2.

[0119] For example, the second emission driver 320 can be located in the second peripheral region NA2 provided on one side (for example, as Figure 2 shown on the left side) of the second pixel region AA2.

[0120] Figure 2 It is shown that the second emission driver 320 is located outside the second scan driver 220. However, in another embodiment, the second emission driver 320 may be located inside the second scan driver 220.

[0121] The fourth emission wiring R4 may be connected between the second emission driver 320 and the second emission control line E2.

[0122] Accordingly, the second emission driver 320 may be electrically connected to the second emission control line E2 located in the second pixel region AA2 through the fourth emission wiring R4.

[0123] Meanwhile, if the second pixel PXL2 has a structure that does not require the second emission control signal, the second emission driver 320, the fourth emission wiring R4, and the second emission control line E2 may be omitted.

[0124] Since the second pixel region AA2 has an area smaller than that of the first pixel region AA1, the lengths of the second scan line S2 and the second emission control line E2 may be smaller than the lengths of the first scan line S1 and the first emission control line E1.

[0125] In addition, the number of second pixels PXL2 connected to the second scan line S2 may be less than the number of first pixels PXL1 connected to the first scan line S1, and the number of second pixels PXL2 connected to the second emission control line E2 may be less than the number of first pixels PXL1 connected to the first emission control line E1.

[0126] The emission control signal may be used to control the emission times of the pixels PXL1 and PXL2. According to one embodiment, the emission control signal may be set to have a width larger than that of the scan signal.

[0127] For example, the emission control signal may be set to a gate cut-off voltage (e.g., a high-level voltage) such that the transistors included in the pixels PXL1 and PXL2 may be cut off, and the scan signal may be set to a gate turn-on voltage (e.g., a low-level voltage) such that the transistors included in the pixels PXL1 and PXL2 may be turned on.

[0128] The data driver 400 may supply data signals to the pixels PXL1 and PXL2 through the data lines D1 and D2. For example, the second data line D2 may be connected to a part of the first data line D1.

[0129] The data driver 400 may be located in the first peripheral region NA1, and specifically, may be disposed at a position that does not overlap with the first scan driver 210. For example, the data driver 400 may be located in the first peripheral region NA1 provided on the lower side of the first pixel region AA1.

[0130] The data driver 400 may be provided in various types such as chip - on - glass, chip - on - plastic, tape - automated bonding, chip - on - film, etc.

[0131] For example, the data driver 400 may be directly mounted on the substrate 100, or may be connected to the substrate 100 through other components (e.g., flexible printed circuit board).

[0132] Meanwhile, although not shown in Figure 2 the display unit 10 may further include a timing controller that provides a predetermined signal to the scan drivers 210 and 220, the emission drivers 310 and 320, and the data driver 400.

[0133] Figure 3 is a more detailed diagram of a display device according to an embodiment of the present disclosure.

[0134] The first scan driver 210 may supply a first scan signal to the first pixels PXL1 through the first scan wirings R11 to R1k and the first scan lines S11 to S1k.

[0135] The first scan wirings R11 to R1k may be connected between the output terminals of the first scan driver 210 and the first scan lines S11 to S1k.

[0136] For example, the first scan wirings R11 to R1k and the first scan lines S11 to S1k may be located in different layers from each other, and in this case, they may be connected to each other through contact holes (not shown).

[0137] The first emission driver 310 may supply a first emission control signal to the first pixels PXL1 through the first emission wirings R31 to R3k and the first emission control lines E11 to E1k.

[0138] The first emission wirings R31 to R3k may be connected between the output terminals of the first emission driver 310 and the first emission control lines E11 to E1k.

[0139] For example, the first emission wirings R31 to R3k and the first emission control lines E11 to E1k may be located in different layers from each other, and in this case, they may be connected to each other through contact holes (not shown).

[0140] The first scan driver 210 and the first emission driver 310 may operate in response to the first scan control signal SCS1 and the first emission control signal ECS1, respectively.

[0141] The data driver 400 may supply data signals to the first pixels PXL1 through the first data lines D11 to D1o.

[0142] The first pixel PXL1 can be connected to a first pixel power supply ELVDD and a second pixel power supply ELVSS. If necessary, the first pixel PXL1 can be further connected to an initialization power supply Vint.

[0143] When a first scan signal is supplied to the first scan lines S11 to S1k, the first pixel PXL1 can receive a data signal from the first data lines D11 to D1o, and the first pixel PXL1 that has received the data signal can control the current flowing from the first pixel power supply ELVDD through an organic light emitting diode (not shown) to the second pixel power supply ELVSS.

[0144] In addition, the number of the first pixels PXL1 located in one line (row or column) can be changed according to the position.

[0145] The second scan driver 220 can supply a second scan signal to the second pixel PXL2 through second scan wirings R21 to R2j and second scan lines S21 to S2j.

[0146] The second scan wirings R21 to R2j can be connected between the output terminals of the second scan driver 220 and the second scan lines S21 to S2j.

[0147] For example, the second scan wirings R21 to R2j and the second scan lines S21 to S2j can be located in different layers from each other, and in this case, they can be connected to each other through contact holes (not shown).

[0148] The second emission driver 320 can supply a second emission control signal to the second pixel PXL2 through second emission wirings R41 to R4j and second emission control lines E21 to E2j.

[0149] The second emission path wirings R41 to R4j can be connected between the output terminals of the second emission driver 320 and the second emission control lines E21 to E2j.

[0150] For example, the second emission wirings R41 to R4j and the second emission control lines E21 to E2j can be located in different layers from each other, and in this case, they can be connected to each other through contact holes (not shown).

[0151] The second scan driver 220 and the second emission driver 320 can operate respectively in response to a second scan control signal SCS2 and a second emission control signal ECS2.

[0152] The data driver 400 can supply a data signal to the second pixel PXL2 through second data lines D21 to D2p.

[0153] For example, the second data lines D21 to D2p may be connected to a partial subset of the first data lines, and in the present embodiment, may be connected to the first data lines D11 to D1m-1.

[0154] In addition, the second pixel PXL2 may be connected to the first pixel power supply ELVDD and the second pixel power supply ELVSS. If necessary, the second pixel PXL2 may be further connected to the initialization power supply Vint.

[0155] When the second scan signals are supplied to the second scan lines S21 to S2j, the second pixel PXL2 may receive data signals from the second data lines D21 to D2p, and the second pixel PXL2 that has received the data signal may control the current flowing from the first pixel power supply ELVDD through an organic light emitting diode (not shown) to the second pixel power supply ELVSS.

[0156] In addition, the number of the second pixels PXL2 located in one line (row or column) may vary according to the position.

[0157] The data driver 400 may operate in response to a data control signal DCS.

[0158] Since the second pixel region AA2 has an area smaller than the area of the first pixel region AA1, the number of the second pixels PXL2 may be less than the number of the first pixels PXL1, and the lengths and numbers of the second scan lines S21 to S2j and the second emission control lines E21 to E2j may be respectively set to be less than the lengths and numbers of the first scan lines S11 to S1k and the first emission control lines E11 to E1k.

[0159] The number of the second pixels PXL2 connected to any one of the second scan lines S21 to S2j may be less than the number of the first pixels PXL1 connected to any one of the first scan lines S11 to S1k.

[0160] In addition, the number of the second pixels PXL2 connected to any one of the second emission control lines E21 to E2j may be less than the number of the first pixels PXL1 connected to any one of the first emission control lines E11 to E1k.

[0161] The timing controller 270 may control the first scan driver 210, the second scan driver 220, the data driver 400, the first emission driver 310, and the second emission driver 320.

[0162] The timing controller 270 can supply a first scan control signal SCS1 and a second scan control signal SCS2 to the first scan driver 210 and the second scan driver 220, respectively, and can supply a first emission control signal ECS1 and a second emission control signal ECS2 to the first emission driver 310 and the second emission driver 320, respectively.

[0163] Each of the scan control signals SCS1 and SCS2 and the emission control signals ECS1 and ECS2 can include at least one clock signal and a start pulse.

[0164] The start pulse can control the timing of the first scan signal or the first emission control signal. The clock signal can be used to shift the start pulse.

[0165] According to one embodiment, the timing controller 270 can supply a data control signal DCS to the data driver 400.

[0166] The data control signal DCS can include a source start pulse and at least one clock signal. The source start pulse can be used to control the sampling start time point of the data, and the clock signal can be used to control the sampling operation.

[0167] Figure 4 Yes Figure 3 A more detailed diagram of the scan driver and the emission driver shown.

[0168] The first scan driver 210 can include a plurality of first scan stage circuits SST11 to SST1k.

[0169] Each of the first scan stage circuits SST11 to SST1k can be connected to corresponding terminals of the first scan wirings R11 to R1k, and can supply a first scan signal to the first scan lines S11 to S1k.

[0170] The first scan stage circuits SST11 to SST1k can operate in response to the clock signals CLK1 and CLK2 supplied from the timing controller 270. According to one embodiment, the first scan stage circuits SST11 to SST1k can be implemented by the same circuit.

[0171] The first scan stage circuits SST11 to SST1k can receive the output signal (i.e., the scan signal) of the previous scan stage circuit or the first start pulse SSP1.

[0172] For example, the first circuit SST11 in the first scan stage circuit can receive the first start pulse SSP1, and the other circuits SST12 to SST1k in the first scan stage circuit can receive the output signal of the previous scan stage circuit.

[0173] In another embodiment, the first circuit SST11 in the first scan stage circuit of the first scan driver 210 may use the signal output from the last scan stage circuit SST2j of the second scan driver 220 as a start pulse.

[0174] The first scan stage circuits SST11 to SST1k may receive the first driving power supply VDD1 and the second driving power supply VSS1, respectively.

[0175] Here, the first driving power supply VDD1 may be set to a gate cut-off voltage, such as a high-level voltage. In addition, the second driving power supply VSS1 may be set to a gate conduction voltage, such as a low-level voltage.

[0176] The second scan driver 220 may include a plurality of second scan stage circuits SST21 to SST2j.

[0177] Each of the second scan stage circuits SST21 to SST2j may be connected to corresponding terminals of the second scan wirings R21 to R2j, and may supply second scan signals to the second scan lines S21 to S2j.

[0178] The second scan stage circuits SST21 to SST2j may operate in response to the clock signals CLK1 and CLK2 supplied from the timing controller 270. According to one embodiment, the second scan stage circuits SST21 to SST2j may be implemented by the same circuit.

[0179] The second scan stage circuits SST21 to SST2j may receive the output signal (i.e., scan signal) of the previous scan stage circuit or the second start pulse SSP2.

[0180] For example, the first circuit SST21 in the second scan stage circuit may receive the second start pulse SSP2, and the other circuits SST22 to SST2j in the second scan stage circuit may receive the output signal of the previous scan stage circuit.

[0181] According to one embodiment, the last scan stage circuit SST2j of the second scan driver 220 may supply an output signal to the first circuit SST11 of the first scan driver 210.

[0182] The second scan stage circuits SST21 to SST2j may receive the first driving power supply VDD1 and the second driving power supply VSS1, respectively.

[0183] The first clock line 241 and the second clock line 242 may be connected to the first scan driver 210 and the second scan driver 220.

[0184] According to an embodiment, the first clock line 241 and the second clock line 242 may be connected to the timing controller 270, and may transmit the first clock signal CLK1 and the second clock signal CLK2 supplied from the timing controller 270 to the first scan driver 210 and the second scan driver 220.

[0185] The first clock line 241 and the second clock line 242 may be disposed in the first peripheral area NA1 and the second peripheral area NA2.

[0186] The first clock signal CLK1 and the second clock signal CLK2 may have different phases from each other. For example, the second clock signal CLK2 may have a phase difference of 180 degrees with respect to the first clock signal CLK1.

[0187] Figure 4 The case where the first scan driver 210 and the second scan driver 220 share the same clock lines 241 and 242 is shown, but the present disclosure is not limited thereto, and the first scan driver 210 and the second scan driver 220 may be respectively connected to mutually separate clock lines.

[0188] In addition, Figure 4 The case where the scan drivers 210 and 220 respectively use two clock signals CLK1 and CLK2 is shown, but the number of clock signals used by the scan drivers 210 and 220 may be changed according to the structure of the scan stage circuit.

[0189] The first emission driver 310 may include a plurality of first emission stage circuits (abbreviated as first emission stages) EST11 to EST1k.

[0190] Each of the first emission stage circuits EST11 to EST1k may be connected to corresponding terminals of the first emission wirings R31 to R3k, and may supply a first emission control signal to the first emission control lines E11 to E1k.

[0191] The first emission stage circuits EST11 to EST1k may operate in response to the clock signals CLK3 and CLK4 supplied from the timing controller 270. According to an embodiment, the first emission stage circuits EST11 to EST1k may be implemented by the same circuit.

[0192] The first emission stage circuits EST11 to EST1k may receive an output signal (i.e., an emission control signal) of a previous emission stage circuit or a third start pulse SSP3.

[0193] For example, the first circuit EST11 of the first emission stage circuits may receive the third start pulse SSP3, and the other circuits EST12 to EST1k of the first emission stage circuits may receive an output signal of a previous emission stage circuit.

[0194] In another embodiment, the first circuit EST11 in the first emission stage circuit of the first emission driver 310 may use the signal output from the last emission stage circuit EST2j of the second emission driver 320 as a start pulse.

[0195] The first emission stage circuits EST11 to EST1k may receive a third drive power supply VDD2 and a fourth drive power supply VSS2, respectively.

[0196] Here, the third drive power supply VDD2 may be set to a gate cut-off voltage, such as a high-level voltage. In addition, the fourth drive power supply VSS2 may be set to a gate conduction voltage, such as a low-level voltage.

[0197] According to one embodiment, the third drive power supply VDD2 may have the same voltage as the first drive power supply VDD1, and the fourth drive power supply VSS2 may have the same voltage as the second drive power supply VSS1.

[0198] The second emission driver 320 may include a plurality of second emission stage circuits (abbreviated as second emission stages) EST21 to EST2j.

[0199] Each of the second emission stage circuits EST21 to EST2j may be connected to corresponding terminals of the second emission wirings R41 to R4j, and may supply a second emission control signal to the second emission control lines E21 to E2j.

[0200] The second emission stage circuits EST21 to EST2j may operate in response to clock signals CLK3 and CLK4 supplied from the timing controller 270. According to one embodiment, the second emission stage circuits EST21 to EST2j may be implemented by the same circuit.

[0201] The second emission stage circuits EST21 to EST2j may receive an output signal (i.e., an emission control signal) of a previous emission stage circuit or a fourth start pulse SSP4.

[0202] For example, the first circuit EST21 in the second emission stage circuit may receive the fourth start pulse SSP4, and the other circuits EST22 to EST2j in the second emission stage circuit may receive an output signal of a previous emission stage circuit.

[0203] According to one embodiment, the last emission stage circuit EST2j of the second emission driver 320 may supply an output signal to the first circuit EST11 of the first emission driver 310.

[0204] The second emission stage circuits EST21 to EST2j may respectively receive a third driving power supply VDD2 and a fourth driving power supply VSS2.

[0205] The third clock line 243 and the fourth clock line 244 may be connected to the first emission driver 310 and the second emission driver 320.

[0206] According to one embodiment, the third clock line 243 and the fourth clock line 244 may be connected to the timing controller 270, and may transmit the third clock signal CLK3 and the fourth clock signal CLK4 supplied from the timing controller 270 to the first emission driver 310 and the second emission driver 320.

[0207] The third clock line 243 and the fourth clock line 244 may be disposed in the first peripheral region NA1 and the second peripheral region NA2.

[0208] The third clock signal CLK3 and the fourth clock signal CLK4 may have phases different from each other. For example, the third clock signal CLK3 may have a phase difference of 180 degrees with respect to the fourth clock signal CLK4.

[0209] Figure 4 The case where the first emission driver 310 and the second emission driver 320 share the same clock lines 243 and 244 is shown, but the present disclosure is not limited thereto, and the first emission driver 310 and the second emission driver 320 may be respectively connected to separate clock lines.

[0210] In addition, Figure 4 The emission drivers 310 and 320 are shown to respectively use two clock signals CLK3 and CLK4, but the number of clock signals used by the emission drivers 310 and 320 may be changed according to the structure of the emission stage circuit.

[0211] Figure 5 is a diagram showing a layout structure of a scan stage circuit and an emission stage circuit according to an embodiment of the present disclosure.

[0212] Specifically, Figure 5 Exemplarily shown are a part of the first scan stage circuits SST11 to SST16 and a part of the first emission stage circuits EST11 to EST16 disposed in the first peripheral region NA1, and a part of the second scan stage circuits SST21 to SST210 and a part of the second emission stage circuits EST21 to EST210 disposed in the second peripheral region NA2.

[0213] As Figure 5 shown, the corner of the second peripheral region NA2 may have a curved shape. For example, as Figure 5As shown, the area in the second peripheral region NA2 where the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210 are provided may have a curved shape with a predetermined curvature.

[0214] The corners of the second pixel region AA2 corresponding to the curved shape of the second peripheral region NA2 may also have a curved shape.

[0215] In order for the corners of the second pixel region AA2 to have a curved shape, the farther the pixel rows in the second pixel region AA2 are from the first pixel region AA1, the fewer the number of pixels PXL2 that the row may include.

[0216] The farther the pixel rows arranged in the second pixel region AA2 are from the first pixel region AA1, the smaller the length of the row. The length may not need to be reduced in the same proportion, and the number of second pixels PXL2 included in each pixel row may be changed differently according to the curvature of the curve forming the corners of the second pixel region AA2.

[0217] The first peripheral region NA1 may have a linear shape, and in this case, the first pixel region AA1 may have a quadrilateral shape.

[0218] All pixel rows in the first pixel region AA1 may include the same number of first pixels PXL1.

[0219] Different from the first peripheral region NA1, the second peripheral region NA2 has a curved shape. Therefore, the layout structures of the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210 in the second peripheral region NA2 may be set to be different from the layout structures of the first scan stage circuits SST11 to SST16 and the first emission stage circuits EST11 to EST16 in the first peripheral region NA1 in order to effectively use the second peripheral region NA2 that may be a dead corner.

[0220] For example, the gap P2 between adjacent second scan stage circuits SST21 to SST210 may be set to be greater than the gap P1 between adjacent first scan stage circuits SST11 to SST16.

[0221] The gap P1 between adjacent first scan stage circuits SST11 to SST16 may be set to a constant.

[0222] In addition, the gap P2 between adjacent second scan stage circuits SST21 to SST210 may be set to be different from each other according to the position.

[0223] For example, the gap P2a between a pair of second scan stage circuits SST23 and SST24 can be set to be different from the gap P2b between a pair of second scan stage circuits SST21 and SST22.

[0224] Specifically, the gap P2b between a pair of second scan stage circuits SST21 and SST22 can be set to be larger than the gap P2a between a pair of second scan stage circuits SST23 and SST24.

[0225] In this example, compared with a pair of second scan stage circuits SST23 and SST24, a pair of second scan stage circuits SST21 and SST22 can be located farther from the first peripheral region NA1.

[0226] In other words, the farther the gap P2 between adjacent second scan stage circuits SST21 to SST210 is from the first peripheral region NA1, the larger the gap P2 can become.

[0227] In addition, compared with the first scan stage circuits SST11 to SST16, the second scan stage circuits SST21 to SST210 can have a predetermined slope. For example, the farther the second scan stage circuits SST21 to SST210 are from the first peripheral region NA1, the larger the slope can become.

[0228] Meanwhile, the second emission stage EST21 to EST210 can be set in a manner substantially similar to that of the second scan stage circuits SST21 to SST210.

[0229] For example, the gap P4 between adjacent second emission stage EST21 to EST210 can be set to be larger than the gap P3 between adjacent first emission stage circuits EST11 to EST16.

[0230] For example, the gap P3 between adjacent first emission stage circuits EST11 to EST16 can be a constant.

[0231] In addition, the gap P4 between adjacent second emission stage EST21 to EST210 can be set to be different from each other according to the position.

[0232] For example, the gap P4a between a pair of second emission stage EST23 and EST24 can be set to be different from the gap P4b between a pair of second emission stage EST21 and EST22.

[0233] Specifically, the gap P4b between a pair of second emission stage EST21 and EST22 can be set to be larger than the gap P4a between a pair of second emission stage EST23 and EST24.

[0234] In this example, compared with a pair of second emitters EST23 and EST24, a pair of second emitters EST21 and EST22 can be located farther from the first peripheral region NA1.

[0235] In other words, the farther the gap P4 between adjacent second emitters EST21 to EST210 is from the first peripheral region NA1, the larger the gap P4 can become.

[0236] Compared with the first emitter circuits EST11 to EST16, the second emitter circuits EST21 to EST210 can have a predetermined slope. For example, the farther the second emitter circuits EST21 to EST210 are from the first peripheral region NA1, the larger the slope can become.

[0237] The first scan stage circuits SST11 to SST16 can be electrically connected to the first scan lines S11 to S16 through the first scan wirings R11 to R16, and the second scan stage circuits SST21 to SST210 can be electrically connected to the second scan lines S21 to S210 through the second scan wirings R21 to R210.

[0238] In this case, since the corners of the second pixel region AA2 are set to have a curved shape, the lengths of the second scan wirings R21 to R210 can be set to be greater than the lengths of the first scan wirings R11 to R16.

[0239] According to one embodiment, the connection points between the first scan wirings R11 to R16 and the first scan lines S11 to S16 can be located within the first pixel region AA1, and the connection points between the second scan wirings R21 to R210 and the second scan lines S21 to S210 can be located within the second pixel region AA2.

[0240] In addition, the first emitter circuits EST11 to EST16 can be electrically connected to the first emission control lines E11 to E16 through the first emission wirings R31 to R36, and the second emitters EST21 to EST210 can be electrically connected to the second emission control lines E21 to E210 through the second emission wirings R41 to R410.

[0241] In this case, since the corners of the second pixel region AA2 are set to have a curved shape, the lengths of the second emission wirings R41 to R410 can be set to be greater than the lengths of the first emission wirings R31 to R36.

[0242] According to one embodiment, the connection points between the first emission wirings R31 to R36 and the first emission control lines E11 to E16 may be located within the first pixel region AA1, and the connection points between the second emission wirings R41 to R410 and the second emission control lines E21 to E210 may be located within the second pixel region AA2.

[0243] Figure 6A and Figure 6B FIGS. Figure 6B and are diagrams showing the layout structures of a second scan stage circuit and a second emission stage circuit according to various embodiments of the present disclosure.

[0244] Specifically, for convenience, Figure 6A and 6B FIG. 6B shows second scan stage circuits SST21 to SST210 and second emission stage circuits EST21 to EST210 provided in the second peripheral region NA2.

[0245] As Figure 6A shown, the gaps P21, P22, and P23 between adjacent second scan stage circuits SST21 to SST210 may be set differently from each other by groups SG1, SG2, and SG3.

[0246] For example, the second scan stage circuits SST27 to SST210 included in the first group SG1 may be set with a first gap P21 therebetween, the second scan stage circuits SST24 to SST26 included in the second group SG2 may be set with a second gap P22 therebetween, and the second scan stage circuits SST21 to SST23 included in the third group SG3 may be set with a third gap P23 therebetween.

[0247] In this case, the first gap P21, the second gap P22, and the third gap P23 may be set differently from each other.

[0248] For example, the first gap P21, the second gap P22, and the third gap P23 may have larger values in ascending order.

[0249] In addition, the gaps P41, P42, and P43 between adjacent second emission stage circuits EST21 to EST210 may be set differently from each other by groups EG1, EG2, and EG3.

[0250] For example, the second emission stage circuits EST27 to EST210 included in the first group EG1 may be set with a first gap P41 therebetween, the second emission stage circuits EST24 to EST26 included in the second group EG2 may be set with a second gap P42 therebetween, and the second emission stage circuits EST21 to EST23 included in the third group EG3 may be set with a third gap P43 therebetween.

[0251] In this case, the first gap P41, the second gap P42, and the third gap P43 can be set differently from each other.

[0252] For example, the first gap P41, the second gap P42, and the third gap P43 can have larger values in ascending order.

[0253] As Figure 6B shown, the gap P2 between adjacent second scan stage circuits SST21 to SST210 can gradually increase.

[0254] For example, the closer the gap P2 between adjacent second scan stage circuits SST21 to SST210 is to one side (e.g., the upper side as Figure 6B shown), the larger the gap P2 can become.

[0255] Accordingly, the gaps P2 adjacent to each other can be set differently from each other.

[0256] In addition, the gap P4 between adjacent second emission stage circuits EST21 to EST210 can gradually increase.

[0257] For example, the closer the gap P4 between adjacent second emission stage circuits EST21 to EST210 is to one side (e.g., the upper side as Figure 6B shown), the larger the gap P4 can become.

[0258] Accordingly, the gaps P4 adjacent to each other can be set differently from each other.

[0259] Figure 7 FIG. is a diagram showing a second scan driver and a second emission driver according to another embodiment of the present disclosure.

[0260] As Figure 7 shown, the second scan driver 220' may further include one or more dummy scan stage circuits DSST.

[0261] Since the dummy scan stage circuit DSST is located between the second scan stage circuits SST21 to SST2j, the critical dimension (CD) uniformity of the second scan driver 220' can be increased.

[0262] For example, the dummy scan stage circuit DSST may be located between the second scan stage circuits SST21 to SST2j, and the number of dummy scan stage circuits DSST can be set differently according to the position.

[0263] The dummy scan stage circuit DSST may have the same circuit structure as the second scan stage circuits SST21 to SST2j, but is not connected to the clock lines 241 and 242, so as not to perform the output operation of the scan signal.

[0264] Meanwhile, the second emission driver 320' may further include one or more dummy emission stage circuits DEST.

[0265] The dummy emission stage circuits DEST are located between the second emission stage circuits EST21 to EST2j, and can improve the CD uniformity of the second emission driver 320'.

[0266] For example, the dummy emission stage circuits DEST may be located between the second emission stage circuits EST21 to EST2j, and the number of the dummy emission stage circuits DEST may be set differently according to the position.

[0267] The dummy emission stage circuits DEST may have the same circuit structure as the second emission stage circuits EST21 to EST2j, but are not connected to the clock lines 243 and 244, so as not to perform the output operation of the emission control signal.

[0268] Figure 8 FIG. is a diagram showing the layout structure of the dummy stage circuit according to an embodiment of the present disclosure.

[0269] Specifically, Figure 8 shows setting the shapes of the dummy stage circuits DSST and DEST in the circuit as Figure 5 shown.

[0270] As Figure 8 shown, the dummy scan stage circuit DSST may be set in the second peripheral area NA2 and may be located between the second scan stage circuits SST21 to SST210.

[0271] Figure 8 FIG. shows a case where the dummy scan stage circuit DSST is partially located between the second scan stage circuits SST21 to SST25.

[0272] The number of the dummy scan stage circuits DSST may be changed according to the position.

[0273] For example, the number of the dummy scan stage circuits DSST located between a pair of second scan stage circuits SST23 and SST24 may be different from the number of the dummy scan stage circuits DSST located between a pair of second scan stage circuits SST21 and SST22.

[0274] Specifically, the number of dummy scan stage circuits DSST located between a pair of second scan stage circuits SST21 and SST22 can be set to be more than the number of dummy scan stage circuits DSST located between a pair of second scan stage circuits SST23 and SST24.

[0275] In this example, compared with a pair of second scan stage circuits SST23 and SST24, a pair of second scan stage circuits SST21 and SST22 can be located farther from the first peripheral region NA1.

[0276] Meanwhile, the dummy emission stage circuit DEST can be disposed in the second peripheral region NA2 and can be located between adjacent second emission stages EST21 to EST210.

[0277] Figure 8 The case where the dummy emission stage circuit DEST is partially located between the second emission stages EST21 to EST25 is shown.

[0278] The number of dummy emission stage circuits DEST can be changed according to the position.

[0279] For example, the number of dummy emission stage circuits DEST located between a pair of second emission stage circuits EST23 and EST24 can be different from the number of dummy emission stage circuits DEST located between a pair of second emission stage circuits EST21 and EST22.

[0280] Specifically, the number of dummy emission stage circuits DEST located between a pair of second emission stage circuits EST21 and EST22 can be set to be more than the number of dummy emission stage circuits DEST located between a pair of second emission stage circuits EST23 and EST24.

[0281] In this example, compared with a pair of second emission stage circuits EST23 and EST24, a pair of second emission stage circuits EST21 and EST22 can be located farther from the first peripheral region NA1.

[0282] Meanwhile, although not shown separately, the dummy scan stage circuit DSST and the dummy emission stage circuit DEST can be additionally provided in various forms in Figure 6A and 6B the embodiments shown.

[0283] Figure 9A and Figure 9B are diagrams showing the layout structures of the dummy stage circuits according to various embodiments of the present disclosure.

[0284] Specifically, for convenience, Figure 9A and Figure 9BShows the second scan stage circuits SST21 to SST210, dummy scan stage circuit DSST, second emission stage circuits EST21 to EST210, and dummy emission stage circuit DEST provided in the second peripheral region NA2.

[0285] As Figure 9A shown, the second scan stage circuits SST21 to SST210 and the dummy scan stage circuit DSST may be located outside the second emission stage circuits EST21 to EST210 and the dummy emission stage circuit DEST.

[0286] For example, Figure 8 compared with, the positions of the second scan stage circuits SST21 to SST210 may be replaced with the positions of the second emission stage circuits EST21 to EST210, and the position of the dummy scan stage circuit DSST may be replaced with the position of the dummy emission stage circuit DEST.

[0287] According to this layout structure, compared with the second scan stage circuits SST21 to SST210 and the dummy scan stage circuit DSST, the second emission stage circuits EST21 to EST210 and the dummy emission stage circuit DEST may be located closer to the second pixel region AA2.

[0288] As Figure 9B shown, the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210 may be placed along the same line.

[0289] For example, Figure 9A in which the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210 are provided on different lines, but the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210 may be provided on the same line.

[0290] In this case, the second scan stage circuits SST21 to SST210 may be inserted between the second emission stage circuits EST21 to EST210.

[0291] In addition, the dummy scan stage circuit DSST and the dummy emission stage circuit DEST may be provided in various types between the second scan stage circuits SST21 to SST210 and the second emission stage circuits EST21 to EST210.

[0292] Figure 10 Is a diagram showing the layout structure of the first scan stage circuit and the first emission stage circuit according to an embodiment of the present disclosure.

[0293] As Figure 10As shown, the first pixel region AA1 may include a first sub-pixel region SAA1 and a second sub-pixel region SAA2.

[0294] In addition, the first peripheral region NA1 may include a first sub-peripheral region SNA1 and a second sub-peripheral region SNA2.

[0295] The first sub-peripheral region SNA1 may be located outside the first sub-pixel region SAA1, and the second sub-peripheral region SNA2 may be located outside the second sub-pixel region SAA2.

[0296] For example, the first sub-pixel region SAA1 may be located between the second pixel region AA2 (not shown) and the second sub-pixel region SAA2, and the first sub-peripheral region SNA1 may be located between the second peripheral region NA2 (not shown) and the second sub-peripheral region SNA2.

[0297] The corner of the second sub-peripheral region SNA2 may have a curved shape. For example, the second sub-peripheral region SNA2 may include part of the first scan stage circuits SSTli+4 to SSTli+10 and part of the first emission stage circuits ESTli+4 to ESTli+10.

[0298] The corner of the second sub-pixel region SAA2 corresponding to the corner of the second sub-peripheral region SNA2 may also have a curved shape.

[0299] In order to make the corner of the second sub-pixel region SAA2 have a curved shape, the farther the pixel row in the second sub-pixel region SAA2 is from the first sub-pixel region SAA1, the fewer the number of pixels PXL1 may be set.

[0300] The farther the pixel row arranged in the second sub-pixel region SAA2 is from the first sub-pixel region SAA1, the smaller the length of that row. The length of the row may not need to be reduced in the same proportion, and the number of pixels PXL1 included in each pixel row may be changed differently according to the curvature of the curve forming the corner of the second sub-pixel region SAA2.

[0301] The first sub-peripheral region SNA1 may have a straight shape, and in this case, the first sub-pixel region SAA1 has a quadrilateral shape.

[0302] According to this layout structure, all pixel rows in the first sub-pixel region SAA1 may include the same number of pixels PXL1.

[0303] For example, the first sub-peripheral region SNA1 may include part of the first scan stage circuits SSTli to SSTli+3 and part of the first emission stage circuits ESTli to ESTli+3.

[0304] Unlike the first sub-peripheral region SNA1, the second sub-peripheral region SNA2 has a curved shape. Therefore, the layout structure of the stage circuit can be set differently from that of the first sub-peripheral region SNA1.

[0305] For example, the gap P5 between adjacent first scan stage circuits SSTli+4 to SSTli+10 can be set to be larger than the gap P6 between adjacent first scan stage circuits SSTli to SSTli+3.

[0306] For example, the gap P6 between adjacent first scan stage circuits SSTli to SSTli+3 located in the first sub-peripheral region SNA1 can be set to a constant.

[0307] In addition, the gaps P5 between adjacent first scan stage circuits SSTli+4 to SSTli+10 located in the second sub-peripheral region SNA2 can be set to be different from each other according to the position.

[0308] The gaps P5 between adjacent first scan stage circuits SSTli+4 to SSTli+10 located in the second sub-peripheral region SNA2 can be restricted according to the presence of the data line D. In this case, the gaps P5 between adjacent first scan stage circuits SSTli+4 to SSTli+10 located in the second sub-peripheral region SNA2 can be set to be smaller than Figure 5 and Figure 6B the gap P2 between adjacent second scan stage circuits SST21 to SST210 shown.

[0309] However, the present disclosure is not limited thereto, and the gaps P5 between adjacent first scan stage circuits SSTli+4 to SSTli+10 located in the second sub-peripheral region SNA2 can be set to be equal to or larger than Figure 5 and Figure 6B the gap P2 between adjacent second scan stage circuits SST21 to SST210 shown.

[0310] In addition, according to one embodiment, one or more dummy scan stage circuits DSST can also be located between adjacent first scan stage circuits SSTli+4 to SSTli+10 provided in the second sub-peripheral region SNA2.

[0311] Meanwhile, the gap P7 between adjacent first emission stage circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2 can be set to be larger than the gap P8 between adjacent first emission stage circuits ESTli to ESTli+3 located in the first sub-peripheral region SNA1.

[0312] For example, the gap P8 between adjacent first emitter circuits ESTli to ESTli+3 located in the first sub-peripheral region SNA1 can be set to a constant value.

[0313] In addition, the gaps P7 between adjacent first emitter circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2 can be set to be different from each other according to their positions.

[0314] The gaps P7 between adjacent first emitter circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2 can be restricted only based on the presence of the data line D. In this case, the gaps P7 between adjacent first emitter circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2 can be set to be smaller than Figure 5 and Figure 6B the gap P4 between adjacent second emitters EST21 to EST210 as shown.

[0315] However, the present disclosure is not limited thereto, and the gaps P7 between adjacent first emitter circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2 can be set to be equal to or greater than Figure 5 and Figure 6B the gap P4 between adjacent second emitters EST21 to EST210 as shown.

[0316] In addition, according to one embodiment, one or more dummy emitter circuits DEST can also be provided between adjacent first emitter circuits ESTli+4 to ESTli+10 located in the second sub-peripheral region SNA2.

[0317] Figure 11 FIG. is a diagram showing a scan stage circuit according to an embodiment of the present disclosure.

[0318] For convenience, Figure 11 the scan stage circuits SST11 and SST12 of the first scan driver 210 are shown.

[0319] As Figure 11 shown, the first first scan stage circuit SST11 can include a first drive circuit 1210, a second drive circuit 1220, and an output unit 1230.

[0320] The output unit 1230 can control the voltage supplied to the output terminal 1006 in response to the voltages of the first node N1 and the second node N2. The output unit 1230 can include a fifth transistor M5 and a sixth transistor M6.

[0321] The fifth transistor M5 may be connected between the fourth input terminal 1004 to which the first driving power supply VDD1 is input and the output terminal 1006, and the gate electrode of the fifth transistor M5 may be connected to the first node N1. The fifth transistor M5 may control the connection between the fourth input terminal 1004 and the output terminal 1006 in response to the voltage applied to the first node N1.

[0322] The sixth transistor M6 may be connected between the output terminal 1006 and the third input terminal 1003, and the gate electrode of the sixth transistor M6 may be connected to the second node N2. The sixth transistor M6 may control the connection between the output terminal 1006 and the third input terminal 1003 in response to the voltage applied to the second node N2.

[0323] The output unit 1230 may be driven to act as a buffer. In addition, the fifth transistor M5 and / or the sixth transistor M6 may be constituted by a plurality of transistors connected in parallel with each other.

[0324] The first driving circuit 1210 may control the voltage of the third node N3 in response to the signals supplied to the first input terminal 1001 to the third input terminal 1003.

[0325] The first driving circuit 1210 may include the second transistor M2 to the fourth transistor M4.

[0326] The second transistor M2 may be connected between the first input terminal 1001 and the third node N3, and the gate electrode of the second transistor M2 may be connected to the second input terminal 1002. The second transistor M2 may control the connection between the first input terminal 1001 and the third node N3 in response to the signal supplied to the second input terminal 1002.

[0327] The third transistor M3 and the fourth transistor M4 may be connected in series between the third node N3 and the fourth input terminal 1004. The third transistor M3 may be connected between the fourth transistor M4 and the third node N3, and the gate electrode of the third transistor M3 may be connected to the third input terminal 1003. The third transistor M3 may control the connection between the fourth transistor M4 and the third node N3 in response to the signal supplied to the third input terminal 1003.

[0328] The fourth transistor M4 may be connected between the third transistor M3 and the fourth input terminal 1004, and the gate electrode of the fourth transistor M4 may be connected to the first node N1. The fourth transistor M4 may control the connection between the third transistor M3 and the fourth input terminal 1004 in response to the voltage of the first node N1.

[0329] The second driving circuit 1220 can control the voltage of the first node N1 in response to the voltages of the second input terminal 1002 and the third node N3. The second driving circuit 1220 can include a first transistor M1, a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

[0330] The second capacitor C1 can be connected between the second node N2 and the output terminal 1006. The first capacitor C1 can be charged with voltages corresponding to conduction and cutoff.

[0331] The second capacitor C2 can be connected between the first node N1 and the fourth input terminal 1004. The second capacitor C2 can be charged with the voltage applied to the first node N1.

[0332] The seventh transistor M7 can be connected between the first node N1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 can be connected to the third node N3. The seventh transistor M7 can control the connection between the first node N1 and the second input terminal 1002 in response to the voltage of the third node N3.

[0333] The eighth transistor M8 can be connected between the first node N1 and the fifth input terminal 1005 to which the second driving power supply VSS1 is supplied, and the gate electrode of the eighth transistor M8 can be connected to the second input terminal 1002. The eighth transistor M8 can control the connection between the first node N1 and the fifth input terminal 1005 in response to the signal of the second input terminal 1002.

[0334] The first transistor M1 can be connected between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 can be connected to the fifth input terminal 1005. The first transistor M1 can provide the connection between the third node N3 and the second node N2 while remaining in the conducting state. In addition, the first transistor M1 can control the reduction amplitude of the voltage of the third node N3 in response to the voltage of the second node N2. In other words, although the voltage of the second node N2 can be reduced to a voltage lower than the voltage of the second driving power supply VSS1, the voltage of the third node N3 can not be reduced to a voltage lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power supply VSS1. This will be described below.

[0335] The second scan stage circuit SST12 and the other scan stage circuits SST13 to SST1k can have the same configuration as the first scan stage circuit SST11.

[0336] The second input terminal 1002 of the j-th (j is odd or even) first scan stage circuit SST1j may receive the first clock signal CLK1, and the third input terminal 1003 may receive the second clock signal CLK2. The second input terminal 1002 of the (j + 1)-th first scan stage circuit SST1j+1 may receive the second clock signal CLK2, and the third input terminal 1003 may receive the first clock signal CLK1.

[0337] The first clock signal CLK1 and the second clock signal CLK2 may have the same period, but may have non-overlapping phases with each other. As an example, when the period during which a scan signal is supplied to one first scan line S1 is referred to as one horizontal period 1H, each of the clock signals CLK1 and CLK2 may have a period of 2H, and may be supplied in different horizontal periods from each other.

[0338] Figure 11 The figure shows the stage circuit included in the first scan driver 210, but in addition to the first scan driver 210, the stage circuit included in the second scan driver 220 may also have the same circuit configuration.

[0339] In addition, except that the input terminals 1001 - 1005 and the output terminal 1006 are not connected to the dummy scan stage circuit DSST, the above-mentioned dummy scan stage circuit DSST may have the same circuit configuration.

[0340] Figure 12 is a diagram showing Figure 11 the waveform diagram of the driving method of the shown scan stage circuit. For convenience, Figure 12 the operation using the first first scan stage circuit SST11 is shown.

[0341] As Figure 12 shown, each of the first clock signal CLK1 and the second clock signal CLK2 may have a period of two horizontal periods 2H, and may be supplied in different horizontal periods from each other. In other words, the second clock signal CLK2 may be set to a signal shifted by half a period (i.e., one horizontal period 1H) from the first clock signal CLK1. In addition, the first start pulse SSP1 supplied to the first input terminal 1001 is synchronized with the clock signal (i.e., the first clock signal CLK1) supplied to the second input terminal 1002.

[0342] When the first start pulse SSP1 is supplied, the first input terminal 1001 can be set to have the voltage of the second driving power supply VSS1, and when the first start pulse SSP1 is not supplied, the first input terminal 1001 can be set to have the voltage of the first driving power supply VDD1. In addition, when the clock signals CLK1 and CLK2 are supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to have the voltage of the second driving power supply VSS1, and when the clock signals CLK1 and CLK2 are not supplied, the second input terminal 1002 and the third input terminal 1003 can be set to have the voltage of the first driving power supply VDD1.

[0343] The operations are described in detail below. First, the first start pulse SSP1 is supplied in synchronization with the first clock signal CLK1.

[0344] When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 can be turned on. When the second transistor M2 is turned on, the first input terminal 1001 can be connected to the third node N3. Here, the first transistor M1 can be set to be continuously turned on, whereby the electrical connection between the second node N2 and the third node N3 can be maintained.

[0345] When the first input terminal 1001 is electrically connected to the third node N3, the third node N3 and the second node N2 can be set to have a low-level voltage by the first start pulse SSP1 supplied to the first input terminal 1001. When the third node N3 and the second node N2 are set to have a low-level voltage, the sixth transistor M6 and the seventh transistor M7 can be turned on.

[0346] When the sixth transistor M6 is turned on, the third input terminal 1003 can be electrically connected to the output terminal 1006. Here, the third input terminal 1003 is set to have a high-level voltage (i.e., the second clock signal CLK2 is not supplied), whereby a high-level voltage can also be output to the output terminal 1006. When the seventh transistor M7 is turned on, the second input terminal 1002 can be electrically connected to the first node N1. Then, the voltage of the first clock signal CLK1 (i.e., the low-level voltage supplied to the second input terminal 1002) can be supplied to the first node N1.

[0347] When the first clock signal CLK1 is supplied, the eighth transistor M8 can be turned on. When the eighth transistor M8 is turned on, the voltage of the second driving power supply VSS1 can be supplied to the first node N1. Here, the voltage of the second driving power supply VSS1 can be set to the same voltage as the first clock signal CLK1, so that the first node N1 can stably maintain a low-level voltage.

[0348] When the first node N1 is set to a voltage with a low level, the fourth transistor M4 and the fifth transistor M5 can be turned on. When the fourth transistor M4 is turned on, the fourth input terminal 1004 can be electrically connected to the third transistor M3. Here, the third transistor M3 is set to the cut-off state. Therefore, although the fourth transistor M4 is turned on, the third node N3 can stably maintain a voltage with a low level.

[0349] When the fifth transistor M5 is turned on, the voltage of the first driving power supply VDD1 can be supplied to the output terminal 1006. Here, the voltage of the first driving power supply VDD1 can be set to the level of the high voltage supplied to the third input terminal 1003. Thus, the output terminal 1006 can stably maintain a voltage with a high level.

[0350] Thereafter, the supply of the first start pulse SSP1 and the first clock signal CLK1 can be stopped. When the supply of the first clock signal CLK1 is stopped, the second transistor M2 and the eighth transistor M8 can be turned off. At the same time, the sixth transistor M6 and the seventh transistor M7 can be kept in the on state in response to the voltage stored in the first capacitor C1. That is to say, the second node N2 and the third node N3 can be kept at a voltage with a low level by the voltage stored in the first capacitor C1.

[0351] When the sixth transistor M6 remains in the on state, the electrical connection between the output terminal 1006 and the third input terminal 1003 can be maintained. When the seventh transistor M7 remains in the on state, the electrical connection between the first node N1 and the second input terminal 1002 can be maintained. Here, when the supply of the first clock signal CLK1 is stopped, the voltage of the second input terminal 1002 can be set to a voltage with a high level. Thus, the first node N1 can also be set to a voltage with a high level. When a voltage with a high level is supplied to the first node N1, the fourth transistor M4 and the fifth transistor M5 can be turned off.

[0352] Thereafter, the second clock signal CLK2 can be supplied to the third input terminal 1003. Since the sixth transistor M6 is set to the on state, the second clock signal CLK2 supplied to the third input terminal 1003 can be supplied to the output terminal 1006. In this case, the output terminal 1006 can output the second clock signal CLK2 to the first scan line as a scan signal.

[0353] At the same time, when the second clock signal CLK2 is supplied to the output terminal 1006, due to the coupling of the first capacitor C1, the voltage of the second node N2 can be reduced to a voltage lower than that of the second driving power supply VSS1. Thus, the sixth transistor M6 can be stably kept in the on state.

[0354] Meanwhile, although the voltage of the second node N2 decreases, the third node N3 can be maintained at a voltage approximately equal to that of the second driving power supply VSS1 (e.g., a voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power supply VSS1) through the first transistor M1.

[0355] After the scan signal is output to the first scan line S11, the supply of the second clock signal CLK2 can be stopped. When the supply of the second clock signal CLK2 is stopped, the output terminal 1006 can output a high-level voltage. In addition, the voltage of the second node N2 can increase to a voltage approximately equal to that of the second driving power supply VSS1 in response to the high-level voltage of the output terminal 1006.

[0356] Thereafter, the first clock signal CLK1 can be supplied. When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 can be turned on. When the second transistor M2 is turned on, the first input terminal 1001 can be electrically connected to the third node N3. The first start pulse SSP1 can be not supplied to the first input terminal 1001, and the first input terminal 1001 can be set to have a high-level voltage. Therefore, when the first transistor M1 is turned on, a high-level voltage can be supplied to the third node N3 and the second node N2, whereby the sixth transistor M6 and the seventh transistor M7 can be turned off.

[0357] When the eighth transistor M8 is turned on, the second driving power supply VSS1 can be supplied to the first node N1, whereby the fourth transistor M4 and the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the voltage of the first driving power supply VDD1 can be supplied to the output terminal 1006. Thereafter, the fourth transistor M4 and the fifth transistor M5 can be maintained in the on state in response to the voltage stored in the second capacitor C2, whereby the output terminal 1006 can stably receive the voltage of the first driving power supply VDD1.

[0358] In addition, when the second clock signal CLK2 is supplied, the third transistor M3 can be turned on. Since the fourth transistor M4 is set to the on state, the voltage of the first driving power supply VDD1 can be supplied to the third node N3 and the second node N2. In this case, the sixth transistor M6 and the seventh transistor M7 can be stably maintained in the off state.

[0359] The second scan stage circuit SST12 can receive the output signal (i.e., the scan signal) of the first first scan stage circuit SST11 to synchronize with the second clock signal CLK2. In this case, the second scan stage circuit SST12 can output the scan signal to the second line S12 of the first scan line to synchronize with the first clock signal CLK1. The scan stage circuit SST according to the present disclosure can repeat the above process, whereby the scan signal can be sequentially output to the scan lines.

[0360] Meanwhile, regardless of the voltage of the second node N2, the first transistor M1 limits the reduction amplitude of the voltage of the third node N3, so that the manufacturing cost can be reduced and the reliability of the drive signal can be improved.

[0361] Figure 13 FIG. is a diagram showing an emitter circuit according to an embodiment of the present disclosure.

[0362] For convenience Figure 13 shows the first first emitter stage circuit EST11 and the second first emitter stage circuit EST12 of the first emitter driver 310.

[0363] As Figure 13 shown, the first first emitter stage circuit EST11 can include a first drive circuit 2100, a second drive circuit 2200, a third drive circuit 2300, and an output unit 2400.

[0364] The first drive circuit 2100 can control the voltages of the twenty-second node N22 and the twenty-first node N21 in response to the signals supplied to the first input terminal 2001 and the second input terminal 2002. The first drive circuit 2100 can include the eleventh transistor M11 to the thirteenth transistor M13.

[0365] The eleventh transistor M11 can be connected between the first input terminal 2001 and the twenty-first node N21, and the gate electrode of the eleventh transistor M11 can be connected to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 can be turned on.

[0366] The twelfth transistor M12 can be connected between the second input terminal 2002 and the twenty-second node N22, and the gate electrode of the twelfth transistor M12 can be connected to the twenty-first node N21. The twelfth transistor M12 can be turned off in response to the voltage of the twenty-first node N21.

[0367] The thirteenth transistor M13 may be connected between the twenty-second node N22 and the fifth input terminal 2005 for receiving the fourth driving power supply VSS2, and the gate electrode of the thirteenth transistor M13 may be connected to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the thirteenth transistor M13 may be turned on.

[0368] The second driving circuit 2200 may control the voltages of the twenty-first node N21 and the twenty-third node N23 in response to the signal supplied to the third input terminal 2003 and the voltage of the twenty-second node N22. The second driving circuit 2200 may include a fourteenth transistor M14 to a seventeenth transistor M17, an eleventh capacitor C11, and a twelfth capacitor C12.

[0369] The fourteenth transistor M14 may be connected between the fifteenth transistor M15 and the twenty-first node N21, and the gate electrode of the fourteenth transistor M14 may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 may be turned on.

[0370] The fifteenth transistor M15 may be connected between the fourteenth transistor M14 and the fourth input terminal 2004 for receiving the third driving power supply VDD2, and the gate electrode of the fifteenth transistor M15 may be connected to the twenty-second node N22. The fifteenth transistor M15 may be turned on or off in response to the voltage of the twenty-second node N22.

[0371] The sixteenth transistor M16 may be connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003, and the gate electrode of the sixteenth transistor M16 may be connected to the twenty-second node N22. The sixteenth transistor M16 may be turned on or off in response to the voltage of the twenty-second node N22.

[0372] The seventeenth transistor M17 may be connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23, and the gate electrode of the seventeenth transistor M17 may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the seventeenth transistor M17 may be turned on.

[0373] The eleventh capacitor C11 may be connected between the twenty-first node N21 and the third input terminal 2003.

[0374] The twelfth capacitor C12 may be connected between the twenty-second node N22 and the seventeenth transistor M17.

[0375] The third driving circuit 2300 can control the voltage of the twenty-third node N23 in response to the voltage of the twenty-first node N21. The third driving circuit 2300 can include the eighteenth transistor M18 and the thirteenth capacitor C13.

[0376] The eighteenth transistor M18 can be connected between the twenty-third node N23 and the fourth input terminal 2004 for receiving the third driving power supply VDD2, and the gate electrode of the eighteenth transistor M18 can be connected to the twenty-first node N21. The eighteenth transistor M18 can be turned on or off in response to the voltage of the twenty-first node N21.

[0377] The thirteenth capacitor C13 can be connected between the twenty-third node N23 and the fourth input terminal 2004 for receiving the third driving power supply VDD2.

[0378] The output unit 2400 can control the voltage supplied to the output terminal 2006 in response to the voltages of the twenty-first node N21 and the twenty-third node N23. The output unit 2400 can include the nineteenth transistor M19 and the twentieth transistor M20.

[0379] The nineteenth transistor M19 can be connected between the output terminal 2006 and the fourth input terminal 2004 for receiving the third driving power supply VDD2, and the gate electrode of the nineteenth transistor M19 can be connected to the twenty-third node N23. The nineteenth transistor M19 can be turned on or off in response to the voltage of the twenty-third node N23.

[0380] The twentieth transistor M20 can be connected between the output terminal 2006 and the fifth input terminal 2005 for receiving the fourth driving power supply VSS2, and the gate electrode of the twentieth transistor M20 can be connected to the twenty-first node N21. The twentieth transistor M20 can be turned on or off in response to the voltage of the twenty-first node N21. The output unit 2400 can be driven to act as a buffer.

[0381] In addition, the nineteenth transistor M19 and the twentieth transistor M20 can be constituted by a plurality of transistors connected in parallel with each other.

[0382] The second first emitter circuit EST12 and the other emitter circuits EST13 to EST1k can have the same configuration as the first first emitter circuit EST11.

[0383] The second input terminal 2002 of the j-th first emission stage circuit EST1j may receive the third clock signal CLK3, and the third input terminal 2003 may receive the fourth clock signal CLK4. The second input terminal 2002 of the (j + 1)-th first emission stage circuit EST1j+1 may receive the fourth clock signal CLK4, and the third input terminal 2003 may receive the third clock signal CLK3.

[0384] The third clock signal CLK3 and the fourth clock signal CLK4 may have the same period, but have non-overlapping phases with each other. As an example, each of the clock signals CLK3 and CLK4 may have a period of 2H and may be supplied in different horizontal time periods from each other.

[0385] Figure 13 The figure shows the stage circuits included in the first emission driver 310. However, in addition to the first emission driver 310, the stage circuits included in the second emission driver 320 may also have the same circuit configuration.

[0386] In addition, except that the input terminals 2001 to 2005 and the output terminal 2006 are not connected to the dummy emission stage circuit DEST, the above-mentioned dummy emission stage circuit DEST may have the same circuit configuration.

[0387] Figure 14 is a diagram showing Figure 13 a waveform diagram of the driving method of the shown emission stage circuit. For convenience, Figure 14 the operation using the first first emission stage circuit EST11 is shown.

[0388] As Figure 14 shown, each of the third clock signal CLK3 and the fourth clock signal CLK4 may have a period of two horizontal time periods 2H and may be supplied in different horizontal time periods from each other. In other words, the fourth clock signal CLK4 may be set to a signal shifted by half a period (i.e., one horizontal time period 1H) from the third clock signal CLK3.

[0389] When the second start pulse SSP2 is supplied, the first input terminal 2001 can be set to have the voltage of the third driving power supply VDD2, and when the second start pulse SSP2 is not supplied, the first input terminal 2001 can be set to have the voltage of the fourth driving power supply VSS2. In addition, when the clock signals CLK3 and CLK4 are supplied to the second input terminal 2002 and the third input terminal 2003, the second input terminal 2002 and the third input terminal 2003 can be set to have the voltage of the fourth driving power supply VSS2, and when the clock signals CLK3 and CLK4 are not supplied, the second input terminal 2002 and the third input terminal 2003 can be set to have the voltage of the third driving power supply VDD2.

[0390] The second start pulse SSP2 supplied to the first input terminal 2001 can be synchronized with the clock signal (i.e., the third clock signal CLK3) supplied to the second input terminal 2002. In addition, the second start pulse SSP2 can be set to have a width larger than the width of the third clock signal CLK3. As an example, the second start pulse SSP2 can be supplied during the horizontal period 4H.

[0391] The operations are described in detail below. First, the third clock signal CLK3 can be supplied to the second input terminal 2002 at the first time t1. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 can be turned on.

[0392] When the eleventh transistor M11 is turned on, the first input terminal 2001 can be electrically connected to the twenty-first node N21. Since the second start pulse SSP2 may not be supplied to the first input terminal 2001, a low-level voltage can be supplied to the twenty-first node N21.

[0393] When a low-level voltage is supplied to the twenty-first node N21, the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 can be turned on.

[0394] When the eighteenth transistor M18 is turned on, the third driving power supply VDD2 can be supplied to the twenty-third node N23, whereby the nineteenth transistor M19 can be turned off.

[0395] At the same time, the thirteenth capacitor C13 can be charged with the voltage corresponding to the third driving power supply VDD2, whereby the first transistor M19 can be maintained in the off state after the first time t1.

[0396] When the twentieth transistor M20 is turned on, the voltage of the fourth drive power supply VSS2 can be supplied to the output terminal 2006. Therefore, the emission control signal can be not supplied to the first line E11 of the first emission control line at the first time t1.

[0397] When the twelfth transistor M12 is turned on, the third clock signal CLK3 can be supplied to the twenty-second node N22. In addition, when the thirteenth transistor M13 is turned on, the voltage of the fourth drive power supply VSS2 can be supplied to the twenty-second node N22. Here, the third clock signal CLK3 can be set to the voltage of the fourth drive power supply VSS2, whereby the twenty-second node N22 can be stably set to have the voltage of the fourth drive power supply VSS2. At the same time, when the voltage of the twenty-second node N22 is set to the fourth drive power supply VSS2, the seventeenth transistor M17 can be set to the cut-off state. Therefore, regardless of the voltage of the twenty-second node N22, the twenty-third node N23 can be maintained at the voltage of the third drive power supply VDD2.

[0398] The supply of the third clock signal CLK3 to the second input terminal 2002 can be stopped at the second time t2. When the supply of the third clock signal CLK3 is stopped, the eleventh transistor M11 and the thirteenth transistor M13 can be turned off. At this time, the voltage of the twenty-first node N21 can be held at a low-level voltage by the eleventh capacitor C11, whereby the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 can be held in the on state.

[0399] When the twelfth transistor M12 is turned on, the second input terminal 2002 can be electrically connected to the twenty-second node N22. At this time, the twenty-second node N22 can be set to have a high-level voltage.

[0400] When the eighteenth transistor M18 is turned on, the voltage of the third drive power supply VDD2 can be supplied to the twenty-third node N23, so that the nineteenth transistor M19 can be held in the cut-off state.

[0401] When the twentieth transistor M20 is turned on, the voltage of the fourth drive power supply VSS2 can be supplied to the output terminal 2006.

[0402] The fourth clock signal CLK4 can be supplied to the third input terminal 2003 at the third time t3. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 can be turned on.

[0403] When the seventeenth transistor M17 is turned on, the twelfth capacitor C12 can be electrically connected to the twenty-third node N23. At this time, the twenty-third node N23 can be held at the voltage of the third driving power supply VDD2. In addition, when the fourteenth transistor M14 is turned on, the fifteenth transistor M15 can be set to the off state, whereby, although the fourteenth transistor M14 is turned on, the voltage of the twenty-first node N21 can remain unchanged.

[0404] When the fourth clock signal CLK4 is supplied to the third input terminal 2003, due to the coupling of the eleventh capacitor C11, the voltage of the twenty-first node N21 can be reduced to a voltage lower than that of the fourth driving power supply VSS2. When the voltage of the twenty-first node N21 is reduced to a voltage lower than that of the fourth driving power supply VSS2, the driving characteristics of the eighteenth transistor M18 and the twentieth transistor M20 can be improved. The lower the voltage received by the PMOS transistor, the better the driving characteristics of the PMOS transistor.

[0405] The second start pulse SSP2 can be supplied to the first input terminal 2001 at the fourth time t4, and the third clock signal CLK3 can be supplied to the second input terminal 2002.

[0406] When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 can be turned on. When the eleventh transistor M11 is turned on, the first input terminal 2001 can be electrically connected to the twenty-first node N21. Since the second start pulse SSP2 is supplied to the first input terminal 2001, a high-level voltage can be supplied to the twenty-first node N21. When the high-level voltage is supplied to the twenty-first node N21, the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 can be turned off.

[0407] When the thirteenth transistor M13 is turned on, the voltage of the fourth driving power supply VSS2 can be supplied to the twenty-second node N22. Since the fourteenth transistor M14 is set to the off state, the twenty-first node N21 can be held at the high-level voltage. In addition, since the seventeenth transistor M17 is set to the off state, the voltage of the twenty-third node N23 can be held at the high-level voltage through the thirteenth capacitor C13. Therefore, the nineteenth transistor M19 can be held in the off state.

[0408] The fourth clock signal CLK4 can be supplied to the third input terminal 2003 at the fifth time t5. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 can be turned on. In addition, since the twenty-second node N22 is set to have the voltage of the fourth drive power supply VSS2, the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on.

[0409] When the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the fourth clock signal CLK4 can be supplied to the twenty-third node N23. When the fourth clock signal CLK4 is supplied to the twenty-third node N23, the nineteenth transistor M19 can be turned on. When the nineteenth transistor M19 is turned on, the voltage of the third drive power supply VDD2 can be supplied to the output terminal 2006. The voltage of the third drive power supply VDD2 supplied to the output terminal 2006 can be supplied to the first line E11 of the first emission control line as an emission control signal.

[0410] Meanwhile, when the voltage of the fourth clock signal CLK4 is supplied to the twenty-third node N23, due to the coupling of the twelfth capacitor C12, the voltage of the twenty-second node N22 can be reduced to a voltage lower than the voltage of the fourth drive power supply VSS2, so that the driving characteristics of the transistors connected to the twenty-second node N22 can be improved.

[0411] When the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the voltage of the third drive power supply VDD2 can be supplied to the twenty-first node N21. Since the voltage of the third drive power supply VDD2 can be supplied to the twenty-first node N21, the twentieth transistor M20 can be kept in the off state. Therefore, the voltage of the third drive power supply VDD2 can be supplied to the first line E11 of the first emission control line.

[0412] The third clock signal CLK3 can be supplied to the second input terminal 2002 at the sixth time t6. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 can be turned on.

[0413] When the eleventh transistor M11 is turned on, the twenty-first node N21 can be electrically connected to the first input terminal 2001, whereby the twenty-first node N21 can be set to have a low-level voltage. When the twenty-first node N21 is set to have a low-level voltage, the eighteenth transistor M18 and the twentieth transistor M20 can be turned on.

[0414] When the eighteenth transistor M18 is turned on, the voltage of the third driving power supply VDD2 can be supplied to the twenty-third node N23. Thus, the nineteenth transistor M19 can be turned off. If the twentieth transistor M20 is turned on, the voltage of the fourth driving power supply VSS2 can be supplied to the output terminal 2006. The voltage of the fourth driving power supply VSS2 supplied to the output terminal 2006 can be supplied to the first line E11 of the first emission control line. Thus, the supply of the emission control signal can be stopped.

[0415] The emitter circuit EST according to the present disclosure can repeat the above process. Thus, the emission control signal can be sequentially output to the emission control line.

[0416] Figure 15 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0417] For convenience, Figure 15 shows the first pixel PXL1 connected to the m-th data line Dm and the i-th line Sli of the first scan line.

[0418] As Figure 15 shown, the first pixel PXL1 may include an organic light emitting diode OLED, first transistors T1 to seventh transistors T7, and a storage capacitor Cst.

[0419] The anode of the organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6, and the cathode of the organic light emitting diode OLED may be connected to the second pixel power supply ELVSS. The organic light emitting diode OLED may emit light with a predetermined brightness in response to the current supplied from the first transistor T1.

[0420] The first pixel power supply ELVDD may be set to a voltage higher than that of the second pixel power supply ELVSS so that current flows through the organic light emitting diode OLED.

[0421] The seventh transistor T7 may be connected between the initialization power supply Vint and the anode of the organic light emitting diode OLED. In addition, the gate electrode of the seventh transistor T7 may be connected to the (i + 1)-th line Sli+1 of the first scan line. When the scan signal is supplied to the (i + 1)-th line Sli+1 of the first scan line, the seventh transistor T7 may be turned on. Thus, the voltage of the initialization power supply Vint can be supplied to the anode of the organic light emitting diode OLED. Here, the initialization power supply Vint may be set to a voltage lower than the voltage of the data signal.

[0422] The sixth transistor T6 may be connected between the first transistor T1 and the organic light-emitting diode OLED. In addition, the gate electrode of the sixth transistor T6 may be connected to the i-th line Eli of the first emission control line. When an emission control signal is supplied to the i-th line Eli of the first emission control line, the sixth transistor T6 may be turned off and may be turned on in other cases.

[0423] The fifth transistor T5 may be connected between the first pixel power supply ELVDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 may be connected to the i-th line Eli of the first emission control line. When an emission control signal is supplied to the i-th line Eli of the first emission control line, the fifth transistor T5 may be turned off and may be turned on in other cases.

[0424] The first electrode of the first transistor T1 (i.e., the driving transistor) may be connected to the first pixel power supply ELVDD through the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the anode of the organic light-emitting diode OLED through the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the tenth node N10. The first transistor T1 may control the current flowing from the first pixel power supply ELVDD through the organic light-emitting diode OLED to the second pixel power supply ELVSS in response to the voltage of the tenth node N10.

[0425] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the tenth node N10. In addition, the gate electrode of the third transistor T3 may be connected to the i-th line Sli of the first scan line. When a scan signal is supplied to the i-th line Sli of the first scan line, the third transistor T3 may be turned on, whereby the second electrode of the first transistor T1 may be electrically connected to the tenth node N10. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form.

[0426] The fourth transistor T4 may be connected between the tenth node N10 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor T4 may be connected to the (i - 1)-th line Sli-1 of the first scan line. When a scan signal is supplied to the (i - 1)-th line Sli-1 of the first scan line, the fourth transistor T4 may be turned on, whereby the initialization power supply Vint is supplied to the tenth node N10.

[0427] The second transistor T2 may be connected between the m-th data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th line Sli of the first scan line. When a scan signal is supplied to the i-th line Sli of the first scan line, the second transistor T2 may be turned on, whereby the first electrode of the first transistor T1 is electrically connected to the m-th data line Dm.

[0428] The storage capacitor Cst may be connected between the first pixel power supply ELVDD and the tenth node N10. The storage capacitor Cst may store a voltage corresponding to a data signal and a threshold voltage of the first transistor T1.

[0429] According to an embodiment, the second pixel PXL2 may be implemented by the same circuit as the first pixel PXL1. Accordingly, a detailed description of the second pixel PXL2 will be omitted.

[0430] In addition, Figure 15 The illustrated pixel structure is merely an example using a scan line and an emission control line, and the pixels PXL1 and PXL2 according to the present disclosure are not limited to this pixel structure. The pixel may have a circuit structure capable of supplying current to the organic light-emitting diode OLED and may be selected as any one of various known structures.

[0431] In the present disclosure, the organic light-emitting diode OLED may generate various colors of light including red, green, and blue in response to current supplied from the driving transistor, but the present disclosure is not limited thereto. For example, the organic light-emitting diode OLED may generate white light in response to current supplied from the driving transistor. In this case, a color image may be generated by using a separate color filter or the like.

[0432] In addition, for convenience, in the present disclosure, the transistors are described by using P-channel (P-type) transistors, but the present disclosure is not limited thereto. In other words, the transistors may be formed of N-channel (N-type) transistors.

[0433] In addition, depending on the type of the transistor, the gate cut-off voltage and the gate turn-on voltage of the transistor may be set to voltages of different levels.

[0434] For example, in the case of a P-channel transistor, the gate cut-off voltage and the gate turn-on voltage may be set to a high-level voltage and a low-level voltage, respectively, and in the case of an N-channel transistor, the gate cut-off voltage and the gate turn-on voltage may be set to a low-level voltage and a high-level voltage, respectively.

[0435] Figure 16 is a diagram showing a pixel region of a display device according to another embodiment of the present disclosure.

[0436] Reference will be made to Figure 16 to mainly describe parts different from the above-described embodiments (e.g., Figure 1 ), and parts overlapping with the above-described embodiments will not be described again. Accordingly, hereinafter, the third pixel region AA3 and the third pixel PXL3 will be mainly described.

[0437] As Figure 16As shown, the display device 10' may include pixel regions AA1, AA2, and AA3, peripheral regions NA1, NA2, and NA3, and pixels PXL1, PXL2, and PXL3.

[0438] The second pixel region AA2 and the third pixel region AA3 may be located on one side of the first pixel region AA1. The second pixel region AA2 and the third pixel region AA3 may be located at separate positions from each other.

[0439] The first pixel region AA1 may have an area wider than that of the second pixel region AA2 and the third pixel region AA3.

[0440] For example, the width W1 of the first pixel region AA1 may be set to be greater than the widths W2 and W3 of the other pixel regions AA2 and AA3, and the length L1 of the first pixel region AA1 may be set to be greater than the lengths L2 and L3 of the other pixel regions AA2 and AA3.

[0441] In addition, each of the second pixel region AA2 and the third pixel region AA3 may have an area smaller than that of the first pixel region AA1, and may have the same or different areas from each other.

[0442] For example, the width W2 of the second pixel region AA2 may be set to be the same as or different from the width W3 of the third pixel region AA3, and the length L2 of the second pixel region AA2 may be set to be the same as or different from the length L3 of the third pixel region AA3.

[0443] The third peripheral region NA3 may be located outside the third pixel region AA3, and may have a shape surrounding at least a part of the third pixel region AA3.

[0444] The width of the third peripheral region NA3 may be set to be substantially uniform along the periphery surrounding the third pixel region AA3. However, the present disclosure is not limited thereto, and the width of the third peripheral region NA3 may be set differently according to the position.

[0445] According to the shape of the substrate 100, the second peripheral region NA2 and the third peripheral region NA3 may be connected to each other or may not be connected to each other.

[0446] The widths of the peripheral regions NA1, NA2, and NA3 may be set to be generally the same. However, the present disclosure is not limited thereto, and the widths of the peripheral regions NA1, NA2, and NA3 may be set differently according to the position.

[0447] The pixels PXL1, PXL2, and PXL3 may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3.

[0448] For example, the first pixel PXL1 may be located in the first pixel region AA1, the second pixel PXL2 may be located in the second pixel region AA2, and the third pixel PXL3 may be located in the third pixel region AA3.

[0449] The pixels PXL1, PXL2, and PXL3 may emit light with a predetermined luminance according to the control of drivers located in the peripheral regions NA1, NA2, and NA3, and each of the pixels may include a light-emitting element (e.g., an organic light-emitting diode).

[0450] The substrate 100 may be formed in various forms in which the above-described pixel regions AA1, AA2, and AA3 and the above-described peripheral regions NA1, NA2, and NA3 can be set.

[0451] For example, the substrate 100 may include a base substrate 101, and a first auxiliary plate 102 and a second auxiliary plate 103 that protrude and extend from one end of the base substrate 101 on one side.

[0452] According to one embodiment, the first auxiliary plate 102 and the second auxiliary plate 103 may be formed integrally with the base substrate 101, and a recess 104 may be located between the first auxiliary plate 102 and the second auxiliary plate 103.

[0453] The recess 104 may be formed by removing a part of the substrate 100, whereby the first auxiliary plate 102 and the second auxiliary plate 103 may be separated from each other.

[0454] The first auxiliary plate 102 and the second auxiliary plate 103 may have an area smaller than that of the base substrate 101, and may have the same area or different areas from each other.

[0455] The first auxiliary plate 102 and the second auxiliary plate 103 may be formed in various shapes in which the pixel regions AA2 and AA3 and the peripheral regions NA2 and NA3 can be set.

[0456] In this case, the above-described first pixel region AA1 and the first peripheral region NA1 may be defined in the base substrate 101, the above-described second pixel region AA2 and the second peripheral region NA2 may be defined in the first auxiliary plate 102, and the above-described third pixel region AA3 and the third peripheral region NA3 may be defined in the second auxiliary plate 103.

[0457] The base substrate 101 may also have various shapes. For example, the base substrate 101 may have a polygonal shape, an annular shape, etc. In addition, at least a part of the base substrate 101 may have a curved shape.

[0458] For example, the base substrate 101 may have, as Figure 16The quadrilateral shown. The corners of the base substrate 101 can be deformed into an inclined plane shape or a curved shape.

[0459] The base substrate 101 can have the same or a similar shape as the first pixel region AA1, but is not limited thereto, and can have a shape different from that of the first pixel region AA1.

[0460] The first auxiliary plate 102 and the second auxiliary plate 103 can also have various shapes.

[0461] For example, the first auxiliary plate 102 and the second auxiliary plate 103 can have shapes such as a polygonal shape or an annular shape. In addition, at least a part of the first auxiliary plate 102 and the second auxiliary plate 103 can have a curved shape.

[0462] The recess 104 can have various shapes. For example, the recess 104 can have shapes such as a polygonal shape or an annular shape. In addition, at least a part of the recess 104 can have a curved shape.

[0463] The third pixel region AA3 can have various shapes. For example, the third pixel region AA3 can have shapes such as a polygonal shape or an annular shape.

[0464] In addition, at least a part of the third pixel region AA3 can have a curved shape.

[0465] For example, the corners of the third pixel region AA3 can have: a curved shape with a predetermined curvature.

[0466] In this case, at least a part of the third peripheral region NA3 can have a curved shape corresponding to the third pixel region AA3.

[0467] According to the deformation of the third pixel region AA3, the number of the third pixels PXL3 located in a line (row or column) can change according to the position.

[0468] Figure 17 is a diagram showing a display device according to another embodiment of the present disclosure.

[0469] Reference will be made to Figure 16 to mainly describe the parts different from the above embodiments (for example, Figure 2 ), and the parts overlapping with the above embodiments will not be described again. Accordingly, hereinafter, the third pixel PXL3, the third scan driver 230, and the third emission driver 330 will be mainly described.

[0470] As Figure 17As shown, the display device 10' may include a substrate 100, a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, a first scan driver 210, a second scan driver 220, a third scan driver 230, a first emission driver 310, a second emission driver 320, and a third emission driver 330.

[0471] The third pixel PXL3 may be located in a third pixel region AA3 and may be connected to a third scan line S3, a third emission control line E3, and a third data line D3, respectively.

[0472] The third scan driver 230 may supply a third scan signal to the third pixel PXL3 through the third scan line S3.

[0473] For example, the third scan driver 230 may sequentially supply the third scan signal to the third scan line S3.

[0474] The third scan driver 230 may be located in a third peripheral region NA3.

[0475] For example, the third scan driver 230 may be located in the third peripheral region NA3 provided on one side (e.g., the right side as Figure 17 shown) of the third pixel region AA3.

[0476] A third scan wiring R5 may be connected between the third scan driver 230 and the third scan line S3.

[0477] The third scan driver 230 may be electrically connected to the third scan line S3 located in the third pixel region AA3 through the third scan wiring R5.

[0478] The third emission driver 330 may supply a third emission control signal to the third pixel PXL3 through the third emission control line E3.

[0479] For example, the third emission driver 330 may sequentially supply the third emission control signal to the third emission control line E3.

[0480] The third emission driver 330 may be located in the third peripheral region NA3.

[0481] For example, the third emission driver 330 may be located in the third peripheral region NA3 provided on one side (e.g., the right side as Figure 17 shown) of the third pixel region AA3.

[0482] Figure 17 The third emission driver 330 located outside the third scan driver 230 is shown, but in another embodiment, the third emission driver 330 may be located inside the third scan driver 230.

[0483] The third emission wiring R6 may be connected between the third emission driver 330 and the third emission line E3.

[0484] The third emission driver 330 may be electrically connected to the third emission control line E3 located in the third pixel region AA3 through the third emission wiring R6.

[0485] If the third pixel PXL3 has a structure that does not require the third emission control signal, the third emission driver 330, the third emission wiring R6, and the third emission control line E3 may be omitted.

[0486] Since the third pixel region AA3 has an area smaller than that of the first pixel region AA1, the lengths of the third scan line S3 and the third emission control line E3 may be smaller than the lengths of the first scan line S1 and the first emission control line E1.

[0487] In addition, the number of third pixels PXL3 connected to one third scan line S3 may be less than the number of first pixels PXL1 connected to one first scan line S1, and the number of third pixels PXL3 connected to one third emission control line E3 may be less than the number of first pixels PXL1 connected to one first emission control line E1.

[0488] The data driver 400 may supply data signals to the pixels PXL1, PXL2, and PXL3 through the data lines D1, D2, and D3. For example, the second data line D2 may be connected to a part of the first data line D1, and the third data line D3 may be connected to another part of the first data line D1.

[0489] Figure 18 is a more detailed diagram of a display device according to another embodiment of the present disclosure.

[0490] will be mainly described with reference to Figure 18 the parts different from the above embodiments (e.g., Figure 3 ), and the parts overlapping with the above embodiments will not be described again. Accordingly, the third scan driver 230 and the third emission driver 330 will be mainly described below.

[0491] The third scan driver 230 may supply third scan signals to the third pixels PXL3 through the third scan wirings R51 to R5h and the third scan lines S31 to S3h.

[0492] The third scan wirings R51 to R5h may be connected between the output terminals of the third scan driver 230 and the third scan lines S31 to S3h.

[0493] For example, the third scan wirings R51 to R5h and the third scan lines S31 to S3h may be located in different layers from each other, and in this case, they may be connected to each other through contact holes (not shown).

[0494] The third scan driver 230 may operate in response to the third scan control signal SCS3.

[0495] The third emission driver 330 may supply the third emission control signal to the third pixel PXL3 through the third emission wirings R61 to R6h and the third emission control lines E31 to E3h.

[0496] The third emission wirings R61 to R6h may be connected between the output terminals of the third emission driver 330 and the third emission control lines E31 to E3h.

[0497] For example, the third emission wirings R61 to R6h and the third emission control lines E31 to E3h may be located in different layers from each other, and in this case, they may be connected to each other through contact holes (not shown).

[0498] The third emission driver 330 may operate in response to the third emission control signal ECS3.

[0499] The data driver 400 may supply data signals to the third pixel PXL3 through the third data lines D31 to D3q.

[0500] The third pixel PXL3 may be connected to the first pixel power supply ELVDD and the second pixel power supply ELVSS. If necessary, the third pixel PXL3 may additionally be connected to the initialization power supply Vint.

[0501] When the third scan signal is supplied to the third scan lines S31 to S3h, the third pixel PXL3 may receive data signals from the third data lines D31 to D3q, and the third pixel PXL3 that has received the data signal may control the current flowing from the first pixel power supply ELVDD through an organic light-emitting diode (not shown) to the second pixel power supply ELVSS.

[0502] The number of third pixels PXL3 located in one line (row or column) may vary according to the position.

[0503] For example, the third data lines D31 to D3q may be connected to a part of the first data lines D1n+1 to D1o.

[0504] In addition, the second data lines D21 to D2p may be connected to a part of the first data lines D11 to D1m-1.

[0505] Since the third pixel region AA3 has an area smaller than that of the first pixel region AA1, the number of third pixels PXL3 can be less than the number of first pixels PXL1, and the lengths of the third scan lines S31 to S3h and the third emission control lines E31 to E3h can be less than the lengths of the first scan lines S11 to S1k and the first emission control lines E11 to E1k.

[0506] The number of third pixels PXL3 connected to any one of the third scan lines S31 to S3h can be less than the number of first pixels PXL1 connected to any one of the first scan lines S11 to S1k.

[0507] In addition, the number of third pixels PXL3 connected to any one of the third emission control lines E31 to E3h can be less than the number of first pixels PXL1 connected to any one of the first emission control lines E11 to E1k.

[0508] The timing controller 270 can supply the third scan control signal SCS3 and the third emission control signal ECS3 to the third scan driver 230 and the third emission driver 330, respectively, to control the third scan driver 230 and the third emission control driver 330.

[0509] Each of the third scan control signal SCS3 and the third emission control signal ECS3 can include at least one clock signal and at least one start pulse.

[0510] Figure 19 Yes Figure 18 A more detailed diagram of the third scan driver and the third emission driver shown.

[0511] As Figure 19 Shown, the third scan driver 230 can include a plurality of third scan stage circuits SST31 to SST3h.

[0512] Each of the third scan stage circuits SST31 to SST3h can be connected to corresponding terminals of the third scan wirings R51 to R5h, whereby the third scan signals are supplied to the third scan lines S31 to S3h.

[0513] The third scan stage circuits SST31 to SST3h can operate in response to the clock signals CLK5 and CLK6 supplied from the timing controller 270. According to one embodiment, the third scan stage circuits SST31 to SST3h can be implemented by the same circuit.

[0514] The third scan stage circuits SST31 to SST3h can receive the output signal of the previous scan stage circuit or the fifth start pulse SSP5.

[0515] For example, the first circuit SST31 in the third scan stage circuit can receive the fifth start pulse SSP5, and the other third scan stage circuits SST32 to SST3h can receive the output signals of the previous scan stage circuits.

[0516] Each of the third scan stage circuits SST31 to SST3h can receive the first drive power supply VDD1 and the second drive power supply VSS1.

[0517] The fifth clock line 245 and the sixth clock line 246 can be connected to the third scan driver 230.

[0518] The fifth clock line 245 and the sixth clock line 246 can be connected to the timing controller 270, whereby the fifth clock signal CLK5 and the sixth clock signal CLK6 supplied from the timing controller 270 are transmitted to the third scan driver 230.

[0519] According to one embodiment, the fifth clock line 245 and the sixth clock line 246 can be provided in the first peripheral region NA1 and the third peripheral region NA3.

[0520] The fifth clock signal CLK5 and the sixth clock signal CLK6 can have different phases from each other. For example, the sixth clock signal CLK6 can have a 180-degree phase difference relative to the fifth clock signal CLK5.

[0521] Figure 19 It is shown that the third scan driver 230 uses two clock signals CLK5 and CLK6, and the number of clock signals used by the third scan driver 230 can be changed according to the structure of the scan stage circuit.

[0522] The third scan stage circuits SST31 to SST3h can have the same circuit structure as the first scan stage circuits SST11 to SST1k and the second scan stage circuits SST21 to SST2j described above.

[0523] The third emission driver 330 can include a plurality of third emission stage circuits EST31 to EST3h.

[0524] Each of the third emission stage circuits EST31 to EST3h can be connected to the corresponding terminals of the third emission wirings R61 to R6h, whereby the third emission control signal is supplied to the third emission control lines E31 to E3h.

[0525] The third emission stage circuits EST31 to EST3h can operate in response to the clock signals CLK7 and CLK8 supplied from the timing controller 270. According to one embodiment, the third emission stage circuits EST31 to EST3h can be implemented by the same circuit.

[0526] The third emission stage circuits EST31 to EST3h can receive the output signal (i.e., the emission control signal) of the previous emission stage circuit or the sixth start pulse SSP6.

[0527] For example, the first circuit EST31 in the third emission stage circuits can receive the sixth start pulse SSP6, and the other third emission stage circuits EST32 to EST3h can receive the output signal of the previous emission stage circuit.

[0528] Each of the third emission stage circuits EST31 to EST3h can receive the third drive power supply VDD2 and the fourth drive power supply VSS2.

[0529] The seventh clock line 247 and the eighth clock line 248 can be connected to the third emission driver 330.

[0530] In addition, the seventh clock line 247 and the eighth clock line 248 can be connected to the timing controller 270, whereby the seventh clock signal CLK7 and the eighth clock signal CLK8 supplied from the timing controller 270 are transmitted to the third emission driver 330.

[0531] According to one embodiment, the seventh clock line 247 and the eighth clock line 248 can be provided in the first peripheral area NA1 and the third peripheral area NA3.

[0532] The seventh clock signal CLK7 and the eighth clock signal CLK8 can have different phases from each other. For example, the eighth clock signal CLK8 can have a 180-degree phase difference with respect to the seventh clock signal CLK7.

[0533] Figure 19 It is shown that the third emission driver 330 uses two clock signals CLK7 and CLK8, and the number of clock signals used by the third emission driver 330 can be changed according to the structure of the emission stage circuit.

[0534] The third emission stage circuits EST31 to EST3h can have the same circuit structure as the first emission stage circuits EST11 to EST1k and the second emission stage circuits EST21 to EST2j described above.

[0535] Figure 20 FIG. is a diagram showing a layout structure of a third scan stage circuit and a third emission stage circuit according to an embodiment of the present disclosure.

[0536] Specifically, Figure 20 Exemplarily shown are the third scan stage circuits SST31 to SST310 and the third emission stage circuits EST31 to EST310 provided in the third peripheral area NA3.

[0537] As shown Figure 20 in the figure, the corners of the third peripheral region NA3 may have a curved shape. For example, as Figure 20 shown, the region where the third scan stage circuits SST31 to SST310 and the third emission stage circuits EST31 to EST310 are provided in the third peripheral region NA3 may have: a curved shape with a predetermined curvature.

[0538] The corners of the third pixel region AA3 corresponding to the curved shape of the third peripheral region NA3 may also have a curved shape.

[0539] In order to make the corners of the third pixel region AA3 have a curved shape, the farther the pixel rows in the third pixel region AA3 are from the first pixel region AA1, the fewer the number of pixels PXL3 that the row may include.

[0540] The farther the pixel rows arranged in the third pixel region AA3 are from the first pixel region AA1, the smaller the length of the row. It is not necessary to reduce the length in the same proportion, and the number of the third pixels PXL3 included in each pixel row may be changed differently according to the curvature of the curve forming the corners of AA3.

[0541] The third scan stage circuits SST31 to SST310 and the third emission stage circuits EST31 to EST310 may be provided in the same shape as Figure 5 the second scan stage circuits SST21 to SST210 and the second emission stage EST21 to EST210 shown.

[0542] For example, the gap P9 between adjacent third scan stage circuits SST31 to SST310 may be set to be larger than the gap P1 between adjacent first scan stage circuits SST11 to SST16.

[0543] In addition, the gap P9 between adjacent third scan stage circuits SST31 to SST310 may be set to be different from each other according to the position.

[0544] For example, the gap P9a between a pair of third scan stage circuits SST33 and SST34 may be set to be different from the gap P9b between a pair of third scan stage circuits SST31 and SST32.

[0545] Specifically, the gap P9b between a pair of third scan stage circuits SST31 and SST32 may be set to be larger than the gap P9a between a pair of third scan stage circuits SST33 and SST34.

[0546] Compared with a pair of third scan stage circuits SST33 and SST34, a pair of third scan stage circuits SST31 and SST32 can be located farther from the first peripheral region NA1.

[0547] In other words, the farther the gap P9 between adjacent third scan stage circuits SST31 to SST310 is from the first peripheral region NA1, the larger the gap P9 can become.

[0548] In addition, compared with the first scan stage circuits SST11 to SST16, the third scan stage circuits SST31 to SST310 can have a predetermined slope. For example, the farther the third scan stage circuits SST31 to SST310 are from the first peripheral region NA1, the larger the slope can become.

[0549] The third emission stage EST31 to EST310 can be arranged in a manner substantially similar to that of the third scan stage circuits SST31 to SST310.

[0550] For example, the gap P10 between adjacent third emission stages EST31 to EST310 can be set to be larger than the gap P3 between adjacent first emission stage circuits EST11 to EST16.

[0551] In addition, the gap P10 between adjacent third emission stages EST31 to EST310 can be set to be different from each other according to the position.

[0552] For example, the gap P10a between a pair of third emission stages EST33 and EST34 can be set to be different from the gap P10b between a pair of third emission stages EST31 and EST32.

[0553] Specifically, the gap P10b between a pair of third emission stages EST31 and EST32 can be set to be larger than the gap P10a between a pair of third emission stages EST33 and EST34.

[0554] Compared with a pair of third emission stages EST33 and EST34, a pair of third emission stages EST31 and EST32 can be located farther from the first peripheral region NA1.

[0555] In other words, the farther the gap P10 between adjacent third emission stages EST31 to EST310 is from the first peripheral region NA1, the larger the gap P10 can become.

[0556] In addition, compared with the first emission stage circuits EST11 to EST16, the third emission stage circuits EST31 to EST310 can have a predetermined slope. For example, the farther the third emission stage circuits EST31 to EST310 are from the first peripheral region NA1, the larger the slope can become.

[0557] The third scan stage circuits SST31 to SST310 can be electrically connected to the third scan lines S31 to S310 through the third scan wirings R51 to R510.

[0558] In this case, since the corners of the third pixel region AA3 are set to have a curved shape, the lengths of the third scan wirings R51 to R510 can be set to be greater than the lengths of the first scan wirings R11 to R16.

[0559] According to one embodiment, the connection points between the third scan wirings R51 to R510 and the third scan lines S31 to S310 can be located within the third pixel region AA3.

[0560] The third emission stage circuits EST31 to EST310 can be electrically connected to the third emission control lines E31 to E310 through the third emission wirings R61 to R610.

[0561] In this case, since the corners of the third pixel region AA3 are set to have a curved shape, the lengths of the third emission wirings R61 to R610 can be set to be greater than the lengths of the first emission wirings R31 to R36.

[0562] According to one embodiment, the connection points between the third emission wirings R61 to R610 and the first emission control lines E31 to E310 can be located within the third pixel region AA3.

[0563] In addition, although not shown separately, the third scan stage circuits SST31 to SST310 and the third emission stage circuits EST31 to EST310 can be set in a substantially similar manner as Figure 6A and Figure 6B shown.

[0564] Figure 21 is a diagram showing the layout structure of a dummy stage circuit according to an embodiment of the present disclosure.

[0565] Specifically, Figure 21 shows the shapes of the dummy stage circuits DSST and DEST provided in Figure 20 the embodiment shown.

[0566] As Figure 21 shown, the third scan driver 230 may further include a dummy scan stage circuit DSST located in the third peripheral region NA3.

[0567] For example, the dummy scan stage circuit DSST can be located between the third scan stage circuits SST31 to SST310, and the number of the dummy scan stage circuits DSST can be set to be different from each other according to the position.

[0568] For example, the number of dummy scan stage circuits DSST located between a pair of third scan stage circuits SST33 and SST34 may be different from the number of dummy scan stage circuits DSST located between a pair of third scan stage circuits SST31 and SST32.

[0569] Specifically, the number of dummy scan stage circuits DSST located between a pair of third scan stage circuits SST31 and SST32 may be set to be more than the number of dummy scan stage circuits DSST located between a pair of third scan stage circuits SST33 and SST34.

[0570] Compared with a pair of third scan stage circuits SST33 and SST34, a pair of third scan stage circuits SST31 and SST32 may be located farther from the first peripheral region NA1.

[0571] The dummy scan stage circuit DSST may have the same circuit structure as the third scan stage circuits SST31 to SST310, but may not be connected to the clock lines 245 and 246. Therefore, the output operation of the scan signal may not be performed.

[0572] In addition, the third transmission driver 330 may further include a dummy transmission stage circuit DEST located in the third peripheral region NA3.

[0573] For example, the dummy transmission stage circuit DEST may be located between the third transmission stage circuits EST31 to EST310, and the number of dummy transmission stage circuits DEST may be set differently according to the position.

[0574] For example, the number of dummy transmission stage circuits DEST located between a pair of third transmission stage circuits EST33 and EST34 may be different from the number of dummy transmission stage circuits DEST located between a pair of third transmission stage circuits EST31 and EST32.

[0575] Specifically, the number of dummy transmission stage circuits DEST located between the first pair of third transmission stage circuits EST31 and EST32 may be set to be more than the number of dummy transmission stage circuits DEST located between a pair of third transmission stage circuits EST33 and EST34.

[0576] Compared with a pair of third transmission stage circuits EST33 and EST34, a pair of third transmission stage circuits EST31 and EST32 may be located farther from the first peripheral region NA1.

[0577] The dummy emission stage circuit DEST may have the same circuit structure as the third emission stage circuits EST31 to EST310, but may not be connected to the clock lines 247 and 248, and thus may not perform the output operation of the emission control signal.

[0578] Meanwhile, although not shown separately, the third scan stage circuits SST31 to SST310, the third emission stage circuits EST31 to EST310, and the dummy emission stage circuit DEST may be arranged in a substantially similar manner as in Figure 9A and Figure 9B are set.

[0579] Those skilled in the art of the present disclosure will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical spirit or basic features. Therefore, it should be understood that the above embodiments are merely exemplary and not restrictive. The scope of the present disclosure is defined by the scope of the described claims (rather than the above description). In addition, it should be understood that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts are included in the scope of the present disclosure.

Claims

1. A display device, comprising: The first pixel is configured to be located in a first pixel region and to be connected to a first scan line; The first scan stage circuit is configured to be located in a first peripheral region provided outside the first pixel region and to supply a first scan signal to the first scan line; The second pixel is configured to be located in a second pixel region and to be connected to a second scan line; The second scan stage circuit is configured to be located in a second peripheral region provided outside the second pixel region and to supply a second scan signal to the second scan line; And The dummy scan stage circuit is configured to be located between adjacent second scan stage circuits.

2. The display device according to claim 1, wherein The number of the dummy scan stage circuits is set differently according to the position.

3. The display device according to claim 2, wherein The second scan stage circuit includes a first pair of adjacent second scan stage circuits and a second pair of adjacent second scan stage circuits, wherein the dummy scan stage circuit includes: At least one first dummy scan stage circuit is provided between the first pair of adjacent second scan stage circuits; And The second dummy scan stage circuit is provided between the second pair of adjacent second scan stage circuits, and wherein the number of the second dummy scan stage circuits is greater than the number of the first dummy scan stage circuits.

4. The display device according to claim 3, wherein The second pair of adjacent second scan stage circuits is farther from the first peripheral area than the first pair of adjacent second scan stage circuits.

5. A display device, comprising: The first pixel is configured to be located in a first pixel region; The second pixel is configured to be located in a second pixel region; The first emission stage circuit is configured to be located in a first peripheral region and to supply a first emission control signal to the first pixel through a first emission control line; The second emission stage circuit is configured to be located in a second peripheral region and to supply a second emission control signal to the second pixel through a second emission control line; And The dummy emission stage circuit is configured to be located between adjacent second emission stage circuits.

6. The display device according to claim 5, wherein The number of the dummy emission stage circuits is set differently according to the position.

7. The display device according to claim 6, wherein the second emission stage circuit includes a first pair of adjacent second emission stage circuits and a second pair of adjacent second emission stage circuits, wherein the dummy emission stage circuit includes: At least one first dummy emission stage circuit is provided between the first pair of adjacent second emission stage circuits; And The second dummy emission stage circuit is provided between the second pair of adjacent second emission stage circuits, and wherein the number of the second dummy emission stage circuits is greater than the number of the first dummy emission stage circuits.

8. The display device according to claim 7, wherein The second pair of adjacent second emission stage circuits are farther from the first peripheral region than the first pair of adjacent second emission stage circuits.

9. A display device, comprising: The first scan stage circuit is located in a first peripheral region and is configured to supply a first scan signal to a first scan line, wherein the first scan stage circuit is arranged in a first direction; The second scan stage circuit is located in a second peripheral region and is configured to supply a second scan signal to a second scan line, wherein the second scan stage circuit is arranged deviating from the first direction; And The dummy scan stage circuit is located between adjacent second scan stage circuits.

10. The display device according to claim 9, wherein at least some of the second scan stage circuits have a slope with respect to a second direction intersecting the first direction, and wherein the first scan stage circuit has no slope with respect to the second direction.

11. The display device according to claim 9, wherein the number of dummy scan stage circuits is set differently according to the position.

12. The display device according to claim 11, wherein the second scan stage circuit includes a first pair of adjacent second scan stage circuits and a second pair of adjacent second scan stage circuits, wherein the dummy scan stage circuit includes: At least one first dummy scan stage circuit is provided between the first pair of adjacent second scan stage circuits; And The second dummy scan stage circuit is provided between the second pair of adjacent second scan stage circuits, and wherein the number of the second dummy scan stage circuits is greater than the number of the first dummy scan stage circuits.

13. The display device according to claim 12, wherein the second pair of adjacent second scan stage circuits are farther from the first peripheral region than the first pair of adjacent second scan stage circuits.

14. A display device, comprising: The first emission stage circuit is located in a first peripheral region and is configured to supply a first emission control signal to a first emission control line, wherein the first emission stage circuit is arranged in a first direction; The second emission stage circuit is located in a second peripheral region and is configured to supply a second emission control signal to a second emission control line, wherein the second emission stage circuit is arranged deviating from the first direction; And Dummy emitter circuit, located between adjacent second emitter circuits.

15. The display device according to claim 14, wherein at least some of the second emission stage circuits have a slope with respect to a second direction intersecting the first direction, and wherein the first emission stage circuit has no slope with respect to the second direction.

16. The display device according to claim 14, wherein the number of dummy emission stage circuits is set differently according to the position.

17. The display device according to claim 16, Wherein the second emission stage circuit includes a first pair of adjacent second emission stage circuits and a second pair of adjacent second emission stage circuits, Wherein the dummy emission stage circuit includes: At least one first dummy emitter circuit, disposed between the first pair of adjacent second emitter circuits; And A second dummy emitter circuit, disposed between the second pair of adjacent second emitter circuits, and wherein the number of the second dummy emitter circuits is more than the number of the first dummy emitter circuits.

18. The display device according to claim 17, wherein the second pair of adjacent second emission stage circuits is farther from the first peripheral region than the first pair of adjacent second emission stage circuits.

19. A display device, comprising: A first scan stage circuit, located in a first peripheral region and configured to supply a first scan signal to a first scan line, wherein the first scan stage circuit is arranged in a first direction; A second scan stage circuit, located in a second peripheral region and configured to supply a second scan signal to a second scan line, wherein the second scan stage circuit is arranged deviating from the first direction, and a gap between adjacent second scan stage circuits is different from a gap between adjacent first scan stage circuits; and At least one dummy scan stage circuit, located between the adjacent second scan stage circuits.

20. The display device according to claim 19, wherein at least some of the second scan stage circuits have a slope with respect to a second direction intersecting the first direction, and wherein the first scan stage circuit has no slope with respect to the second direction.

21. The display device according to claim 19, wherein the gap between the adjacent second scan stage circuits is greater than the gap between the adjacent first scan stage circuits.

22. The display device according to claim 19, wherein the second scan stage circuit includes a first pair of adjacent second scan stage circuits and a second pair of adjacent second scan stage circuits, and wherein the gap between the second pair of adjacent scan stage circuits is greater than the gap between the first pair of adjacent scan stage circuits.

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