A manufacturing method of an array substrate capable of reducing touch capacitance

Abstract

The application discloses a manufacturing method of an array substrate capable of reducing touch capacitance, which comprises the following steps: sequentially forming a buffer layer SiOx, an active layer, an etching stop layer ES and a metal layer GE, including a gate electrode and a touch layer CM, on a glass by patterning; depositing an insulating protective layer PV; coating an organic flat layer OC and patterning an OC hole; performing exposure / development / etching processes by using an ES mask to pattern an ES hole; patterning a metal layer SD on the OC layer and connecting the metal layer SD with the SE through the ES hole, and patterning a metal pad layer at the touch layer CM; depositing an insulating layer VA to form a VA hole; and depositing a pixel electrode PE and connecting the pixel electrode PE with a source / drain metal layer through a CH hole. The application reduces the touch capacitance and improves the receiving degree of an active pen signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of display device manufacturing, and particularly relates to a method for manufacturing an array substrate capable of reducing touch capacitance. Background Art

[0002] IGZO is an amorphous oxide containing indium, gallium, and zinc. Its carrier mobility is 20 to 30 times that of amorphous silicon. This significantly increases the charge and discharge rates of the TFT pixel electrode, improving pixel response speed and enabling faster panel refresh rates, enabling ultra-high-resolution TFT-LCDs. Existing amorphous silicon production lines require only minor modifications to be compatible with the IGZO process, making it more cost-competitive than low-temperature polycrystalline silicon (LTPS).

[0003] The existing In-Cell technology refers to a method of embedding touch panel functions into liquid crystal pixels, thereby realizing an integrated design of touch panel components and liquid crystal panels. In terms of the array process, transparent materials such as ITO are used as the film layer of the common electrode and pixel electrode, and the charging and discharging of pixels are carried out by overlapping the source and drain metal layers through the CH hole. The existing stylus pens used in touch screens mainly include passive pens and active pens. The working principle of the active pen is that when the active pen contacts the conventional touch screen, the touch electrode on the touch screen will receive a pulse signal of a specific frequency emitted by the active pen, thereby identifying the position of the active pen on the touch screen. The touch panel using the existing Midcom In-cell technology just meets the existing active pen design requirements. However, if the touch electrode is used as the receiving electrode for the active pen signal, since the RC Loading on the existing touch electrode is very large, the active pen signal reaches the touch electrode due to severe signal attenuation, which can easily lead to the inability to realize the active pen function. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing an array substrate capable of reducing touch capacitance, which not only reduces the RC loading of the touch electrode, but also avoids the attenuation of the active pen signal and improves the response speed of the device.

[0005] The present invention is achieved in that:

[0006] A method for manufacturing an array substrate capable of reducing touch capacitance comprises the following steps:

[0007] Step 1: Pattern a buffer layer SiOx on the glass in sequence;

[0008] Step 2: Pattern forms the active layer;

[0009] Step 3: depositing an etch stop layer ES;

[0010] Fourth step: Pattern the metal layer GE, including the gate electrode and the touch layer CM;

[0011] Fifth step: Deposit an insulating protective layer PV;

[0012] Sixth step: Apply an organic flat layer OC on the TFT device, and pattern the OC hole;

[0013] Seventh step: Perform exposure / development / etching process using the ES mask to pattern the ES hole;

[0014] Eighth step: Pattern a metal layer SD on the OC layer, and connect it with SE through the ES hole, and pattern a metal pad layer at the touch layer CM;

[0015] Ninth step: Deposit an insulating layer VA, and pattern the VA hole;

[0016] Tenth step: Deposit a common electrode layer BC, and pattern it to be connected with the touch metal layer through the VA hole;

[0017] Eleventh step: Deposit an insulating layer CH on the BC hole, and pattern the CH hole;

[0018] Twelfth step: Deposit a pixel electrode layer PE, and pattern it to be connected with the source-drain metal layer through the CH hole.

[0019] Further, the active layer SE is IGZO.

[0020] Further, the metal layer GE is Mo / Al / Mo or Ti / Al / Ti.

[0021] Further, the insulating layer PV is SiOx.

[0022] Further, the source-drain layer SD is Ti / Al / Ti.

[0023] Further, the insulating layer VA is SiOx or SiNx.

[0024] Further, the common electrode layer BC is ITO.

[0025] Further, the insulating layer CH is SiOx or SiNx.

[0026] Further, the pixel electrode layer PE is ITO.

[0027] The application has the advantages that: by designing GE and CM common mask, designing CM below OC layer, designing data metal line SD above OC layer, patterning SD as metal pad layer at VA hole position, eliminating the risk of ITO broken line, not only improving the response speed of TFT, but also reducing the touch capacitance, improving the reception of active pen signal. BRIEF DESCRIPTION OF DRAWINGS

[0028] The application will be further described below with reference to the accompanying drawings and embodiments.

[0029] Figure 1 is the first step structure schematic diagram of the application.

[0030] Figure 2 is the second step structure schematic diagram of the application.

[0031] Figure 3 is the third step structure schematic diagram of the application.

[0032] Figure 4 is the fourth step structure schematic diagram of the application.

[0033] Figure 5 is the fifth step structure schematic diagram of the application.

[0034] Figure 6 is the sixth step structure schematic diagram of the application.

[0035] Figure 7 is the seventh step structure schematic diagram of the application.

[0036] Figure 8 is the eighth step structure schematic diagram of the application.

[0037] Figure 9 is the ninth step structure schematic diagram of the application.

[0038] Figure 10 is the tenth step structure schematic diagram of the application.

[0039] Figure 11 is the eleventh step structure schematic diagram of the application.

[0040] Figure 12 is the twelfth step structure schematic diagram of the application. DETAILED DESCRIPTION

[0041] As shown in the figure, a manufacturing method of array substrate capable of reducing touch capacitance comprises the following steps: Figures 1 to 12

[0042] First step: sequentially pattern forming buffer layer SiOx-2 on Glass;

[0043] ​Second step: Pattern active layer-3;

[0044] Third step: Deposition of an etching stop layer ES-4, temporarily not Pattern;

[0045] Fourth step: Pattern metal layer GE-5, including gate-51, touch layer CM-52;

[0046] Fifth step: Deposition of an insulating protective layer PV-6;

[0047] Sixth step: Coating an organic flat layer OC-7 on the TFT device, and Pattern OC hole;

[0048] Seventh step: Exposure / development / etching process using ES mask, Pattern ES hole;

[0049] Eighth step: Pattern a metal layer SD-8 on the OC layer, and connect with SE through ES hole, and Pattern metal pad layer at touch layer CM;

[0050] Ninth step: Deposition of an insulating layer VA-9, and Pattern VA hole;

[0051] Tenth step: Deposition of a common electrode BC-10, and Pattern through VA hole and touch metal layer;

[0052] Eleventh step: Deposition of an insulating layer CH-11 on BC hole, and Pattern CH hole;

[0053] Twelfth step: Deposition of a pixel electrode PE-12, and Pattern through CH hole and source / drain metal layer.

[0054] Explanation of layer code:

[0055] Glass: Array (array) side substrate glass, the basic component of display device, on which active devices such as TFT are sequentially formed;

[0056] Buffer layer: between glass and active layer IGZO, generally inorganic insulating layer SiOx;

[0057] SE: active layer, TFT device semiconductor layer, such as a-Si, MOx and LTPS, etc., IGZO can be selected in the present application;

[0058] ES / GI: the present application is top gate self-alignment design, so the layer is actually GI layer, but an ES mask will be designed, and SiOx can be selected in this scheme;

[0059] GE / CM: Gate-51, Metal1 metal layer, touch metal layer CM-52, Metal3 metal layer, the application is common mask for both, Mo / Al / Mo or Ti / Al / Ti can be selected here;

[0060] PV: Insulating layer, insulating layer with large dielectric constant, SiOx can be selected in the application, mainly used for blocking water and oxygen to avoid affecting the stability of TFT device;

[0061] OC: Organic planar layer, mainly organic material, covered on the insulating layer, used for planarizing the surface of TFT device;

[0062] SD: Source and drain, Metal2 metal layer, Ti / Al / Ti here;

[0063] VA: Insulating layer, insulating layer with large dielectric constant, SiOx or SiNx can be selected in the application, VA hole is dry etched, which is convenient for the connection of common electrode BC and touch metal layer CM;

[0064] BC: Common electrode layer ITO;

[0065] CH: Insulating layer, insulating layer with large dielectric constant, SiOx or SiNx can be selected in the application, which is convenient for the connection of pixel electrode PE and source and drain SD;

[0066] PE: Pixel electrode layer ITO.

[0067] The application designs GE and CM common mask, designs CM below OC layer and data metal line SD above OC layer, and SD is also patterned as a metal pad layer at the position of VA hole, which eliminates the risk of ITO easy broken line, not only improves the response speed of TFT, but also reduces the touch capacitance and improves the reception degree of active pen signal.

[0068] The above only describes the preferred embodiments of the application, and is not used to limit the protection scope of the application. Any modification, equivalent replacement and improvement within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A method for manufacturing an array substrate capable of reducing touch capacitance, characterized in that: The steps include: Step 1: Sequentially patterning a buffer layer SiOx on the glass; Step 2: Patterning to form the active layer SE; Step 3: depositing an etch stop layer ES; Step 4: Patterning to form a metal layer GE, including a gate and a touch layer CM; Step 5: Deposit an insulating protective layer PV; Step 6: Coat an organic planar layer (OC) on the TFT device and pattern the OC holes; Step 7: Use ES mask to perform exposure, development and etching processes to pattern ES holes; Step 8: Patterning a metal layer SD on the organic planar layer OC and connecting it to the active layer SE through the ES hole, and patterning a metal pad layer on the touch layer CM; Step 9: depositing an insulating layer VA and patterning it to form VA holes; Step 10: deposit a common electrode BC and pattern it through the VA hole to overlap the metal layer SD; Step 11: depositing an insulating layer CH on the BC hole and patterning it to form a CH hole; Step 12: deposit a layer of pixel electrode PE, and pattern it through the CH hole to overlap with the metal layer SD.

2. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The active layer SE is IGZO.

3. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The metal layer GE is Mo / Al / Mo or Ti / Al / Ti.

4. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The insulating protective layer PV is SiOx.

5. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The metal layer SD is Ti / Al / Ti.

6. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The insulating layer VA is SiOx or SiNx.

7. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The common electrode BC is ITO.

8. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The insulating layer CH is SiOx or SiNx.

9. The method for manufacturing an array substrate capable of reducing touch capacitance according to claim 1, wherein: The pixel electrode PE is made of ITO.

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