CMOS structure and method of forming the same

Abstract

This application provides a CMOS structure and its formation method. The formation method includes: providing a semiconductor substrate, on the surface of which alternately distributed PMOS channel layers and NMOS trenches penetrating the PMOS channel layers are formed; forming an NMOS channel material layer on the surface of the PMOS channel layers and in the NMOS trenches, wherein the surface of the NMOS channel material layer has a recess; filling the recesses with a sacrificial layer, wherein the surfaces of the sacrificial layer and the NMOS channel material layer are coplanar; removing the sacrificial layer and a portion of the NMOS channel material layer; forming a protective layer on the surface of the PMOS channel layers; and forming an NMOS channel layer in the NMOS trenches, wherein the surfaces of the protective layer and the NMOS channel layer are coplanar. The formation method of this application effectively avoids problems such as lattice damage, scratches, and poor thickness uniformity on the surface of the PMOS channel layer, thereby improving device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing, and in particular to a CMOS structure and a method for forming the same. Background Technology

[0002] With the increasing integration of semiconductor devices, the critical dimensions of transistors are continuously shrinking, making the design of three-dimensional structures such as FinFETs a hot topic in the field. A FinFET is an emerging multi-gate device, typically featuring multiple thin fins extending vertically upwards from the substrate. The channel of the FinFET is formed within these fins, and the gate structure is formed on the fins. Active and drain regions are formed in the fins on either side of the gate structure. By epitaxially growing SiGe in the source / drain regions, compressive stress can be applied to the pFET channel, effectively improving the pFET channel carrier mobility and enhancing device performance.

[0003] As semiconductor manufacturing technology nodes continue to shrink, the limitations of improving channel carrier mobility through strain engineering have become apparent. Therefore, inducing strain during channel formation itself has become an effective method to improve device performance. In pFETs (p-channel MOSFETs), replacing Si with Si to form a SiGe / Si dual-channel has proven to be an effective way to improve device performance.

[0004] When forming SiGe channels, excess SiGe material layers are usually removed. Currently, chemical mechanical polishing (CMP) is mostly used for this process. However, the resulting SiGe channel surface is prone to problems such as lattice damage, scratches, and poor thickness uniformity, which affect device performance. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide a CMOS structure and its formation method, which can effectively avoid problems such as lattice damage, scratches and poor thickness uniformity on the surface of PMOS channel layer, and improve device performance.

[0006] To address the aforementioned technical problems, this application provides a method for forming a CMOS structure, comprising: providing a semiconductor substrate, wherein alternating PMOS channel layers and NMOS trenches penetrating the PMOS channel layers are formed on the surface of the semiconductor substrate; forming an NMOS channel material layer on the surface of the PMOS channel layers and in the NMOS trenches, wherein the surface of the NMOS channel material layer has a recess; filling the recesses with a sacrificial layer, wherein the surfaces of the sacrificial layer and the NMOS channel material layer are coplanar; removing the sacrificial layer and a portion of the NMOS channel material layer; forming a protective layer on the surface of the PMOS channel layers; forming an NMOS channel layer in the NMOS trenches, wherein the surfaces of the protective layer and the NMOS channel layer are coplanar.

[0007] In this embodiment, the process of forming the PMOS channel layer and the NMOS trench includes: sequentially forming a PMOS channel material layer and a mask layer on the surface of the semiconductor substrate, wherein the mask layer includes a pattern defining the NMOS trench; and etching the PMOS channel material layer to form the PMOS channel layer and the NMOS trench.

[0008] In the embodiments of this application, the material of the mask layer includes silicon oxide and / or silicon nitride.

[0009] In this embodiment, the PMOS channel layer is made of silicon germanide, and the NMOS channel material layer is made of monocrystalline silicon.

[0010] In this embodiment, the process for forming the NMOS channel material layer includes at least one of epitaxial growth, atomic layer deposition, and chemical vapor deposition.

[0011] In this embodiment of the application, the process of filling the recess with a sacrificial layer includes: forming a sacrificial material layer on the surface of the NMOS channel material layer, and the sacrificial material layer filling the recess; planarizing the sacrificial material layer and stopping it on the NMOS channel material layer to form the sacrificial layer.

[0012] In this embodiment of the application, when the sacrificial material layer is planarized using a chemical mechanical polishing (CMP) process, the polishing rate of the sacrificial material layer is greater than the polishing rate of the NMOS channel material layer.

[0013] In this embodiment, the material of the sacrificial layer includes at least one of silicon oxide, silicon nitride, and polycrystalline silicon.

[0014] In this embodiment, the process for removing the sacrificial layer and part of the NMOS channel material layer includes dry etching and / or chemical mechanical polishing.

[0015] In this embodiment, the dry etching process has the same etching rate for the sacrificial layer and the NMOS channel material layer.

[0016] In this embodiment, the chemical mechanical polishing process applies the same polishing rate to both the sacrificial layer and the NMOS channel material layer.

[0017] In this embodiment of the application, after forming the protective layer and the channel layer, the method further includes etching portions of the protective layer, the PMOS channel layer, the NMOS channel layer and the semiconductor substrate to form alternately distributed PMOS fins and NMOS fins.

[0018] To address the aforementioned technical problems, this application also provides a CMOS structure, comprising: a semiconductor substrate; PMOS fins and NMOS fins, alternately distributed on the semiconductor substrate, wherein the PMOS fins include a PMOS channel layer and a protective layer stacked sequentially, and the NMOS fins include an NMOS channel layer; wherein the surfaces of the protective layer and the NMOS channel layer are coplanar, and the protective layer and the NMOS channel layer are made of the same material.

[0019] In this embodiment, the PMOS channel layer is made of silicon germanide, and the protective layer and the NMOS channel layer are made of monocrystalline silicon.

[0020] Compared with the prior art, the CMOS structure and its formation method of the present application have the following advantages:

[0021] The CMOS structure formation method of this application involves first forming a PMOS channel layer and an NMOS trench on the surface of a semiconductor substrate. The PMOS channel layer is no longer formed by chemical mechanical polishing, thus effectively avoiding the problems of lattice damage, scratches, and poor thickness uniformity on the surface of the PMOS channel layer caused by chemical mechanical polishing in the prior art.

[0022] Then, an NMOS channel material layer is formed on the surface of the PMOS channel layer and in the NMOS trench. The surface of the formed NMOS channel material layer will have depressions, and a sacrificial layer is filled in the depressions. By introducing the sacrificial layer, it is beneficial for subsequent processes to remove part of the NMOS channel material layer to form the NMOS channel layer. This is because removing the NMOS channel material layer with the depression structure will result in poor thickness uniformity of the formed NMOS channel layer, while the added sacrificial layer can fill the depressions, which is beneficial to obtaining an NMOS channel layer with better thickness uniformity and improving device performance.

[0023] Since the surface of the PMOS channel layer in this application has an NMOS channel material layer, when the sacrificial layer and part of the NMOS channel material layer are removed, the NMOS channel material layer plays a role in protecting the surface of the PMOS channel layer and avoiding damage to the surface of the PMOS channel layer during the removal process.

[0024] When removing the sacrificial layer and part of the NMOS channel material layer, no new materials or processes are introduced. Therefore, existing process platforms can be utilized, reducing technical difficulty and saving costs. Moreover, while forming the NMOS channel layer, a protective layer is also formed on the surface of the formed PMOS channel layer, eliminating the step of forming a protective layer in the prior art, simplifying the process flow and reducing costs. Attached Figure Description

[0025] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a CMOS structure.

[0027] Figure 6 This is a flowchart illustrating a method for forming a CMOS structure according to an embodiment of this application.

[0028] Figures 7-13 This is a schematic diagram of the structure corresponding to each step in the method for forming a CMOS structure according to an embodiment of this application. Detailed Implementation

[0029] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0030] refer to Figure 1 and Figure 2A method for forming a CMOS structure includes: providing a semiconductor substrate 10, wherein an oxide layer 20 and a mask layer 30 are sequentially formed on the surface of the semiconductor substrate 10, and the mask layer 30 is made of silicon nitride. In some prior art, only the oxide layer 20 may be formed. The oxide layer 20, the mask layer 30, and the semiconductor substrate 10 are etched to form a trench 40, the trench 40 defining the channel layer of a PMOS, and the oxide layer 20 and the mask layer 30 defining the channel layer of an NMOS.

[0031] refer to Figure 3 and Figure 4 A SiGe layer 50 is formed in the trench 40, and the SiGe layer 50 is used to form the channel layer of the PMOS. Due to the contour of the trench 40, the surface of the formed SiGe layer 50 has depressions. The oxide layer 20 and the mask layer 30 are removed by processes such as chemical-mechanical planarization (CMP), and the SiGe layer 50 is planarized to form the PMOS channel layer 51. However, the surface of the formed PMOS channel layer 51 may have many defects, such as lattice damage, scratches, and poor thickness uniformity, resulting in poor device performance.

[0032] refer to Figure 5 Since the surface of the PMOS channel layer 51 is exposed, a protective layer 60 (Sicap) is formed on the surface of the PMOS channel layer 51 to protect it from damage by subsequent processes. This adds an extra process step and increases the cost.

[0033] In view of this, the present application provides a CMOS structure and its formation method, which abandons the previous approach of forming a PMOS channel layer through SiGeCMP process. By forming a PMOS channel layer and an NMOS trench on the surface of a semiconductor substrate, the problem of defects on the surface of the PMOS channel layer in the prior art is solved. An NMOS channel material layer is formed on the surface of the PMOS channel layer and in the NMOS trench, and a sacrificial layer is filled in the depression on the surface of the NMOS channel material layer. The sacrificial layer and the surface of the NMOS channel material layer are coplanar, which is beneficial for subsequent processes to remove part of the NMOS channel material layer to form an NMOS channel layer with better thickness uniformity. At the same time as forming the NMOS channel layer, a protective layer is also formed on the surface of the PMOS channel layer, thus eliminating the step of forming a protective layer in the prior art.

[0034] The CMOS structure and its formation method of the present application are described in detail below with reference to specific embodiments and accompanying drawings.

[0035] refer to Figure 6The method for forming a CMOS structure according to embodiments of this application mainly includes:

[0036] Step S1: Provide a semiconductor substrate, wherein alternating PMOS channel layers and NMOS trenches penetrating the PMOS channel layers are formed on the surface of the semiconductor substrate;

[0037] Step S2: An NMOS channel material layer is formed on the surface of the PMOS channel layer and in the NMOS trench, wherein the surface of the NMOS channel material layer has a recess;

[0038] Step S3: Fill the recess with a sacrificial layer, and the surfaces of the sacrificial layer and the NMOS channel material layer are coplanar;

[0039] Step S4: Remove the sacrificial layer and part of the NMOS channel material layer, form a protective layer on the surface of the PMOS channel layer, form an NMOS channel layer in the NMOS trench, and the surfaces of the protective layer and the NMOS channel layer are coplanar.

[0040] Combination Figure 6 and Figure 7 A semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SiI), or germanium-on-insulator, etc. It may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide. In this embodiment, the semiconductor substrate 100 is made of silicon.

[0041] A PMOS channel material layer 200 and a mask material layer 300 are sequentially formed on the surface of the semiconductor substrate 100. The PMOS channel material layer 200 can be formed by epitaxial growth, and the mask material layer 300 can be formed by chemical vapor deposition, furnace tube deposition, or atomic layer deposition, etc. The material of the PMOS channel material layer 200 may include silicon germanide (SiGe), and the material of the mask material layer 300 may include at least one of silicon oxide and silicon nitride. The PMOS channel material layer 200 is used to form the PMOS channel layer, and the mask material layer 300 is used to pattern the PMOS channel material layer 200.

[0042] refer to Figure 8 The mask material layer 300 is etched to form a mask layer 310, the mask layer 310 including a pattern defining an NMOS trench; using the mask layer 310 as a mask, the PMOS channel material layer 200 is etched to form the PMOS channel layer 210 and the NMOS trench 400, wherein the NMOS trench 400 is used to form the NMOS channel layer.

[0043] refer to Figure 9 The mask layer 310 is removed, and an NMOS channel material layer 500 is formed on the surface of the PMOS channel layer 210 and in the NMOS trench 400. The NMOS channel material layer 500 can be formed using at least one of epitaxial growth, atomic layer deposition, and chemical vapor deposition processes. Due to the contour of the NMOS trench 400, the surface of the final NMOS channel material layer 500 has a depression 501. The material of the NMOS channel material layer 500 includes, for example, single-crystal silicon.

[0044] refer to Figure 10 A sacrificial material layer 600 is formed on the surface of the NMOS channel material layer 500, filling the depression 501. The sacrificial material layer 600 can be formed using furnace tube deposition, chemical vapor deposition, atomic layer deposition, etc. The material of the sacrificial material layer 600 can include at least one of silicon oxide, silicon nitride, and polysilicon. The function of the sacrificial material layer 600 is to fill the depression 501, so that a relatively smooth surface can be obtained after subsequent polishing of the NMOS channel material layer 500, which is beneficial to the formation of other subsequent film layers.

[0045] refer to Figure 11 The sacrificial material layer 600 is planarized and stopped on the NMOS channel material layer 500 to form the sacrificial layer 610. The surfaces of the formed sacrificial layer 610 and the NMOS channel material layer 500 are coplanar. The planarization of the sacrificial material layer 600 can be performed using a CMP process. The CMP process has a higher polishing rate on the sacrificial material layer 600 than on the NMOS channel material layer 500. Furthermore, planarizing the sacrificial material layer 600 and stopping on the NMOS channel material layer 500 is a relatively mature process technology, thus allowing for a lower loading surface.

[0046] refer to Figure 12The sacrificial layer 610 and a portion of the NMOS channel material layer 500 are removed to make the surface of the remaining NMOS channel material layer 500 relatively smooth. In some embodiments, a dry etching process and / or a CMP process can be used to remove the sacrificial layer 610 and a portion of the NMOS channel material layer 500. In some embodiments, a dry etching process is used to remove the sacrificial layer 610 and a portion of the NMOS channel material layer 500, and the dry etching process etches the sacrificial layer 610 and the NMOS channel material layer 500 at the same rate. In some embodiments, a CMP process is used to remove the sacrificial layer 610 and a portion of the NMOS channel material layer 500, and the CMP process etches the sacrificial layer 610 and the NMOS channel material layer 500 at the same polishing rate.

[0047] The remaining NMOS channel material layers 500 have fundamentally different functions due to their different positions. The NMOS channel material layer 500 located in the NMOS trench serves as the NMOS channel layer 710, while the NMOS channel material layer 500 located on the surface of the PMOS channel layer 210 serves as a protective layer 720, used to protect the surface of the PMOS channel layer 210 from damage in subsequent processes. Therefore, the formation method of this embodiment eliminates the step of forming a protective layer in the prior art, simplifying the process flow and reducing costs.

[0048] In some embodiments, after forming the NMOS channel layer 710 and the protective layer 720, the step of forming PMOS fins and NMOS fins is further included.

[0049] refer to Figure 13 The protective layer 720, PMOS channel layer 210, NMOS channel layer 710 and semiconductor substrate 100 are etched to form alternately distributed PMOS fins and NMOS fins.

[0050] Continue to refer to Figure 13 This application also provides a CMOS structure, including: a semiconductor substrate 100; PMOS fins and NMOS fins, alternately distributed on the semiconductor substrate 100, wherein the PMOS fins include a PMOS channel layer 210 and a protective layer 720 stacked sequentially, and the NMOS fins include an NMOS channel layer 710; wherein the surfaces of the protective layer 720 and the NMOS channel layer 710 are coplanar, and the protective layer 720 and the NMOS channel layer 710 are made of the same material.

[0051] In some embodiments, the PMOS channel layer 210 is made of silicon germanide, and the protective layer 720 and the NMOS channel layer 710 are made of monocrystalline silicon.

[0052] The thicknesses of the PMOS channel layer 210, the protective layer 720, and the NMOS channel layer 710 are designed reasonably according to different process nodes.

[0053] The CMOS structure formation method of this application embodiment has good thickness uniformity in the PMOS channel layer and NMOS channel layer, which greatly improves the performance of the device; it eliminates the need for an additional protective layer deposition step (Si cap), simplifying the process flow and reducing costs.

[0054] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0055] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items.

[0056] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0057] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a CMOS structure, characterized in that, include: A semiconductor substrate is provided, wherein alternating PMOS channel layers and NMOS trenches penetrating the PMOS channel layers are formed on the surface of the semiconductor substrate; An NMOS channel material layer is formed on the surface of the PMOS channel layer and in the NMOS trench, and the surface of the NMOS channel material layer has a depression; A sacrificial layer is filled in the recess, and the surfaces of the sacrificial layer and the NMOS channel material layer are coplanar; The sacrificial layer and part of the NMOS channel material layer are removed, a protective layer is formed on the surface of the PMOS channel layer, and an NMOS channel layer is formed in the NMOS trench, wherein the surfaces of the protective layer and the NMOS channel layer are coplanar.

2. The method for forming a CMOS structure according to claim 1, characterized in that, The process for forming the PMOS channel layer and NMOS trench includes: A PMOS channel material layer and a mask layer are sequentially formed on the surface of the semiconductor substrate, wherein the mask layer includes a pattern defining the NMOS trench; The PMOS channel material layer is etched to form the PMOS channel layer and the NMOS trench.

3. The method for forming a CMOS structure according to claim 2, characterized in that, The material of the mask layer includes silicon oxide and / or silicon nitride.

4. The method for forming a CMOS structure according to claim 1, characterized in that, The PMOS channel layer is made of silicon germanide, and the NMOS channel material layer is made of monocrystalline silicon.

5. The method for forming a CMOS structure according to claim 1, characterized in that, The process for forming the NMOS channel material layer includes at least one of epitaxial growth, atomic layer deposition, and chemical vapor deposition.

6. The method for forming a CMOS structure according to claim 1, characterized in that, The process of filling the recess with a sacrificial layer includes: A sacrificial material layer is formed on the surface of the NMOS channel material layer, and the sacrificial material layer fills the depression; The sacrificial material layer is planarized and stopped on the NMOS channel material layer to form the sacrificial layer.

7. The method for forming a CMOS structure according to claim 6, characterized in that, When planarizing the sacrificial material layer using a chemical mechanical polishing (CMP) process, the polishing rate of the sacrificial material layer is greater than the polishing rate of the NMOS channel material layer.

8. The method for forming a CMOS structure according to claim 1, characterized in that, The material of the sacrificial layer includes at least one of silicon oxide, silicon nitride, and polycrystalline silicon.

9. The method for forming a CMOS structure according to claim 1, characterized in that, The process for removing the sacrificial layer and part of the NMOS channel material layer includes dry etching and / or chemical mechanical polishing.

10. The method for forming a CMOS structure according to claim 9, characterized in that, The dry etching process has the same etching rate for the sacrificial layer and the NMOS channel material layer.

11. The method for forming a CMOS structure according to claim 9, characterized in that, The chemical mechanical polishing process applies the same polishing rate to both the sacrificial layer and the NMOS channel material layer.

12. The method for forming a CMOS structure according to claim 1, characterized in that, After forming the protective layer and the channel layer, the process further includes etching portions of the protective layer, the PMOS channel layer, the NMOS channel layer, and the semiconductor substrate to form alternately distributed PMOS fins and NMOS fins.

13. A CMOS structure, characterized in that, Formed using any one of claims 1 to 12, comprising: Semiconductor substrate; PMOS fins and NMOS fins are alternately distributed on the semiconductor substrate, wherein the PMOS fins include a PMOS channel layer and a protective layer stacked sequentially, and the NMOS fins include an NMOS channel layer; The protective layer and the NMOS channel layer have coplanar surfaces, and the protective layer and the NMOS channel layer are made of the same material.

14. The CMOS structure according to claim 13, characterized in that, The PMOS channel layer is made of silicon germanide, and the protective layer and the NMOS channel layer are made of monocrystalline silicon.

Images