Semiconductor structure and method of forming the same
By forming logic and optoelectronic regions on a semiconductor substrate and integrating optoelectronic and logic devices on the same chip using ion implantation and epitaxial growth processes, the problem of not being able to fabricate optoelectronic and logic devices simultaneously has been solved, achieving cost reduction and increased integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-06-11
- Publication Date
- 2026-04-24
AI Technical Summary
Optoelectronic devices and logic devices cannot be fabricated on the same chip at the same time, resulting in high manufacturing costs and low integration.
Logic regions and optoelectronic regions are formed on a semiconductor substrate, and logic devices and optoelectronic devices are formed in the logic regions and optoelectronic regions respectively through ion implantation. PN junctions are formed using different types of doped regions, and the devices are integrated by combining dielectric layers and epitaxial growth processes.
This enables the integration of optoelectronic devices and logic devices on the same chip, reducing manufacturing costs and increasing device integration.
Smart Images
Figure CN115472634B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the development of robotics and autonomous driving technologies, the demand for 3D sensors is rising rapidly. ToF (Time of Flight) technology measures the phase difference of the reflected light after it is reflected by the object being measured by a near-infrared laser, and converts it into the required time difference of flight.
[0003] Currently, in order to improve the infrared light absorption rate of photodiodes, germanium epitaxial wafers (Ge-Epi) are usually used. Moreover, optoelectronic devices can only be made using N-type Ge-Epi. However, N-type Ge-Epi cannot be used to make logic circuits. Therefore, optoelectronic devices and logic devices cannot be made on the same chip at the same time. They must be made separately and then integrated together. Summary of the Invention
[0004] The technical problem this application aims to solve is that optoelectronic devices and logic devices cannot be fabricated simultaneously on the same chip.
[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including adjacent logic regions and optoelectronic regions, wherein logic devices are formed in the logic regions, and a first dielectric layer is formed on the semiconductor substrate of the logic regions and the optoelectronic regions; forming an optoelectronic material layer in the first dielectric layer of the optoelectronic regions, wherein the optoelectronic material layer is coplanar with the surface of the first dielectric layer; and forming optoelectronic devices in the optoelectronic material layer or in the semiconductor substrate below the optoelectronic material layer.
[0006] In this embodiment of the application, the logic device includes a source and a drain located in the semiconductor substrate of the logic region; while the source and drain are formed by a first ion implantation process, a first doped region of the optoelectronic device is formed in the semiconductor substrate of the optoelectronic region.
[0007] In this embodiment of the application, the method for forming the semiconductor structure further includes: forming a second doped region at the same depth as the first doped region in the semiconductor substrate of the photoelectric region using a second ion implantation process, wherein the doping ion types of the first doped region and the second doped region are different.
[0008] In this embodiment of the application, the method for forming the semiconductor structure further includes: etching a portion of the first dielectric layer on the surface of the source and drain, the first doped region and the second doped region to form contact holes for the logic device and the optoelectronic device, respectively.
[0009] In this embodiment of the application, the process of forming an optoelectronic device in the optoelectronic material layer includes: forming a first doped region of the optoelectronic device in the optoelectronic material layer using a first ion implantation process; and forming a second doped region in the optoelectronic material layer at the same depth as the first doped region using a second ion implantation process, wherein the doping ion types of the first doped region and the second doped region are different.
[0010] In this embodiment, the logic device includes a source and a drain located in a semiconductor substrate in the logic region; the method for forming the semiconductor structure further includes: forming a second dielectric layer on the first dielectric layer and the optoelectronic material layer; etching a portion of the second dielectric layer on the first doped region and the second doped region to form a contact hole of the optoelectronic device; and etching a portion of the first dielectric layer and the second dielectric layer on the source and drain to form a contact hole of the logic device.
[0011] In this embodiment, the material of the second dielectric layer includes silicon oxide or silicon nitride.
[0012] In this embodiment of the application, the logic device further includes a gate structure located on the surface of a semiconductor substrate between the source and the drain.
[0013] In this embodiment, the formation process of the optoelectronic material layer includes: etching the first dielectric layer to form an opening in the optoelectronic region for defining the optoelectronic device; growing the optoelectronic material layer on the surface of the first dielectric layer and in the opening using an epitaxial growth process; and planarizing the optoelectronic material layer so that the surface of the optoelectronic material layer is coplanar with the surface of the first dielectric layer.
[0014] In this embodiment, the material of the optoelectronic material layer includes germanium, and the material of the first dielectric layer includes silicon oxide or silicon nitride.
[0015] In this embodiment, an isolation structure is further formed in the semiconductor substrate between the logic region and the photoelectric region.
[0016] This application also provides a semiconductor structure, comprising: a semiconductor substrate including an adjacent logic region and a photoelectric region; a first dielectric layer located on the semiconductor substrate of the logic region and the photoelectric region; a photoelectric material layer located in the first dielectric layer of the photoelectric region, and the surface of the photoelectric material layer is coplanar with that of the first dielectric layer; a logic device located in the logic region; and a photoelectric device located in the photoelectric material layer or in the semiconductor substrate below the photoelectric material layer.
[0017] In this embodiment of the application, the logic device includes a source and a drain in a semiconductor substrate located in the logic region, and the optoelectronic device is located in a semiconductor substrate below the optoelectronic material layer and includes a first doped region. The source and drain and the first doped region have the same type of doped ions and are located at the same depth.
[0018] In this embodiment of the application, the optoelectronic device further includes a second doped region, wherein the doped ion types of the first doped region and the second doped region are different.
[0019] In this embodiment of the application, the semiconductor structure further includes contact holes for the logic device and the optoelectronic device, located in the first dielectric layer, wherein the contact holes for the logic device are connected to the source and the drain, and the contact holes for the optoelectronic device are connected to the first doped region and the second doped region.
[0020] In this embodiment, the optoelectronic device is located in the optoelectronic material layer, including a first doped region and a second doped region, which are located at the same depth but have different doped ion types.
[0021] In this embodiment of the application, the logic device includes a source and a drain located in the semiconductor substrate of the logic region, and the source and drain are of the same dopant ion type as the first doped region.
[0022] In this embodiment of the application, the semiconductor structure further includes: a second dielectric layer, located on the first dielectric layer and the optoelectronic material layer;
[0023] Contact holes for logic devices and optoelectronic devices, wherein the contact holes for logic devices are located in the first dielectric layer and the second dielectric layer and connect the source and the drain, and the contact holes for optoelectronic devices are located in the second dielectric layer and connect the first doped region and the second doped region.
[0024] In this embodiment, the material of the second dielectric layer includes silicon oxide or silicon nitride.
[0025] In this embodiment of the application, the logic device further includes: a gate structure located on the surface of a semiconductor substrate between the source and the drain.
[0026] In this embodiment, the material of the optoelectronic material layer includes germanium, and the material of the first dielectric layer includes silicon oxide or silicon nitride.
[0027] In this embodiment of the application, the semiconductor structure further includes an isolation structure located in the semiconductor substrate between the logic region and the photoelectric region.
[0028] The semiconductor structure and its formation method described in this application can fabricate optoelectronic devices and logic devices on the same chip, significantly reducing manufacturing costs and improving device integration. Attached Figure Description
[0029] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0030] Figures 1 to 5 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of this application;
[0031] Figures 6 to 11 This is a schematic diagram of the steps in another method for forming a semiconductor structure in an embodiment of this application. Detailed Implementation
[0032] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0033] This application provides a method for forming a semiconductor structure, enabling the formation of logic devices and optoelectronic devices on the same chip, thus integrating infrared photodiode technology with logic technology. The method for forming the semiconductor structure in this application includes:
[0034] A semiconductor substrate is provided, the semiconductor substrate including adjacent logic regions and photoelectric regions, wherein logic devices are formed in the logic regions, and a first dielectric layer is formed on the semiconductor substrate of the logic regions and the photoelectric regions;
[0035] A photoelectric material layer is formed in the first dielectric layer of the photoelectric region, and the surface of the photoelectric material layer is coplanar with that of the first dielectric layer;
[0036] Optoelectronic devices are formed in the optoelectronic material layer or in a semiconductor substrate below the optoelectronic material layer.
[0037] The following describes in detail, with reference to embodiments and accompanying drawings, the method for forming the semiconductor structure of the present application when the optoelectronic device is located in the semiconductor substrate below the optoelectronic material layer.
[0038] refer to Figure 1 A semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SiI), or germanium-on-insulator, etc. It may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide. In this embodiment, the semiconductor substrate 100 is made of silicon.
[0039] The semiconductor substrate 100 includes adjacent logic regions 110 and photoelectric regions 120, wherein the logic regions 110 are used to form logic devices and the photoelectric regions 120 are used to form photoelectric devices. The semiconductor substrate 100 also includes an isolation structure 200 for isolating the logic regions 110 and the photoelectric regions 120. The isolation structure 200 may be a shallow trench isolation structure.
[0040] The logic device includes a source 320 and a drain 310 located in the semiconductor substrate 100 of the logic region 110, and a gate structure 310 located on the surface of the semiconductor substrate 100 between the source 320 and the drain 310. The process for forming the logic device includes: forming a gate material layer on the surface of the semiconductor substrate 100 of the logic region 110 and the photoelectric region 120; etching the gate material layer to form the gate structure 310 on the surface of the semiconductor substrate 100 of the logic region 110, wherein the gate structure 310 may be a single-layer structure or a stacked structure; and forming a source 320 and a drain 330 in the semiconductor substrate 100 on both sides of the gate structure 310.
[0041] While forming the source 320 and drain 330, a first doped region 410 of the optoelectronic device is formed in the semiconductor substrate 100 of the photoelectric region 120. The source 320, drain 330, and first doped region 410 are formed simultaneously using a first ion implantation process; that is, the source 320, drain 330, and first doped region 410 are at the same depth and have the same doping ion type, for example, the doping ion type of the source 320, drain 330, and first doped region 410 is N-type. The specific parameters of the first ion implantation process can be designed according to actual conditions. To improve the integration density of the semiconductor structure, the first doped region 410 is adjacent to the isolation structure 200.
[0042] refer to Figure 2 A second doped region 420 of the optoelectronic device is formed in the semiconductor substrate 100 of the photoelectric region 120. The second doped region 420 is at the same depth as the first doped region 410 but has a different type of doped ion. For example, the doped ion type of the first doped region 410 is N-type, and the doped ion type of the second doped region 420 is P-type. The first doped region 410 and the second doped region 420 form a PN junction of the optoelectronic device. The process for forming the second doped region 420 can be a second ion implantation process, and the specific parameters of the first ion implantation process can be designed according to actual conditions.
[0043] refer to Figure 3 A first dielectric layer 500 is formed on the semiconductor substrate 100 of the logic region 110 and the photoelectric region 120. The process for forming the first dielectric layer 500 can be chemical vapor deposition, atomic layer deposition, etc., and the material of the first dielectric layer 500 can include silicon oxide or silicon nitride, etc. The first dielectric layer 500 is etched to form an opening 431 in the photoelectric region 120 for defining the optoelectronic device; that is, the opening 431 exposes the first doped region 410 and the second doped region 420. Since subsequent processes will create contact holes for the first doped region 410 in the first dielectric layer 500, the opening 431 only exposes a portion of the first doped region 410.
[0044] refer to Figure 4 A photoelectric material layer 430 is formed in the first dielectric layer 500. Specifically, the photoelectric material layer 430 is grown on the surface of the first dielectric layer 500 and in the opening 431 using an epitaxial growth process. The material of the photoelectric material layer 430 may include germanium. The photoelectric material layer 430 is planarized so that it is coplanar with the surface of the first dielectric layer 500. The planarization process may employ a chemical mechanical polishing process. The photoelectric material layer 430 and the semiconductor substrate 100 together serve as the substrate of the optoelectronic device.
[0045] refer to Figure 5 The contact holes 600 of the logic device and the optoelectronic device are formed. The process of forming the contact holes 600 includes: etching a portion of the first dielectric layer 500 on the surface of the source electrode 320 and the drain electrode 330 to form the contact holes 600 of the logic device; etching a portion of the first dielectric layer 500 on the surface of the first doped region 410 and the second doped region 420 to form the contact holes 600 of the optoelectronic device. The order in which the contact holes 600 are formed is not particularly limited; the contact holes 600 of the logic device can be formed first, followed by the contact holes 600 of the optoelectronic device; or the contact holes 600 of the logic device and the optoelectronic device can be formed simultaneously. This embodiment forms the contact holes 600 of the logic device and the optoelectronic device in the same process, reducing time costs.
[0046] The process of forming the contact hole 600 may further include: etching a portion of the first dielectric layer 500 on the surface of the gate structure 310 to form the contact hole 600 connecting the gate structure 310. It should be noted that, due to limitations in the selected cross-sectional area, it is not possible to... Figure 5 The cross-sectional view shown illustrates the contact hole connecting the gate structure 310 and the second doped region 420, but this does not mean that it does not exist.
[0047] Continue to refer to Figure 5 This application also provides a semiconductor structure, including: a semiconductor substrate 100, including adjacent logic regions 110 and photoelectric regions 120; a first dielectric layer 500 located on the semiconductor substrate 100 of the logic regions 110 and the photoelectric regions 120; a photoelectric material layer 430 located in the first dielectric layer 500 of the photoelectric regions 120, and the surface of the photoelectric material layer 430 is coplanar with the surface of the first dielectric layer 500; a logic device located in the logic region 110; and a photoelectric device located in the semiconductor substrate 100 below the photoelectric material layer 430. The material of the photoelectric material layer 430 may include germanium, and the material of the first dielectric layer may include silicon oxide or silicon nitride.
[0048] The logic device includes a source 320 and a drain 330 located in the semiconductor substrate 100 of the logic region 110. The optoelectronic device includes a first doped region 410. The source 320, drain 330, and the first doped region 410 have the same type of doped ions and are located at the same depth. The logic device also includes a gate structure 310 located on the surface of the semiconductor substrate 100 between the source 320 and drain 330.
[0049] The optoelectronic device further includes a second doped region 420, wherein the doped ion types of the first doped region 410 and the second doped region 420 are different.
[0050] In this embodiment of the application, the semiconductor structure further includes contact holes 600 for the logic device and the optoelectronic device, located in the first dielectric layer 500, wherein the contact holes 600 for the logic device are connected to the source 320 and the drain 330, and the contact holes 600 for the optoelectronic device are connected to the first doped region 410 and the second doped region 420.
[0051] The semiconductor structure may further include an isolation structure 200 located in the semiconductor substrate 100 between the logic region 110 and the optoelectronic region 120, which serves to isolate the logic device and the optoelectronic device.
[0052] The following describes in detail, with reference to another embodiment and accompanying drawings, a method for forming the semiconductor structure of the present application when the optoelectronic device is located in the optoelectronic material layer.
[0053] refer to Figure 6 A semiconductor substrate 100 is provided. The semiconductor substrate 100 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, silicon-on-insulator (SiI), or germanium-on-insulator, etc. It may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide. In this embodiment, the semiconductor substrate 100 is made of silicon.
[0054] The semiconductor substrate 100 includes adjacent logic regions 110 and photoelectric regions 120, wherein the logic regions 110 are used to form logic devices and the photoelectric regions 120 are used to form photoelectric devices. The semiconductor substrate 100 also includes an isolation structure 200 for isolating the logic regions 110 and the photoelectric regions 120. The isolation structure 200 may be a shallow trench isolation structure.
[0055] The logic device includes a source 320 and a drain 310 located in the semiconductor substrate 100 of the logic region 110, and a gate structure 310 located on the surface of the semiconductor substrate 100 between the source 320 and the drain 310. The process for forming the logic device includes: forming a gate material layer on the surface of the semiconductor substrate 100 of the logic region 110 and the photoelectric region 120; etching the gate material layer to form the gate structure 310 on the surface of the semiconductor substrate 100 of the logic region 110, wherein the gate structure 310 may be a single-layer structure or a stacked structure; and forming a source 320 and a drain 330 in the semiconductor substrate 100 on both sides of the gate structure 310.
[0056] refer to Figure 7 A first dielectric layer 500 is formed on the semiconductor substrate 100 of the logic region 110 and the photoelectric region 120. The process for forming the first dielectric layer 500 can be chemical vapor deposition, atomic layer deposition, etc., and the material of the first dielectric layer 500 can include silicon oxide or silicon nitride, etc. The first dielectric layer 500 is etched to form an opening 431 for defining the optoelectronic device in the photoelectric region 120.
[0057] refer to Figure 8 A photoelectric material layer 430 is formed in the first dielectric layer 500. Specifically, the photoelectric material layer 430 is grown on the surface of the first dielectric layer 500 and in the opening 431 using an epitaxial growth process. The material of the photoelectric material layer 430 may include germanium. The photoelectric material layer 430 is planarized so that the photoelectric material layer 430 is coplanar with the surface of the first dielectric layer 500. The planarization process may be a chemical mechanical polishing process.
[0058] refer to Figure 9 A photoelectric device is formed in the photoelectric material layer 430. The process for forming the photoelectric device may include: forming a first doped region 410 of the photoelectric device in the photoelectric material layer 430 using a first ion implantation process; and forming a second doped region 420 in the photoelectric material layer 430 at the same depth as the first doped region 410 using a second ion implantation process. The first doped region 410 and the second doped region 420 have different dopant ion types; for example, the first doped region 410 has N-type dopant ions, and the second doped region 420 has P-type dopant ions. The formation order of the first doped region 410 and the second doped region 420 is not required and can be interchanged. The first doped region 410 and the second doped region 420 together form the PN junction of the photoelectric device.
[0059] The method for forming the semiconductor structure may further include: forming contact holes for the logic device and the optoelectronic device.
[0060] refer to Figure 10 The specific process for forming the contact hole may include: forming a second dielectric layer 700 on the first dielectric layer 500 and the optoelectronic material layer 430, wherein the second dielectric layer 700 provides a site for forming the contact hole 600 of the optoelectronic device. The process for forming the second dielectric layer 700 may be chemical vapor deposition, atomic layer deposition, etc., and the material of the second dielectric layer 700 may include silicon oxide or silicon nitride, etc. The material of the second dielectric layer 700 and the first dielectric layer 500 may be the same or different. In the embodiments of this application, the material of the second dielectric layer 700 and the first dielectric layer 500 is the same, both including silicon oxide.
[0061] refer to Figure 11 The process involves etching portions of the second dielectric layer 700 on the first doped region 410 and the second doped region 420 to form the contact hole 600 of the optoelectronic device; and etching portions of the first dielectric layer 500 and the second dielectric layer 700 on the source electrode 320 and the drain electrode 330 to form the contact hole 600 of the logic device. Since the contact holes 600 of the optoelectronic device and the logic device have different depths, they need to be formed in steps. In some embodiments, the contact holes 600 of the logic device can be formed first, followed by the contact holes 600 of the optoelectronic device. However, in this embodiment, the process sequence of forming the contact holes 600 of the optoelectronic device first, followed by the contact holes 600 of the logic device, is adopted. This is because, after forming a photoresist pattern with contact holes for logic devices on the surface of the second dielectric layer 700, and using the photoresist as a mask to form contact holes 600 for logic devices, the photoresist is removed. Then, a photoresist pattern with contact holes for optoelectronic devices is formed on the surface of the second dielectric layer 700. At this time, because there is no shielding on the surface of the formed contact holes for logic devices, the photoresist will also enter the contact holes for logic devices. After forming the contact holes 600 for optoelectronic devices, the photoresist needs to be removed. However, because the contact holes 600 for logic devices are relatively deep, the photoresist in the contact holes 600 for logic devices is not easy to remove, which can easily cause photoresist residue and affect the quality of the contact holes.
[0062] The process of forming the contact hole 600 may further include: etching a portion of the first dielectric layer 500 and the second dielectric layer 700 on the surface of the gate structure 310 to form the contact hole 600 connecting the gate structure 310. It should be noted that, due to limitations in the selected cross-sectional area, it is not possible to... Figure 5 The cross-sectional view shown illustrates the contact hole connecting the gate structure 310, but this does not mean that it does not exist.
[0063] Continue to refer to Figure 11 This application also provides a semiconductor structure, including a semiconductor substrate 100, comprising adjacent logic regions 110 and photoelectric regions 120; a first dielectric layer 500 located on the semiconductor substrate 100 of the logic regions 110 and the photoelectric regions 120; a photoelectric material layer 430 located in the first dielectric layer 500 of the photoelectric regions 120, and the surface of the photoelectric material layer 430 is coplanar with that of the first dielectric layer 500; a logic device located in the logic region 110; and a photoelectric device located in the photoelectric material layer 430. The material of the photoelectric material layer 430 may include germanium, and the material of the first dielectric layer 500 may include silicon oxide or silicon nitride.
[0064] The optoelectronic device includes a first doped region 410 and a second doped region 420, which are located at the same depth but have different doped ion types.
[0065] The logic device includes a source 320 and a drain 330 located in the semiconductor substrate 100 of the logic region 110, wherein the source 320 and drain 330 are of the same doped ion type as the first doped region 410. The logic device may further include a gate structure 310 located on the surface of the semiconductor substrate 100 between the source 320 and drain 330.
[0066] In some embodiments, the semiconductor structure further includes: a second dielectric layer 700 located on the first dielectric layer 500 and the optoelectronic material layer 430; and contact holes 600 for logic devices and optoelectronic devices, wherein the contact holes 600 for logic devices are located in the first dielectric layer 500 and the second dielectric layer 700 and connect the source 320 and the drain 330, and the contact holes 600 for optoelectronic devices are located in the second dielectric layer 700 and connect the first doped region 410 and the second doped region 420. The material of the second dielectric layer 700 may include silicon oxide or silicon nitride.
[0067] The semiconductor structure may further include an isolation structure 200 located in the semiconductor substrate 100 between the logic region 110 and the optoelectronic region 120, which serves to isolate the logic device and the optoelectronic device.
[0068] The semiconductor structure and its formation method provided in this application embodiment effectively integrate the formation process of optoelectronic devices and the formation process of logic devices, overcoming the drawback of the prior art that it is impossible to simultaneously fabricate optoelectronic devices and logic devices on the same chip, greatly reducing the manufacturing cost and improving the integration of devices.
[0069] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0070] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0071] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0072] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0073] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including adjacent logic regions and photoelectric regions, wherein logic devices are formed in the logic regions, and a first dielectric layer is formed on the semiconductor substrate of the logic regions and the photoelectric regions; A photoelectric material layer is formed in the first dielectric layer of the photoelectric region, and the surface of the photoelectric material layer is coplanar with that of the first dielectric layer; An optoelectronic device is formed in the optoelectronic material layer or in a semiconductor substrate below the optoelectronic material layer, wherein the logic device includes a source and a drain located in the semiconductor substrate of the logic region; While forming the source and drain electrodes using a first ion implantation process, a first doped region of the optoelectronic device is formed in the semiconductor substrate of the optoelectronic region.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: A second doped region at the same depth as the first doped region is formed in the semiconductor substrate of the photoelectric region using a second ion implantation process, wherein the doping ion types of the first doped region and the second doped region are different.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, Also includes: A portion of the first dielectric layer on the surface of the source and drain electrodes, the first doped region, and the second doped region is etched to form contact holes for the logic device and the optoelectronic device, respectively.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The process for forming optoelectronic devices in the optoelectronic material layer includes: The first doped region of the optoelectronic device is formed in the optoelectronic material layer using a first ion implantation process. A second doped region at the same depth as the first doped region is formed in the optoelectronic material layer using a second ion implantation process, wherein the doping ion types of the first doped region and the second doped region are different.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The logic device includes a source and a drain located in a semiconductor substrate of the logic region; The method for forming the semiconductor structure further includes: A second dielectric layer is formed on the first dielectric layer and the optoelectronic material layer; Etching a portion of the second dielectric layer on the first doped region and the second doped region forms the contact hole of the optoelectronic device; A portion of the first and second dielectric layers on the source and drain electrodes are etched to form contact holes for the logic device.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the second dielectric layer includes silicon oxide or silicon nitride.
7. The method for forming a semiconductor structure according to claim 1 or 5, characterized in that, The logic device also includes a gate structure located on the surface of a semiconductor substrate between the source and the drain.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, The process for forming the optoelectronic material layer includes: The first dielectric layer is etched to form an opening in the photoelectric region for defining the photoelectric device; An epitaxial growth process is used to grow a photoelectric material layer on the surface of the first dielectric layer and in the opening; The photoelectric material layer is planarized so that the surface of the photoelectric material layer is coplanar with the surface of the first dielectric layer.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the optoelectronic material layer includes germanium, and the material of the first dielectric layer includes silicon oxide or silicon nitride.
10. The method for forming a semiconductor structure according to claim 1, characterized in that, An isolation structure is also formed in the semiconductor substrate between the logic region and the photoelectric region.
11. A semiconductor structure, characterized in that, include: Semiconductor substrate, including adjacent logic regions and optoelectronic regions; A first dielectric layer is located on the semiconductor substrate of the logic region and the photoelectric region; A photoelectric material layer is located in the first dielectric layer of the photoelectric region, and the surface of the photoelectric material layer is coplanar with that of the first dielectric layer; Logic devices are located in the logic area; An optoelectronic device is located in or below a semiconductor substrate of a photoelectric material layer. The logic device includes a source and a drain in the semiconductor substrate of the logic region. The optoelectronic device is located in the semiconductor substrate below the photoelectric material layer and includes a first doped region. The source and drain and the first doped region have the same type of doped ions and are located at the same depth.
12. The semiconductor structure according to claim 11, characterized in that, The optoelectronic device further includes a second doped region, wherein the doped ions in the first doped region and the second doped region are of different types.
13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure further includes contact holes for the logic device and the optoelectronic device, located in the first dielectric layer, wherein the contact holes for the logic device are connected to the source and the drain, and the contact holes for the optoelectronic device are connected to the first doped region and the second doped region.
14. The semiconductor structure according to claim 11, characterized in that, The optoelectronic device is located in the optoelectronic material layer and includes a first doped region and a second doped region. The first doped region and the second doped region are located at the same depth and have different types of doped ions.
15. The semiconductor structure according to claim 14, characterized in that, The logic device includes a source and a drain in a semiconductor substrate located in the logic region, and the source and drain are of the same type of dopant ions as the first doped region.
16. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure also includes: The second dielectric layer is located on the first dielectric layer and the optoelectronic material layer; Contact holes for logic devices and optoelectronic devices, wherein the contact holes for logic devices are located in the first dielectric layer and the second dielectric layer and connect the source and the drain, and the contact holes for optoelectronic devices are located in the second dielectric layer and connect the first doped region and the second doped region.
17. The semiconductor structure according to claim 16, characterized in that, The material of the second dielectric layer includes silicon oxide or silicon nitride.
18. The semiconductor structure according to claim 11 or 15, characterized in that, The logic device further includes a gate structure located on the surface of a semiconductor substrate between the source and the drain.
19. The semiconductor structure according to claim 11, characterized in that, The material of the optoelectronic material layer includes germanium, and the material of the first dielectric layer includes silicon oxide or silicon nitride.
20. The semiconductor structure according to claim 11, characterized in that, Also includes: An isolation structure is located in a semiconductor substrate between the logic region and the photoelectric region.
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