An oxygen passivated gate self-aligned p-gan hemt device and method of fabrication thereof

Abstract

The present application relates to oxygen passivation gate self-alignment p-GaN HEMT device and its preparation method, belong to semiconductor device technical field. Through oxygen plasma passivation and high temperature oxidation method, through the process of gate self-alignment, the enhancement mode hole injection transistor is realized. The high temperature thermal oxidation method is used instead of ICP etching method, the damage caused by ion bombardment is avoided, the surface damage of the device is reduced, and the device after oxygen passivation has high temperature resistance. The high temperature thermal oxidation method is based on oxygen oxidation, so that the Al element in the AlGaN layer reacts with oxygen to automatically prevent further oxidation, avoiding the damage of ICP etching method to AlGaN layer and affecting the performance of the device. The gate metal is used instead of the role of mask to oxidize, the self-alignment process is realized, the hole injection transistor is realized through the ohmic contact gate metal, the holes can combine with the electrons, the electron defects are inhibited, the stability of the threshold voltage of the device is improved, the process steps are reduced, and the process simplicity is improved.

Description

TECHNICAL FIELD

[0001] The application relates to an oxygen passivation gate self-alignment p-GaN HEMT device and a preparation method thereof, and belongs to the technical field of semiconductor devices. BACKGROUND

[0002] Gallium nitride (GaN) material is widely used in power semiconductor devices due to its wide band gap, high thermal conductivity and other characteristics. The high electron mobility transistor (HEMT) made of gallium nitride material can work in harsh environments such as high frequency, high temperature and high voltage, so it has a large application space in chip manufacturing and other industries. The working principle of GaN HEMT is to conduct electricity by means of the high-concentration two-dimensional electron gas (2DEG) between the AlGaN epitaxial layer and the GaN layer, so it has the advantages of high mobility and small on-state resistance.

[0003] The conductive channel of GaN HEMT is naturally formed by piezoelectric effect and polarization effect, so under normal conditions, the device works in the on state, so it is called D-mode device. In order to meet the needs of safe operation and simplify the drive, it is necessary to process the D-mode device to become an E-mode device that can only be turned on under the action of gate voltage (VG). There are currently three main ways to achieve E-mode GaN HEMT: gate recess type (Gate Recess), p-GaN layer depletion type (p-GaN) and fluorine ion implantation type. The p-GaN HEMT has less damage to the conductive channel during production, so the device has smaller on-state resistance and higher electron mobility. Therefore, p-GaN HMET has greater development prospects compared with other methods.

[0004] The p-GaN type GaN HEMT is made of a p-GaN epitaxial wafer. The p-GaN epitaxial wafer is a layer of p-GaN grown on a traditional AlGaN / GaN epitaxial wafer. In the preparation, the p-GaN layer except the p-GaN layer under the gate is removed, thereby retaining the inherent 2DEG conductive channel. The p-GaN retained by the gate interacts with the AlGaN layer, which depletes the underlying 2DEG, and under the action of no gate voltage, it is in the off state, thereby realizing the E-mode function.

[0005] In the prior art, the p-GaN layer is passivated by hydrogen to form Mg-H bonds between hydrogen ions and Mg ions in the p-GaN layer, but due to the instability of the Mg-H bonds, the passivation by hydrogen cannot achieve reliability under high-temperature conditions, and the passivation by hydrogen loses the high-temperature resistance. The process of passivation by oxygen usually grows an AlN layer between the p-GaN layer and the AlGaN layer, so as to facilitate the control of the oxidation time, but the AlN layer with a thickness of about 1-5 nm as a semiconductor material cannot improve the breakdown resistance of the device. Another full-etching scheme removes the p-GaN layer between the source, the drain and the gate by etching, and the difficulty lies in accurately controlling the etching depth, reducing the surface roughness after etching, and avoiding etching damage to the crystal lattice, which often requires harsh environment and long-term debugging. SUMMARY

[0006] The purpose of the present application is to provide an oxygen passivation and gate self-alignment p-GaN HEMT device and a preparation method thereof, which realizes a gate self-alignment preparation process and improves the gate control performance of the device.

[0007] To achieve the above purpose, the present application provides the following technical scheme: a preparation method of an oxygen passivation and gate self-alignment p-GaN HEMT device, comprising the following steps:

[0008] S1, growing a GaN barrier layer, an AlGaN layer and a p-GaN layer on the surface of a base layer in sequence;

[0009] S2, after defining the active region position on the p-GaN layer, growing Ni / Au or Ni / Ag as a gate metal on the surface of the p-GaN layer by PVD to define the gate position;

[0010] S3, growing a SiOx mask layer on the surface of the gate by LPCVD;

[0011] S4, passivating the p-GaN layer into a high-resistance layer in the area not protected by the SiOx mask layer by an ICP O2 plasma passivation device;

[0012] S5, removing the SiOx mask layer, oxidizing the device in a high-temperature oxidation furnace, and oxidizing the gate metal to form an ohmic contact with the p-GaN layer below the gate;

[0013] S6, defining the source and drain regions by photolithography, and selectively etching the p-GaN layer in the secondary oxidation area;

[0014] S7, PVD deposition and annealing to form an ohmic contact of the source and the drain, PRCVD deposition of a SiNx passivation layer, and completion of the device manufacturing.

[0015] Further, the GaN barrier layer has a thickness of 2-5 μm.

[0016] Further, the AlGaN layer has a thickness of 15-25 nm.

[0017] Further, the active region position is defined by ICP etching or ion implantation method in the step S2.

[0018] Further, the high resistance layer after secondary oxidation is etched by KOH solution or KCl solution in the step S6.

[0019] Further, Ti / Al / Ni / TiN four-layer metal is grown by PVD and annealed in inert gas environment to realize ohmic contact of the source and drain in the step S7.

[0020] The application also provides an oxygen passivation gate self-aligned p-GaN HEMT device prepared by the preparation method of the oxygen passivation gate self-aligned p-GaN HEMT device.

[0021] The application provides a preparation method of an oxygen passivation gate self-aligned p-GaN HEMT device, which uses a high-temperature thermal oxidation method to replace a traditional ICP etching method in the step S5, so that damage caused by ion bombardment can be avoided, the damage of the device surface is reduced, and the device after oxygen passivation has high-temperature resistance. The high-temperature thermal oxidation method is based on oxygen to oxidize, so that the Al element in the AlGaN layer reacts with oxygen to automatically prevent further oxidation, avoids damage to the AlGaN layer caused by the ICP etching method, and further affects the performance of the device. The application uses gate metal to replace the role of a mask to oxidize, realizes self-aligned process treatment, realizes a hole injection type transistor through ohmic contact of the gate metal, the holes can be combined with electrons to inhibit electron defects, improve the stability of the threshold voltage of the device, reduces the process steps, and improves the simplicity of the process.

[0022] The above description is only a summary of the technical scheme of the application, in order to more clearly understand the technical means of the application, and the application can be implemented according to the content of the description, as follows. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The figure is a preparation process flowchart of the device of the application. DETAILED DESCRIPTION

[0024] The specific embodiments of the present application will be further described with reference to the drawings and examples. The following examples are intended to illustrate the present application and are not intended to limit the scope of the present application.

[0025] The present application will be further described with reference to the drawings and examples. The following examples are intended to illustrate the present application and are not intended to limit the scope of the present application.

[0026] As used herein, the terms "comprise", "comprising", "include", "including", "have", "having" or the like are open-ended, that is, they mean "including but not limited to".

[0027] As used herein, the terms "comprise", "comprising", "include", "including", "have", "having" or the like are open-ended, that is, they mean "including but not limited to".

[0028] See Figure 1 The present application provides a preparation method of an oxygen passivated gate self-aligned p-GaN HEMT device, comprising the following steps:

[0029] Example 1

[0030] Step 1, growing GaN barrier layer and AlGaN layer and p-GaN layer on the surface of the base layer in sequence.

[0031] The base layer is a silicon substrate, and the GaN barrier layer, the AlGaN layer and the p-GaN layer are grown on the silicon substrate at one time. The thickness of the GaN barrier layer is 2-5 μm, and the thickness of the AlGaN layer is 15-25 nm.

[0032] Step 2, after defining the active region position on the p-GaN layer, growing Ni / Au as the gate metal on the surface of the p-GaN layer by PVD to define the gate position.

[0033] The active region position is defined by ICP etching or ion implantation method. The source and drain regions are protected by photoresist by lithography, and the gate region is exposed, and then two layers of metal are grown in sequence by electron beam evaporation, the lower layer is Ni, and the upper layer is Au or Ag, as the gate electrode.

[0034] Step 3, growing a SiOx mask layer on the surface of the gate by LPCVD.

[0035] Step 4, passivating the p-GaN layer region not protected by the SiOx mask layer into a high resistance layer by ICP O2 plasma passivation device.

[0036] See the cross-sectional structure of Figure 1 (a), wherein 1 is a substrate, 2 is a GaN barrier layer, 3 is an AlGaN layer, 4 is a p-GaN layer, 5 is a p-GaN layer oxidized by an oxygen plasma, 6 is a gate metal alloy, and 7 is a SiOx mask layer.

[0037] Step 5, remove the SiOx mask layer, and oxidize the device in a high-temperature oxidation furnace, so that the gate metal is oxidized to form an ohmic contact with the p-GaN layer below the gate.

[0038] See the cross-sectional structure of Figure 1 (b), wherein 1 is a substrate, 2 is a GaN barrier layer, 3 is an AlGaN layer, 4 is a p-GaN layer, 6 is a gate metal alloy, and 8 is a p-GaN layer after being oxidized by an oxygen plasma and then being subjected to high-temperature thermal oxidation.

[0039] Step 6, define the source and drain regions by photolithography, and selectively etch the p-GaN layer in the second-oxidized region.

[0040] Define the source and drain regions of the device by photolithography, and selectively partially etch the p-GaN layer after being second-oxidized by a potassium hydroxide (KOH) or hydrochloric acid (HCl) solution. See the cross-sectional structure of Figure 1 (c), wherein 1 is a substrate, 2 is a GaN barrier layer, 3 is an AlGaN layer, 4 is a p-GaN layer, 6 is a gate metal alloy, and 8 is a p-GaN layer after being oxidized by an oxygen plasma and then being subjected to high-temperature thermal oxidation.

[0041] Step 7, PVD deposition and annealing to form ohmic contacts of the source and drain, PRCVD deposition of a SiNx passivation layer, and completion of the device.

[0042] In which, Ti / Al / Ni / TiN four-layer metal is grown using PVD, and annealing is performed in an inert gas environment to enable the source and drain to achieve ohmic contact. In detail, Ti / Al / Ni / TiN four-layer metal is grown using an electron beam evaporation or a magnetron sputtering device, and annealing is performed in an N2 or Ar inert gas environment to enable the source and drain to achieve ohmic contact. See the cross-sectional structure of Figure 1 (d), wherein 1 is a substrate, 2 is a GaN barrier layer, 3 is an AlGaN layer, 4 is a p-GaN layer, 6 is a gate metal alloy, 8 is a p-GaN layer after being oxidized by an oxygen plasma and then being subjected to high-temperature thermal oxidation, 9 is a metal electrode deposited on the surface of the p-GaN layer, and 10 is a SiNx passivation layer.

[0043] It should be noted that the most critical step of realizing the normally-off device through the p-GaN layer is to disable the p-GaN layer below the gate, thereby restoring the two-dimensional electron gas conduction channel, maintaining the advantage of high electron mobility of the gallium nitride device, and the existing technology usually uses etching or hydrogen passivation, such as patent CN109727863, which uses ICP-RIE process for etching to remove the excess p-GaN layer. The ICP etching method is to use plasma gas to bombard the part that needs to be etched, and the ICP etching method is easy to cause surface damage to the device, affect the two-dimensional electron gas, and further increase the on-resistance of the device. Therefore, how to accurately control the complete etching of the p-GaN layer and not cause damage to the AlGaN layer below is a key technical difficulty, and the existing technology uses different etching rates for the AlGaN layer and the p-GaN layer to achieve the purpose of protection, and the rate difference is the selection ratio, but the selection ratio of the ICP at the present stage does not reach the ideal state, and in actual application, damage to the AlGaN layer will occur during etching, affecting the performance of the device. In the present application, the high-temperature thermal oxidation method can avoid the damage caused by ion bombardment, and because the high-temperature thermal oxidation method is based on oxygen oxidation, when the AlGaN layer is encountered, the Al element will react with oxygen, automatically preventing further oxidation. And during step 5, i.e., the high-temperature thermal oxidation process, the gate metal is oxidized at the same time, so that the contact mode of the gate metal and the p-GaN layer becomes ohmic contact.

[0044] In summary, the preparation method of the oxygen passivation gate self-alignment p-GaN HEMT device provided by the present application uses a high-temperature thermal oxidation method instead of the traditional ICP etching method in step S5, which can avoid the damage caused by ion bombardment, reduce the damage to the surface of the device, and the device passivated by oxygen has high-temperature resistance. And the high-temperature thermal oxidation method is based on oxygen oxidation, so that the Al element in the AlGaN layer reacts with oxygen to automatically prevent further oxidation, avoiding damage to the AlGaN layer using the ICP etching method and affecting the performance of the device. The present application uses gate metal to replace the role of the mask plate for oxidation, realizes self-alignment process, realizes hole injection type transistor through ohmic contact gate metal, holes can combine with electrons to suppress electron defects, improve the stability of the threshold voltage of the device, and at the same time, reduce the process steps and improve the simplicity of the process.

[0045] The technical features of the above-described embodiments and the detection items can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0046] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for fabricating an oxygen passivated gate self-aligned p-GaN HEMT device, comprising: The method comprises the following steps: S1, growing GaN barrier layer and AlGaN layer and p-GaN layer on the surface of the base layer in sequence; S2, after defining the active region position on the p-GaN layer, growing Ni / Au or Ni / Ag as the gate metal on the surface of the p-GaN layer by PVD to define the gate position; S3, growing SiOx mask layer on the surface of the gate by LPCVD; S4, passivating the p-GaN layer into high resistance layer by ICP O2 plasma passivation device in the area not protected by the SiOx mask layer; S5, removing the SiOx mask layer, and oxidizing the device in a high-temperature oxidation furnace, and the gate metal is oxidized to form ohmic contact with the p-GaN layer under the gate; S6, defining the source and drain regions by photolithography, and selectively etching the p-GaN layer in the secondary oxidation area, and the secondary oxidation area is an oxidation area formed by oxygen plasma oxidation and high-temperature thermal oxidation in sequence; S7, PVD deposition and annealing to form ohmic contact of the source and drain, PRCVD deposition of SiNx passivation layer, and completion of device fabrication.

2. The method of fabricating an oxygen passivated gate self-aligned p-GaN HEMT device as claimed in claim 1, wherein, The thickness of the GaN barrier layer is 2-5 μm.

3. The method of fabricating an oxygen passivated gate self-aligned p-GaN HEMT device as claimed in claim 1, wherein, The thickness of the AlGaN layer is 15-25 nm.

4. The method of claim 1, wherein the method further comprises: The active region position is defined by ICP etching or ion implantation method in the step S2.

5. The method of fabricating an oxygen passivated gate self-aligned p-GaN HEMT device as claimed in claim 1, wherein, The high resistance layer after secondary oxidation is etched by KOH solution or KCl solution in the step S6.

6. The method of fabricating an oxygen passivated gate self-aligned p-GaN HEMT device as claimed in claim 1, wherein, Ti / Al / Ni / TiN four-layer metal is grown by PVD in the step S7, and annealing is performed in an inert gas environment to realize ohmic contact of the source and drain.

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