Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: removing a dummy gate structure to form a gate opening, exposing a stacked structure and an isolation layer; removing a portion of the thickness of the isolation layer at the bottom of the gate opening to expose a portion of the sidewall of the protrusion; removing the protrusion exposed by the isolation layer along a direction perpendicular to the extension of the first channel layer to form a trench between the first channel layer and the remaining protrusion, with the first channel layer and the remaining protrusion or the substrate spaced apart; or thinning the sidewalls of the exposed protrusion along a direction perpendicular to the extension of the first channel layer to form a trench surrounded by the first channel layer and the remaining protrusion; removing a sacrificial layer in the channel stack to form a through-groove; and filling the gate opening, the through-groove, and the trench with a gate structure, wherein the gate structure surrounds the second channel layer and also surrounds the first channel layer or the first channel layer exposed by the protrusion. Embodiments of the present invention reduce leakage current of the device and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration. Semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the reduction of process nodes.

[0003] To better adapt to the scaling requirements of device sizes, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area on all sides. Compared with planar transistors, the gate of a GAA transistor has stronger control over the channel and can better suppress short channel effects.

[0004] However, the performance of gate-all-around transistors still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to reduce the leakage current of the device and improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a lateral extension region extending in a lateral direction, wherein the lateral extension region comprises a first region and second regions located on both sides of the first region in a lateral direction; the substrate comprising: a substrate; a raised portion, wherein the raised portion protrudes from the substrate in the second region, or the raised portion protrudes from the substrate in the lateral extension region, and the top surface of the raised portion in the first region is lower than the top surface of the raised portion in the second region; a channel structure layer, located above the substrate in the first region, wherein the bottom surface of the channel structure layer is higher than or flush with the top surface of the raised portion in the second region, and the channel structure layer comprises first trenches arranged sequentially from bottom to top. The invention relates to a channel structure layer and one or more second channel layers; an isolation layer located on the substrate and surrounding the protrusion; a gate structure located on the isolation layer and across the channel structure layer, the gate structure filling between the first channel layer and the substrate, and between the first channel layer and the second channel layer, or the gate structure filling between the first channel layer and the substrate, between the first channel layer and the second channel layer, and between adjacent second channel layers; the gate structure surrounds the first channel layer and the second channel layer; a source-drain doped layer located on the protrusion of the second region on both sides of the gate structure, and the source-drain doped layer is in contact with the end of the channel structure layer along the extension direction.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, comprising a lateral extension region extending in a lateral direction, wherein a direction parallel to the substrate and perpendicular to the lateral direction is a longitudinal direction; the lateral extension region comprises a first region and a second region located on both sides of the first region in the lateral direction; the substrate comprises: a substrate; a protrusion protruding from the substrate in the lateral extension region, the protrusion located in the first region comprises a support portion, and along the longitudinal direction, the sidewall of the support portion is retracted relative to the sidewall on the same side of the protrusion in the second region; a channel structure layer, located on the support portion, the channel structure layer comprising a first channel layer and one or more second channel layers arranged in sequence from bottom to top, and a portion of the bottom surface of the first channel layer is in contact with the support portion; an isolation layer, located on the substrate and surrounding the protrusion; a gate structure, located on the isolation layer and spanning the channel structure layer and surrounding the second channel layer, and the gate structure also surrounds the first channel layer exposed by the support portion; a source / drain doping layer, located on the protrusion of the second region on both sides of the gate structure, and the source / drain doping layer is in contact with the end of the channel structure layer along the extension direction.

[0008] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a base, comprising a substrate and a raised portion protruding from the substrate, a stacked structure formed on the raised portion, the stacked structure comprising a first channel layer and one or more channel stacks stacked in sequence from bottom to top on the first channel layer, each of the channel stacks comprising a sacrificial layer and a second channel layer on the sacrificial layer; an isolation layer surrounding the raised portion is formed on the substrate, the isolation layer exposing the stacked structure; a pseudo-gate structure spanning the stacked structure is formed on the isolation layer; source-drain doping layers are formed in the stacked structure on both sides of the pseudo-gate structure; the pseudo-gate structure is removed to form a gate opening to expose the stacked structure and the isolation layer; a portion of the thickness of the isolation layer at the bottom of the gate opening is removed to expose the raised portion. ; removing the protrusion exposed by the isolation layer along an extension direction perpendicular to the first channel layer to form a groove between the first channel layer and the remaining protrusion, and the first channel layer is spaced apart from the remaining protrusion or the substrate; or thinning the sidewall of the exposed protrusion along an extension direction perpendicular to the first channel layer so that the first channel layer and the remaining protrusion form a groove; removing the sacrificial layer in the channel stack to form a through groove, which is surrounded by the second channel layer and the first channel layer, or by the adjacent second channel layer; filling the gate opening and the through groove, as well as the trench, with a gate structure, which surrounds the second channel layer, and the gate structure also surrounds the first channel layer or the first channel layer exposed by the protrusion.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the semiconductor structure provided by an embodiment of the present invention, the raised portion protrudes from the substrate of the second region; or, the raised portion protrudes from the substrate of the lateral extension region, and the top surface of the raised portion in the first region is lower than the top surface of the raised portion in the second region; and the bottom surface of the channel structure layer is higher than or flush with the top surface of the raised portion in the second region. Therefore, the embodiment of the present invention allows the raised portion to protrude only from the substrate of the second region or adjusts the top surface height of the raised portion in the first region, so that there is a gap between the first channel layer and the base, thereby providing a filling space for the gate structure at the bottom of the first channel layer, so that the gate structure can also be filled between the first channel layer and the base. Accordingly, the gate structure can also surround the first channel layer, which is beneficial to increase the surrounding area of ​​the gate structure on the first channel layer, thereby improving the control ability of the gate structure on the first channel layer, reducing the leakage current of the device, and improving the performance of the semiconductor structure.

[0011] In the semiconductor structure provided by an embodiment of the present invention, the raised portion protrudes from the substrate of the lateral extension area, the raised portion located in the first area includes a supporting portion, and along the longitudinal direction, the side wall of the supporting portion is retracted relative to the side wall on the same side of the raised portion in the second area; in the channel structure layer, part of the bottom surface of the first channel layer is in contact with the supporting portion, so that the supporting portion can also expose part of the bottom surface of the first channel layer, and thus the gate structure also surrounds the first channel layer exposed by the supporting portion, which correspondingly increases the surrounding area of ​​the gate structure on the first channel layer, which is beneficial to improving the control ability of the gate structure on the first channel layer, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure.

[0012] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming a gate opening, a portion of the thickness of the isolation layer at the bottom of the gate opening is removed to expose a portion of the sidewall of the raised portion, and the exposed raised portion is removed or the sidewall of the exposed raised portion is thinned along an extension direction perpendicular to the first channel layer to form a trench. The trench can provide space for subsequent filling of the gate structure at the bottom of the first channel layer. Accordingly, in the process of forming the gate structure, the gate structure can also be filled in the trench, so that the gate structure not only surrounds the second channel layer, but also surrounds the first channel layer or surrounds the first channel layer exposed by the raised portion. Compared with the gate structure only covering the top surface of the first channel layer or only covering the top surface and sidewalls of the first channel layer, the embodiment of the present invention increases the surrounding area of ​​the gate structure of the first channel layer, which is beneficial to improving the control ability of the gate structure over the first channel layer, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural diagram of a semiconductor structure;

[0014] Figures 2 to 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figures 5 and 6 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention;

[0016] Figures 7 to 33 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0017] Figures 34 to 36 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0018] As can be seen from the background art, the performance of current all-around gate transistors still needs to be improved. The reasons why the performance of all-around gate transistors needs to be improved are now analyzed in conjunction with a semiconductor structure. Figure 1 It is a schematic diagram of the local three-dimensional structure of a semiconductor structure.

[0019] The semiconductor structure includes: a base, including a substrate 10 and a protrusion 16 protruding from the substrate 10; an isolation layer 17, located on the substrate 10 and surrounding the protrusion 16; a channel structure layer 11, located on the protrusion 16, the channel structure layer 11 including a first channel layer 18, and one or more second channel layers 12 located on the first channel layer 18 and spaced apart from the first channel layer 18, the one or more second channel layers 12 being spaced apart from each other from bottom to top, wherein the first channel layer 18 and the protrusion 16 are an integrated structure; a gate structure 13, located on the isolation layer 18. 7 and spans the channel structure layer 11 and covers the top of the channel structure layer 11, the gate structure 13 surrounds the second channel layer 12, and the gate structure 13 is filled between the first channel layer 18 and the second channel layer 12, or, is filled between the first channel layer 18 and the second channel layer 12, and between adjacent second channel layers 12; the source and drain doped layers 14 are located on the protrusions 16 on both sides of the gate structure 13 and are in contact with the end of the channel structure layer 11 along the extension direction; the dielectric layer 15 is located on the isolation layer 17 and covers the source and drain doped layers 14.

[0020] The semiconductor structure is a fully enclosed gate transistor, wherein the gate structure 13 only surrounds the second channel layer 12. For the first channel layer 18, the gate structure 13 only covers the top surface and sidewalls of the first channel layer 18. The gate structure 13 only surrounds the first channel layer 18 on three sides. Compared with the second channel layer 12, the gate structure 13 has a weaker control ability over the first channel layer 18. The transistor corresponding to the first channel layer 18 is more likely to generate leakage current, and the device performance is poor.

[0021] In order to solve the technical problem, in the semiconductor structure provided by the embodiment of the present invention, the protrusion protrudes from the substrate of the second region; or, the protrusion protrudes from the substrate of the lateral extension region, and the top surface of the protrusion in the first region is lower than the top surface of the protrusion in the second region; and the bottom surface of the channel structure layer is higher than or flush with the top surface of the protrusion in the second region. Therefore, the embodiment of the present invention makes the protrusion protrude only from the substrate of the second region or adjusts the top surface height of the protrusion in the first region, so that there is a gap between the first channel layer and the base, thereby providing a filling space for the gate structure at the bottom of the first channel layer, so that the gate structure can also be filled between the first channel layer and the base. Accordingly, the gate structure can also surround the first channel layer, which is beneficial to increase the surrounding area of ​​the gate structure of the first channel layer, thereby improving the control ability of the gate structure over the first channel layer, reducing the leakage current of the device, and improving the performance of the semiconductor structure.

[0022] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] refer to Figures 2 to 4 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention. Figure 2 For a three-dimensional image, Figure 3 for Figure 2 A local stereogram along the a-a1 secant line. Figure 4 (a) Figure 2 Cross-section along the xx direction, Figure 4 (b) Figure 2 Cross-sectional view along the yy direction.

[0024] like Figures 2 to 4As shown, in this embodiment, the semiconductor structure includes: a base, including a lateral extension area 100L extending in the lateral direction, the lateral extension area 100L including a first region I and a second region II located on both sides of the first region I in the lateral direction; the base includes: a substrate 100; a protrusion 110, the protrusion 110 protruding from the substrate 100 in the second region II; or, the protrusion 110 protruding from the substrate 100 in the lateral extension area 100L, and the top surface of the protrusion 110 in the first region I is lower than the top surface of the protrusion 110 in the second region II; a channel structure layer 300, located above the base in the first region I, and the bottom surface of the channel structure layer 300 is higher than or flush with the top surface of the protrusion 110 in the second region II, and the channel structure layer 300 includes a first channel layer 40 and a one or more second channel layers 30; an isolation layer 105, located on the substrate 100 and surrounding the protrusion 110; a gate structure 230, located on the isolation layer 105 and across the channel structure layer 300, the gate structure 230 filling between the first channel layer 40 and the substrate, and between the first channel layer 40 and the second channel layer 30, or, the gate structure 230 filling between the first channel layer 40 and the substrate, between the first channel layer 40 and the second channel layer 30, and between adjacent second channel layers 30; the gate structure 230 surrounds the first channel layer 40 and the second channel layer 30; a source-drain doped layer 155, located on the protrusion 110 of the second region II on both sides of the gate structure 230, and the source-drain doped layer 155 is in contact with the end of the channel structure layer 300 along the extension direction.

[0025] The substrate is used to provide a process platform for forming a semiconductor structure. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for description. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0026] In this embodiment, the substrate includes a plurality of transverse extension areas 100L, and the plurality of transverse extension areas 100L are arranged in parallel and spaced apart along a longitudinal direction, where the longitudinal direction is perpendicular to the transverse direction.

[0027] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0028] The protrusion 110 protrudes from the substrate 100 of the second region II; or, the protrusion 110 protrudes from the substrate 100 of the lateral extension area 100L, and the top surface of the protrusion 110 in the first region I is lower than the top surface of the protrusion 110 in the second region II; and the bottom surface of the channel structure layer 300 is higher than or flush with the top surface of the protrusion 110 in the second region II. Therefore, in this embodiment, the protrusion 110 is only protruded from the substrate 100 in the second region II or the top surface height of the protrusion 110 in the first region I is adjusted. The structure of the first channel layer 40 is configured such that there is a gap between the first channel layer 40 and the substrate, thereby providing a filling space for the gate structure 230 at the bottom of the first channel layer 40, so that the gate structure 230 can also be filled between the first channel layer 40 and the substrate. Accordingly, the gate structure 230 can also surround the first channel layer 40, which is beneficial to increase the surrounding area of ​​the gate structure 230 to the first channel layer 40, thereby improving the control ability of the gate structure 230 to the first channel layer 40, reducing the leakage current of the device, and improving the performance of the semiconductor structure.

[0029] As an example, the raised portion 110 protrudes from the substrate 100 of the lateral extension zone 100L, and the top surface of the raised portion 110 of the first region I is lower than the top surface of the raised portion 110 of the second region II, so that the first channel layer 40 located above the raised portion 110 of the first region I can have a gap between it and the raised portion 110.

[0030] In other embodiments, the protrusion may only protrude from the protrusion of the second region, which is beneficial to increase the distance between the first channel layer and the substrate of the first region, thereby increasing the filling space of the gate structure between the first channel layer and the substrate.

[0031] It should be noted that the raised portion 110 protrudes from the substrate 100 of the second region II; or, the raised portion 110 protrudes from the substrate 100 of the lateral extension region 100L, and the top surface of the raised portion 110 of the first region I is lower than the top surface of the raised portion 110 of the second region II. This is because in the formation process of the semiconductor structure, after forming the gate opening and removing part of the thickness of the isolation layer 105 below the gate opening, the raised portion 110 exposed by removing the isolation layer 105 along the longitudinal direction, accordingly, when the raised portion 110 protrudes from the substrate 100 of the lateral extension region 100L, the raised portion 110 is an integrated structure.

[0032] In this embodiment, the raised portion 110 and the substrate 100 are integrally formed. The material of the raised portion 110 is the same as that of the substrate 100, namely silicon. In other embodiments, the material of the raised portion may be different from that of the substrate. The material of the raised portion may be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0033] The channel structure layer 300 is used to provide a conductive channel of the field effect transistor.

[0034] As an example, the channel structure layer 300 is a fin structure extending along the lateral direction.

[0035] The stacking direction of the first channel layer 40 and the second channel layer 30 (eg Figure 2 The Z direction is perpendicular to the surface of the substrate 100.

[0036] In this embodiment, the first channel layer 40 and the raised portion 110 are made of the same material because during the formation of the semiconductor structure, the first channel layer 40 and the raised portion 110 are in contact and form an integrated structure. After forming the gate opening and removing a portion of the thickness of the isolation layer 105 below the gate opening, the raised portion 110 exposed by removing the isolation layer 105 along the longitudinal etching is removed, so that there is a gap between the first channel layer 40 and the raised portion 110 of the first region I.

[0037] In this embodiment, the material of the first channel layer 40 is Si, which is beneficial for improving the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, SiGe channel technology can be used to improve the performance of the PMOS transistor, and the material of the first channel layer is SiGe. In other embodiments, the material of the first channel layer can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0038] As an example, in the channel structure layer 450 , the number of the second channel layers 30 is three. In other embodiments, the number of the second channel layers may be other numbers.

[0039] The isolation layer 105 is used to isolate adjacent protrusions 110 and to isolate the substrate 100 from the gate structure 230. In this embodiment, the isolation layer 105 is made of silicon oxide. The isolation layer 105 may also be made of other insulating materials.

[0040] In this embodiment, the isolation layer 105 includes a first isolation layer 106 located at the bottom of the gate structure 230 and a second isolation layer 107 exposed from the gate structure 230 . The top surface of the first isolation layer 106 is lower than the top surface of the second isolation layer 107 .

[0041] The top surface of the first isolation layer 106 is lower than the top surface of the second isolation layer 107. This is because in the formation process of the semiconductor structure, after the gate opening is formed, part of the thickness of the isolation layer 105 below the gate opening is also removed to expose part of the side wall of the protrusion 110, so that the protrusion 110 can be etched along the longitudinal direction. The gate opening is used to provide a spatial position for forming the gate structure 230. Accordingly, the top surface of the isolation layer 105 (i.e., the first isolation layer 106) located at the bottom of the gate structure 230 is lower than the top surface of the isolation layer 105 (i.e., the second isolation layer 107) exposed in the gate structure 230.

[0042] Along the direction perpendicular to the surface of the substrate 100, the distance between the first channel layer 40 and the adjacent second channel layer 30 is a first dimension; the height difference between the top surface of the first isolation layer 106 and the top surface of the second isolation layer 107 is a second dimension, and the second dimension is 90% to 110% of the first dimension.

[0043] During the formation of the semiconductor structure, a sacrificial layer is further formed between the first channel layer 40 and the adjacent second channel layer 30, or between the adjacent second channel layers 30; by setting the height difference between the top surface of the first isolation layer 106 and the top surface of the second isolation layer 107 within the above range, so that in the process of removing the partial thickness isolation layer below the gate opening, the removed thickness of the isolation layer 105 is substantially equivalent to the thickness of the sacrificial layer, so that the side wall height of the protrusion 110 exposed by the isolation layer 105 is substantially equivalent to the distance between the first channel layer 40 and the adjacent second channel layer 30. In other words, the side wall height of the protrusion 110 exposed by the isolation layer 105 is smaller than the distance between the first channel layer 40 and the adjacent second channel layer 30, which is beneficial for making the height of the groove formed below the first channel layer 40 after the protrusion 110 exposed by the isolation layer 105 is removed along the longitudinal direction. The difference between the height of the groove and the distance between the first channel layer 40 and the adjacent second channel layer 30 is smaller, which facilitates the filling of the gate structure 230 between the first channel layer 40 and the adjacent second channel layer 30 and in the space below the first channel layer 40, which is correspondingly beneficial for improving process compatibility.

[0044] In this embodiment, the raised portion 110 protrudes from the substrate 100 in the lateral extension region 100L, and the top surface of the raised portion 110 in the first region I is flush with or lower than the top surface of the first isolation layer 106. When the top surface of the raised portion 110 in the first region I is lower than the top surface of the first isolation layer 106, the distance between the first channel layer 106 and the raised portion 110 in the first region I can be increased, thereby increasing the filling space of the gate structure 230 below the first channel layer 106, which facilitates the filling of the gate structure 230 below the first channel layer 230.

[0045] When the device is operating, the gate structure 230 is used to control the opening and closing of the conductive channel.

[0046] In this embodiment, the gate structure 230 is a metal gate structure, which includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove 180 and the gate opening 170.

[0047] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3. As an example, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0048] The work function layer is used to adjust the work function of the gate structure 230, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

[0049] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 230 to an external circuit. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0050] In this embodiment, the gate structure 230 is described as a metal gate structure. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0051] In this embodiment, the gate structure 230 includes a first portion (not labeled) spanning the channel structure layer 300, and a second portion (not labeled) located between the first channel layer 40 and the substrate of the first region I, between the first channel layer 40 and the second channel layer 30, or between adjacent second channel layers 30.

[0052] In this embodiment, along the transverse direction, the sidewall of the first portion is retracted relative to the sidewall of the first channel layer 40 , and the sidewall of the second portion is retracted relative to the sidewall of the first channel layer 40 .

[0053] In this embodiment, the semiconductor structure further includes a gate spacer 130 located on the sidewall of the first portion. The gate spacer 130 is used to define the formation position of the source / drain doped layer 155 and to protect the sidewall of the gate structure 230.

[0054] In this embodiment, the gate spacer 130 is made of silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material, and is a single-layer or stacked-layer structure. As an example, the gate spacer 130 is a single-layer structure, and the material of the gate spacer 130 is silicon nitride.

[0055] In this embodiment, the semiconductor structure further includes an inner sidewall 150 located on the sidewall of the second portion. The inner sidewall 150 is used to isolate the source / drain doped layer 155 from the gate structure 230 and also increases the distance between the gate structure 230 and the source / drain doped layer 155, thereby reducing parasitic capacitance between the gate structure 230 and the source / drain doped layer 155.

[0056] In this embodiment, the inner sidewall 150 is made of an insulating material to isolate the gate structure 230 from the source / drain doped layer 155. In this embodiment, the material of the inner sidewall 150 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. For example, the material of the inner sidewall 150 is silicon nitride.

[0057] The source-drain doped layer 155 is used as a source or drain of the field effect transistor. When the field effect transistor is working, the source-drain doped layer 155 is used to provide a carrier source.

[0058] In this embodiment, the source / drain doped layer 155 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer 155 includes a stress layer doped with N-type ions, and the stress layer material is Si or SiC. When forming a PMOS transistor, the source / drain doped layer 155 includes a stress layer doped with P-type ions, and the stress layer material is Si or SiGe.

[0059] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 160 , which is located on the isolation layer 105 and covers the sidewalls of the gate spacer 130 and the source / drain doping layer 155 .

[0060] The interlayer dielectric layer 160 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide. The material of the interlayer dielectric layer 160 can also be other insulating materials.

[0061] refer to Figures 5 and 6 , shows a schematic structural diagram of another embodiment of the semiconductor structure of the present invention. Figure 5 For a three-dimensional image, Figure 6 (a) Figure 5 Cross-section along the yy direction, Figure 6 (b) Figure 6 (a) Cross-sectional view along the 1-1' direction.

[0062] like Figures 5 and 6As shown, in this embodiment, the semiconductor structure includes: a substrate, including a lateral extension area 400L extending in a lateral direction, wherein the direction parallel to the substrate and perpendicular to the lateral direction is a longitudinal direction; the lateral extension area includes a first region I and a second region II located on both sides of the first region I in the lateral direction; the substrate includes: a substrate 400; a protrusion 410, the substrate 400 protruding from the lateral extension area 400L, the protrusion 410 located in the first region I includes a supporting portion 411, and along the longitudinal direction, the sidewall of the supporting portion 411 is retracted relative to the sidewall of the protrusion 410 on the same side of the second region II; a channel structure layer, located on the supporting portion 411, and the channel structure layer 450 includes The invention comprises a first channel layer 50 and one or more second channel layers 60 arranged in sequence from bottom to top, and a portion of the bottom surface of the first channel layer 50 is in contact with the support portion 412; an isolation layer 405, located on the substrate 400 and surrounding the protrusion; a gate structure 430, located on the isolation layer 405 and spanning the channel structure layer 450 and surrounding the second channel layer 60, and the gate structure 430 also surrounds the first channel layer 50 exposed by the support portion 412; a source-drain doped layer 455, located on the protrusion II of the second region on both sides of the gate structure 430, and the source-drain doped layer 455 is in contact with the end of the channel structure layer 450 along the extension direction.

[0063] In the semiconductor structure provided in this embodiment, the protrusion 410 protrudes from the substrate 400 of the lateral extension area 400L, and the protrusion 410 located in the first region I includes a supporting portion 412, and along the longitudinal direction, the side wall of the supporting portion 412 is retracted relative to the side wall on the same side of the protrusion 410 in the second region II; in the channel structure layer 455, part of the bottom surface of the first channel layer 50 is in contact with the supporting portion 412, so that the supporting portion 412 can also expose part of the bottom surface of the first channel layer 50, and thus the gate structure 430 also surrounds the first channel layer 50 exposed by the supporting portion 412, which correspondingly increases the surrounding area of ​​the gate structure 430 on the first channel layer 50, which is beneficial to improving the control ability of the gate structure 430 on the first channel layer 50, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure.

[0064] In this embodiment, during the formation of the semiconductor structure, after forming the gate opening and removing the partial thickness isolation layer 405 below the gate opening, the sidewalls of the exposed protrusion 410 are thinned, so that only a partial width of the first channel layer 50 is removed along the extension direction perpendicular to the first channel layer 50, so that a portion of the protrusion 410 is retained below the first channel layer 50 and in contact with the first channel layer 50, which is beneficial to improving the process controllability of thinning the sidewalls of the exposed protrusion 410, shortening the process time of etching the exposed protrusion 410, reducing the risk of damage to the bottom of the first channel layer 50 and other film layer structures (for example, the second channel layer 60), and improving process compatibility and stability.

[0065] In this embodiment, the remaining protrusion 410 located at the bottom of the first channel layer 50 includes: a bottom protrusion 411 and a support portion 412 protruding from the bottom protrusion 411; the top surface of the bottom protrusion 411 is flush with or lower than the top surface of the first isolation layer 406.

[0066] In other embodiments, the support portion may further protrude from the substrate in the first region.

[0067] In this embodiment, the protrusion 410 and the first channel layer 50 are an integrated structure.

[0068] In this embodiment, the protrusion 410 and the substrate 400 are an integrated structure.

[0069] In this embodiment, the isolation layer 405 includes a first isolation layer 406 located at the bottom of the gate structure 430 and a second isolation layer 407 exposed from the gate structure 430 . The top surface of the first isolation layer 406 is lower than the top surface of the second isolation layer 407 .

[0070] For the detailed description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiments, and this embodiment will not be repeated here.

[0071] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 33 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0072] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0073] refer to Figure 7, providing a base, including a substrate 100 and a protruding portion 110 protruding from the substrate 100, a stacked structure 200 is formed on the protruding portion 110, the stacked structure 200 includes a first channel layer 40 and one or more channel stacks 210 stacked from bottom to top on the first channel layer 40, each of the channel stacks 210 includes a sacrificial layer 20 and a second channel layer 30 located on the sacrificial layer 20; an isolation layer 105 surrounding the protruding portion 110 is formed on the substrate 100, and the isolation layer 105 exposes the stacked structure 200.

[0074] The substrate is used to provide a process platform for subsequent processes. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for illustration. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field-effect transistor (CFET).

[0075] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single crystal silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0076] In this embodiment, the raised portion 110 and the substrate 100 are integrally formed. The material of the raised portion 110 is the same as that of the substrate 100, namely silicon. In other embodiments, the material of the raised portion may be different from that of the substrate. The material of the raised portion may be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0077] In this embodiment, the protrusion 110 is arranged in a horizontal direction (such as Figure 7 As an example, the stacked structure 200 is a fin structure, and the fin structure is extended in the horizontal direction (as shown in the X direction). Figure 7 The X direction is shown in FIG.

[0078] In the stacked structure 200, the stacking direction of the first channel layer 40 and the channel stack 210 (eg Figure 7 The Z direction is perpendicular to the surface of the substrate 100.

[0079] The channel stack 210 provides a process foundation for the subsequent formation of the second channel layer 30 with a suspended, spaced arrangement. Specifically, the second channel layer 30 and the first channel layer 40 are used to provide a conductive channel for the field-effect transistor, and the sacrificial layer 20 is used to support the second channel layer 30, thereby providing a process foundation for the subsequent realization of the spaced, suspended arrangement of the second channel layer 30. The sacrificial layer 20 also serves to occupy a space for the subsequent formation of the gate structure.

[0080] In this embodiment, an NMOS transistor is formed, and the material of the first channel layer 40 and the second channel layer 30 is Si, and the material of the sacrificial layer 20 is SiGe. During the subsequent removal of the sacrificial layer 20, SiGe and Si have a relatively high etching selectivity. Therefore, by setting the material of the sacrificial layer 20 to SiGe and the material of the first channel layer 40 and the second channel layer 30 to Si, the impact of the sacrificial layer 20 removal process on the first channel layer 40 and the second channel layer 30 can be effectively reduced, thereby improving the quality of the first channel layer 40 and the second channel layer 30, and further facilitating improved device performance.

[0081] In other embodiments, when forming a PMOS transistor, to improve the performance of the PMOS transistor, SiGe channel technology can be used, with the first and second channel layers made of SiGe and the sacrificial layer made of Si. In other embodiments, the material of the first channel layer can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0082] In this embodiment, the first channel layer 40 and the protrusion 110 are an integral structure. Specifically, in this embodiment, the first channel layer 40 and the protrusion 110 and the substrate 100 are an integral structure.

[0083] In this embodiment, in the step of providing the substrate, the sacrificial layer 20 has a first thickness, which defines a filling thickness subsequently formed between adjacent second channel layers 30 or between the first channel layer 40 and the second channel layer 30 .

[0084] As an example, the number of the channel stacks 210 is three. In other embodiments, the number of the channel stacks may be other.

[0085] The isolation layer 105 is used to isolate adjacent protrusions 110 and to isolate the substrate 100 from subsequent gate structures. In this embodiment, the isolation layer 105 is made of silicon oxide. The isolation layer 105 may also be made of other insulating materials.

[0086] refer to Figure 8 , a dummy gate structure 120 is formed on the isolation layer 105 and spans the stacked structure 200 .

[0087] Specifically, the dummy gate structure 120 is located on the isolation layer 105 and covers a portion of the top and a portion of the sidewalls of the stacked structure 200. The dummy gate structure 120 extends along the longitudinal direction.

[0088] The dummy gate structure 120 is used to pre-occupy a space position for the subsequent formation of a gate structure.

[0089] The dummy gate structure 120 may be a stacked structure or a single-layer structure. In this embodiment, the dummy gate structure 120 is a stacked structure, including a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer. Specifically, the dummy gate structure 120 is a polysilicon gate structure, the dummy gate oxide layer may be made of silicon oxide or silicon oxynitride, and the dummy gate layer may be made of polysilicon.

[0090] refer to Figure 9 The method for forming the semiconductor structure further includes forming a gate spacer 130 on the sidewall of the dummy gate structure 120. The gate spacer 130 is used together with the dummy gate structure 120 to serve as an etching mask for a subsequent etching process for forming a groove to define the formation position of the source and drain doped layers. The gate spacer 130 is also used to protect the sidewalls of the dummy gate structure 120 and the subsequent gate structure.

[0091] In this embodiment, the gate spacer 130 is made of silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material, and is a single-layer or stacked-layer structure. As an example, the gate spacer 130 is a single-layer structure, and the material of the gate spacer 130 is silicon nitride.

[0092] refer to Figures 10 to 15 A source-drain doped layer 155 is formed in the stacked structure 200 on both sides of the dummy gate structure 120. The source-drain doped layer 155 is used as the source or drain of the field effect transistor. When the field effect transistor is working, the source-drain doped layer 155 is used to provide a carrier source.

[0093] In this embodiment, the source / drain doped layer 155 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer 155 includes a stress layer doped with N-type ions, and the stress layer material is Si or SiC. When forming a PMOS transistor, the source / drain doped layer 155 includes a stress layer doped with P-type ions, and the stress layer material is Si or SiGe.

[0094] The specific steps of forming the source-drain doped layer 155 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0095] like Figures 10 and 11 As shown, Figure 10 It is a partial stereogram. Figure 11 for Figure 10 In the cross-sectional view along the xx direction, grooves 140 are formed in the stacked structure 200 on both sides of the dummy gate structure 120 .

[0096] The groove 140 is used to provide a space for forming the source and drain doped layers. The sidewalls of the groove 140 expose the stacked structure 200, facilitating the subsequent epitaxial growth of the source and drain doped layers on the sidewalls of the first channel layer 40 and the second channel layer 30 exposed by the groove 140. This also facilitates the subsequent lateral etching of a portion of the thickness of the sacrificial layer 20.

[0097] In this embodiment, the bottom of the groove 140 exposes the substrate. Specifically, the bottom of the groove 140 exposes the top surface of the protrusion 110 .

[0098] In this embodiment, an anisotropic etching process (for example, an anisotropic dry etching process) is used to etch the pseudo-gate structure 120 and the stacked structure 200 on both sides of the gate sidewall 130, which is beneficial to improving the cross-sectional morphology quality of the groove 140, thereby facilitating precise control of the sidewall morphology of the groove 140.

[0099] Specifically, the stacked structure 200 on both sides of the dummy gate structure 120 and the gate spacer 130 is removed to form the groove 140 .

[0100] like Figures 12 to 13 As shown, Figure 12 It is a partial stereogram. Figure 13 for Figure 12 In the cross-sectional view along the xx direction, in this embodiment, after forming the groove 140, the formation method further includes: etching the sacrificial layer 20 along the transverse direction to a thickness of a portion of the sidewall of the groove 140 to form a sidewall groove (not shown), wherein the sidewall groove is surrounded by the adjacent second channel layer 30 and the sacrificial layer 20, or surrounded by the first channel layer 40, the adjacent second channel layer 30, and the sacrificial layer 20; and filling the sidewall groove with an inner spacer 150.

[0101] The side wall groove is used to provide a space for forming an inner side wall.

[0102] In this embodiment, a steam etching process is used to etch the sacrificial layer 20 along the transverse direction to a thickness of a portion of the sidewall of the groove 140. The steam etching process is an isotropic etching process and can etch the sacrificial layer 20 along the transverse direction. The steam etching process can also easily achieve a large etching selectivity, which helps to reduce the difficulty of etching the sacrificial layer 20 and reduce the probability of damage to other film structures (for example, the first channel layer 40 and the second channel layer 30).

[0103] In this embodiment, the sacrificial layer 20 is made of SiGe, and the first and second channel layers 40 and 30 are made of Si. HCl vapor is used to vapor-etch the sacrificial layer 20 on the sidewalls of the recess 140. The etching rate of HCl vapor on SiGe is much higher than that on Si, effectively reducing the probability of damage to the first and second channel layers 40 and 30.

[0104] In other embodiments, when the material of the first channel layer and the second channel layer is SiGe and the material of the sacrificial layer is Si, a dry etching process can be used to etch the sacrificial layer along the sidewall of the groove in the horizontal direction. The etchant of the dry etching process can include a mixture of CF4, O2, and N2 plasma. The difference between the etching rate of the plasma mixture for Si and the etching rate for SiGe is large, which can also effectively reduce the probability of loss of the first channel layer and the second channel layer.

[0105] Subsequently, a source-drain doped layer is formed in the groove 140, and a gate structure is formed at the position of the pseudo-gate structure 120 and the sacrificial layer 20. The inner sidewall 150 is used to achieve isolation between the source-drain doped layer and the gate structure, and also increases the distance between the gate structure and the source-drain doped layer, which is beneficial to reducing the parasitic capacitance between the gate structure and the source-drain doped layer.

[0106] In this embodiment, the inner sidewall 150 is made of an insulating material to isolate the source / drain doped layer from the gate structure. In this embodiment, the material of the inner sidewall 150 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. As an example, the material of the inner sidewall 150 is silicon nitride.

[0107] like Figures 14 and 15 As shown, Figure 14 It is a partial stereogram. Figure 15 (a) Figure 14 Cross-sectional view along the xx direction, Figure 15 (b) Figure 14 In the cross-sectional view along the yy direction, a source-drain doped layer 155 is formed in the groove 140. In this embodiment, an epitaxial process is used to form a stress layer, and ions are in-situ self-doped during the formation of the stress layer. The ion-doped stress layer is used as the source-drain doped layer 155.

[0108] Specifically, epitaxial growth is performed based on the first channel layer 40 , the second channel layer 30 and the protruding portion 110 exposed by the groove 140 .

[0109] As an example, along the horizontal direction, the width of the source / drain doping layer 155 is the same as the opening width of the groove 140 , the source / drain doping layer 155 covers the protrusion 110 at the bottom of the groove 140 , and the source / drain doping layer 155 fills the groove 140 .

[0110] In other embodiments, based on actual process requirements, the morphology and size of the source / drain doping layer can be adjusted according to actual requirements.

[0111] refer to Figures 16 to 18 , Figure 16 For a three-dimensional image, Figure 17 yes Figure 16 A local stereoscopic diagram along the aa1 direction, Figure 18 (a) Yes Figure 16 Cross-section along the xx direction, Figure 18 (b) Yes Figure 16 In the cross-sectional view along the yy direction, an interlayer dielectric layer 160 is formed on the isolation layer 105 on the side of the dummy gate structure 120 , covering the source / drain doped layer 155 . Specifically, the interlayer dielectric layer 160 covers the sidewalls of the gate spacer 130 and the source / drain doped layer 155 .

[0112] The interlayer dielectric layer 160 is used to isolate adjacent devices and also supports the first channel layer 40 and the second channel layer 30 during the subsequent removal of the dummy gate structure 120 and the sacrificial layer 20, thereby achieving a suspended spacing between the first channel layer 40 and the second channel layer 30. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide. The material of the interlayer dielectric layer 160 can also be other insulating materials.

[0113] In this embodiment, the interlayer dielectric layer 160 further exposes the top of the dummy gate structure 120 to facilitate subsequent removal of the dummy gate structure 120 .

[0114] refer to Figures 19 to 20 , Figure 19 Based on Figure 17 A partial three-dimensional schematic diagram of Figure 20 (a) Yes Figure 19 Cross-section along the xx direction, Figure 20 (b) Yes Figure 19 In the cross-sectional view along the yy direction, the dummy gate structure 120 is removed to form a gate opening 170 , exposing the stacked structure 200 and the isolation layer 105 .

[0115] The gate opening 170 is used to provide a space for forming a gate structure and expose the stacked structure 200 so as to facilitate the subsequent removal of the sacrificial layer 20 in the channel stack 210 through the gate opening 170 .

[0116] Furthermore, removing the dummy gate structure 120 also facilitates the subsequent removal of a portion of the thickness of the isolation layer 105 at the bottom of the gate opening 170 through the gate opening 170 , exposing a portion of the sidewall of the protrusion 110 , thereby enabling the subsequent etching of the protrusion 110 exposed by the isolation layer 105 .

[0117] In this embodiment, the gate opening 170 spans the stacked structure 200 , and the gate opening 170 is located in the interlayer dielectric layer 160 .

[0118] Combined with reference Figures 21 to 22 , Figure 21 is based on Figure 19 A partial stereogram of Figure 22 (a) Yes Figure 21 Cross-section along the xx direction, Figure 22 (b) Yes Figure 21 In the cross-sectional view along the yy direction, the method for forming the semiconductor structure further includes: after forming the gate opening 170, before removing a portion of the thickness of the isolation layer 105 at the bottom of the gate opening 170, forming a protective sidewall 190 on the sidewall of the stacked structure 200 exposed by the gate opening 170.

[0119] In the subsequent steps of removing part of the thickness of the isolation layer 105 at the bottom of the gate opening 170, and removing the protrusion 110 exposed by the isolation layer 105 along the extension direction perpendicular to the first channel layer 40, the protective sidewall 190 is used to protect the side walls of the first channel layer 40 and the second channel layer 30, thereby reducing the probability of damage to the first channel layer 40 and the second channel layer 30.

[0120] The protective sidewall 190 is made of a material that has etching selectivity with the material of the protrusion 110 and the isolation layer 105, so that the protective sidewall 190 can protect the first channel layer 40 and the second channel layer 30 in the subsequent process, and in the subsequent process of removing the protective sidewall 190, the protective sidewall 190 has a higher etching selectivity with other film layers, so as to reduce the difficulty of removing the protective sidewall 190 and reduce damage to other film layers.

[0121] In this embodiment, the material of the protective spacer 190 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide, silicon carbonitride, and silicon boron carbide nitride.

[0122] As an embodiment, the material of the protective sidewall 190 is silicon oxycarbide.

[0123] In this embodiment, the step of forming the protective sidewall 190 includes: forming a conformal sidewall material layer (not shown) on the bottom and sidewall of the gate opening 170; and removing the sidewall material layer on the top of the channel stack 210 exposed by the gate opening 170 and the top of the isolation layer 105.

[0124] In this embodiment, the spacer material layer is formed by atomic layer deposition (ALD), which has high step coverage, is conducive to the deposition of the spacer material layer on the bottom and sidewalls of the gate opening 170 , and is also conducive to improving the thickness uniformity of the spacer material layer.

[0125] In this embodiment, an anisotropic etching process is used to remove the spacer material layer located on the top of the channel stack 210 exposed by the gate opening 170 and on the top of the isolation layer 105 .

[0126] refer to Figures 23 to 24 , Figure 23 is based on Figure 21 A partial three-dimensional schematic diagram of Figure 22 yes Figure 21 In the cross-sectional view along the yy direction, a portion of the thickness of the isolation layer 105 at the bottom of the gate opening 170 is removed, exposing a portion of the sidewall of the protrusion 110 .

[0127] Part of the thickness of the isolation layer 105 at the bottom of the gate opening 170 is removed to expose part of the side wall of the protrusion 110, so that the protrusion 110 exposed by the isolation layer 105 can be removed or the side wall of the protrusion 110 exposed by the isolation layer 105 can be thinned in the extension direction perpendicular to the first channel layer 40.

[0128] Subsequently, the raised portion 110 exposed by the isolation layer 105 is removed along an extension direction perpendicular to the first channel layer 40 to form a groove between the first channel layer 40 and the remaining raised portion 110, and the first channel layer 40 is spaced from the remaining raised portion 110 or the substrate 100; or, the sidewall of the exposed raised portion 110 is thinned along an extension direction perpendicular to the first channel layer 40, so that the first channel layer 40 and the remaining raised portion 110 form a groove.

[0129] The trench is used to provide a filling space for the subsequent formation of a gate structure.

[0130] It should be noted that, in the step of removing a portion of the isolation layer 105 at the bottom of the gate opening 170 , the thickness of the isolation layer 105 removed is a second thickness, which is 90% to 110% of the first thickness.

[0131] By setting the removal thickness of the isolation layer 105 within the above-mentioned range, the side wall height of the protrusion 110 exposed by the isolation layer 105 is basically equivalent to the thickness of the sacrificial layer 20. In other words, the side wall height of the protrusion 110 exposed by the isolation layer 105 is slightly different from the thickness of the sacrificial layer 20, so that the height of the groove is slightly different from the height of the through groove formed by the subsequent removal of the sacrificial layer 20, so as to facilitate the filling of the gate structure in the through groove and the groove, which is correspondingly beneficial to improving process compatibility.

[0132] In this embodiment, an anisotropic etching process is used to remove a portion of the thickness of the isolation layer 105 at the bottom of the gate opening 170. Specifically, in this embodiment, an anisotropic dry etching process is used to remove a portion of the thickness of the isolation layer 105 at the bottom of the gate opening 170. The anisotropic dry etching process facilitates precise control of the thickness of the isolation layer 105 removed.

[0133] It should be noted that in the step of removing part of the thickness of the isolation layer 105 at the bottom of the gate opening 170, a protective side wall 190 is also formed on the side wall of the gate opening 170. Therefore, an anisotropic etching process is used to remove part of the thickness of the isolation layer 105 at the bottom of the gate opening 170 exposed by the protective side wall 190.

[0134] In a specific implementation, after using an anisotropic etching process to remove the partial thickness of the isolation layer 105 at the bottom of the gate opening 170 exposed by the protective side wall 190, it can also include: using an isotropic etching process to remove the partial thickness of the isolation layer 105 at the bottom of the protective side wall 190, generally so that after removing the partial thickness of the isolation layer 105 at the bottom of the gate opening 170, the side wall of the isolation layer 105 is flush with the side wall of the gate opening 170.

[0135] Specifically, the isotropic etching process may be any one or both of an isotropic dry etching process and an isotropic wet etching process.

[0136] refer to Figures 25 to 26 , Figure 25 Based on Figure 23 A partial three-dimensional schematic diagram of Figure 26 (a) Figure 25 Cross-section along the xx direction, Figure 26 (b) Figure 25In the cross-sectional view along the yy direction, the protrusion 110 exposed by the isolation layer 105 is removed along the extension direction perpendicular to the first channel layer 40, forming a groove 220 located between the first channel layer 40 and the remaining protrusion 110, and the first channel layer 40 is spaced from the remaining protrusion 110 or the substrate 100.

[0137] By forming the trench 220, the trench 220 can provide space for the subsequent filling of the gate structure at the bottom of the first channel layer 40. Accordingly, in the process of forming the gate structure, the gate structure can also be filled in the trench 220, so that the gate structure not only surrounds the second channel layer 30, but also surrounds the first channel layer 40. Compared with the gate structure only covering the top surface of the first channel layer or only covering the top surface and sidewall of the first channel layer, this embodiment increases the surrounding area of ​​the gate structure on the first channel layer 40, which is beneficial to improving the control ability of the gate structure on the first channel layer 40, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure.

[0138] In this embodiment, in the step of forming the trench 220 , the bottom surface of the trench 220 is lower than or flush with the top surface of the isolation layer 105 at the bottom of the gate opening 170 .

[0139] Specifically, in this embodiment, the bottom surface of the groove 220 is lower than the top surface of the isolation layer 105 at the bottom of the gate opening 170, which is conducive to further increasing the space under the first channel layer 40 for accommodating the gate structure and facilitating the filling of the gate structure under the first channel layer 40.

[0140] Specifically, in this embodiment, a partial thickness of the raised portion 110 is retained at the bottom of the trench 220. In other embodiments, based on actual processes, the raised portion at the bottom of the trench may be completely removed, and the bottom of the trench may expose the substrate.

[0141] In this embodiment, an isotropic etching process is used to remove the exposed protrusion 110 along a direction perpendicular to the extension direction of the first channel layer 40. The isotropic etching process has the characteristic of isotropic etching, and thus can etch the protrusion 110 exposed by the isolation layer 105 along a direction perpendicular to the extension direction of the first channel layer 40, thereby removing the exposed protrusion 110.

[0142] Specifically, the isotropic etching process includes one or both of a dry etching process and a wet etching process.

[0143] It should be noted that for the convenience of illustration and explanation, Figure 23 On the basis of Figure 25 Hidden Figure 23 The isolation layer 105 is located at position A.

[0144] refer to Figure 27 and Figure 28 , Figure 27 is based on Figure 25 A partial three-dimensional schematic diagram of Figure 28 (a) Yes Figure 27 Cross-section along the xx direction, Figure 28 (b) Yes Figure 27 In the cross-sectional view along the yy direction, the method for forming the semiconductor structure further includes: after forming the trench 220 , removing the protective spacer 190 .

[0145] The protective spacer 190 is removed to expose the stacked structure 200 , so that the sacrificial layer 20 can be removed later.

[0146] refer to Figures 29 to 30 , Figure 29 Based on Figure 27 A stereogram of Figure 30 (a) Figure 29 Cross-section along the xx direction, Figure 30 (b) Figure 29 In the cross-sectional view along the yy direction, the sacrificial layer 20 in the channel stack 210 is removed to form a through groove 180 . The through groove 180 is surrounded by the second channel layer 30 and the first channel layer 40 , or by adjacent second channel layers 30 .

[0147] The through-slot 180 and the gate opening 170 together provide a space for forming a gate structure. The through-slot 180 is communicated with the gate opening 170 .

[0148] The sacrificial layer 20 is removed after the source-drain doped layer 155 is formed. Therefore, after removing the sacrificial layer 20, along the horizontal direction, the two ends of the first channel layer 40 are connected to the source-drain doped layer 155, and the two ends of the second channel layer 30 are connected to the source-drain doped layer 155. The first channel layer 40 and the second channel layer 30 are suspended in the gate opening 170 so that the subsequent gate structure can surround the first channel layer 40.

[0149] In this embodiment, after removing the sacrificial layer 20, the first channel layer 40 is spaced apart from the protrusion 110 or the substrate 100, and the second channel layer 30 is spaced apart from the first channel layer 40. When there are multiple second channel layers 30, the multiple second channel layers 30 are spaced apart. The first channel layer 40 and one or more spaced apart second channel layers 30 are used to form a channel structure layer 300.

[0150] In this embodiment, a steam etching process is used to remove the sacrificial layer 20. Specifically, the first channel layer 40 and the second channel layer 30 are made of Si, and the sacrificial layer 20 is made of SiGe. Therefore, the sacrificial layer 20 exposed by the gate opening 170 is removed using HCl vapor. HCl vapor has a high etching selectivity between SiGe and Si, which helps improve the removal efficiency of the sacrificial layer 20 and reduce the probability of damage to the first channel layer 40 and the second channel layer 30.

[0151] refer to Figures 31 to 33 , Figure 31 For a three-dimensional image, Figure 32 for Figure 31 A local stereogram along the a-a1 secant line. Figure 33 (a) Figure 31 Cross-section along the xx direction, Figure 33 (b) Figure 31 In the cross-sectional view along the yy direction, a gate structure 230 is filled in the gate opening 170, the through-groove 180, and the trench 220. The gate structure 230 surrounds the second channel layer 30 and the first channel layer 40. When the device is in operation, the gate structure 230 is used to control the on and off of the conductive channel.

[0152] In this embodiment, the gate structure 230 is a metal gate structure, which includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove 180 and the gate opening 170.

[0153] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0154] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3. In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0155] The work function layer is used to adjust the work function of the gate structure 230, thereby adjusting the threshold voltage of the field-effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.

[0156] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 230 to an external circuit. The gate electrode layer is made of a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0157] In this embodiment, the gate structure 230 is described as a metal gate structure. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0158] Subsequent steps generally include forming source / drain plugs on both sides of the gate structure 230, contacting the source / drain doped layer 155. The source / drain plugs are used to achieve electrical connection between the source / drain doped layer 155 and external circuits or other interconnect structures.

[0159] The subsequent process steps will not be described in detail in this embodiment.

[0160] Figures 34 to 36 1 is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment are not repeated here. The difference between this embodiment and the previous embodiment is that:

[0161] refer to Figure 34 After removing part of the thickness of the isolation layer 405 at the bottom of the gate opening 470 to expose part of the sidewall of the protrusion 410, the sidewall of the exposed protrusion 410 is thinned along the extension direction perpendicular to the first channel layer 50, so that the first channel layer 50 and the remaining protrusion 410 form a groove 420.

[0162] Along an extension direction perpendicular to the first channel layer 50 , the sidewalls of the exposed protrusions 410 are thinned to form trenches 420 . The trenches 420 can provide space for subsequent filling of gate structures at the bottom of the first channel layer 50 .

[0163] Accordingly, in the process of forming the gate structure, the gate structure can also be filled in the groove 420, so that the gate structure not only surrounds the second channel layer 60, but also surrounds the first channel layer 50 exposed by the protrusion 410. Compared with the gate structure only covering the top surface of the first channel layer 50 or only covering the top surface and side wall of the first channel layer 50, this embodiment increases the surrounding area of ​​the gate structure on the first channel layer 50, which is beneficial to improving the control ability of the gate structure on the first channel layer 50, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure.

[0164] Moreover, in this embodiment, the sidewalls of the exposed protrusions 410 are thinned, so that only a portion of the width of the first channel layer 50 is removed along the extension direction perpendicular to the first channel layer 50, so that a portion of the protrusions 410 remains below the first channel layer 50 in contact with the first channel layer 50, which is beneficial to improving the process controllability of thinning the sidewalls of the exposed protrusions 410, shortening the process time of etching the exposed protrusions 410, and reducing the risk of damage to the bottom of the first channel layer 50 and other film layer structures (for example, the second channel layer 60).

[0165] In this embodiment, an isotropic etching process is used to thin the sidewalls of the exposed protrusion 410 along a direction perpendicular to the extension direction of the first channel layer 50. Specifically, the isotropic etching process may include one or both of a wet etching process and an isotropic dry etching process.

[0166] In this embodiment, after the side walls of the exposed protrusion 410 are thinned along the extension direction perpendicular to the first channel layer 50, the remaining protrusion 410 located at the bottom of the first channel layer 50 includes a bottom protrusion 411 and a support portion 412 protruding from the bottom protrusion 411, or the remaining protrusion 410 located at the bottom of the first channel layer 50 only includes the support portion 412 protruding from the substrate 400.

[0167] Furthermore, along the extending direction perpendicular to the first channel layer 50 , the sidewalls of the support portion 412 are retracted relative to the sidewalls of the protrusions 410 on the same side of the stacked structure (not shown) along the extending direction perpendicular to the first channel layer 50 .

[0168] As one embodiment, the remaining protrusion 410 located at the bottom of the first channel layer 50 includes a bottom protrusion 411 and a support portion 412 protruding from the bottom protrusion 411, and the top surface of the bottom protrusion 411 is flush with or lower than the isolation layer 405 located on both sides of the stacked structure along the extension direction perpendicular to the first channel layer 50.

[0169] Accordingly, reference Figures 35 to 36 , Figure 35 For a three-dimensional image, Figure 36 (a) Figure 35 Cross-section along the xx direction, Figure 36 (b) Figure 35 In the cross-sectional view along the yy direction, in the step of filling the gate structure 430 in the gate opening 470 and the through groove 420 and the groove (not shown), the gate structure 430 surrounds the second channel layer 60 , and the gate structure 430 also surrounds the first channel layer 50 exposed by the protrusion 410 .

[0170] The gate structure 430 can also be filled in the groove 420, so that the gate structure 430 not only surrounds the second channel layer 60, but also surrounds the first channel layer 50 exposed by the protrusion 410. Compared with the gate structure only covering the top surface of the first channel layer or only covering the top surface and side wall of the first channel layer, this embodiment increases the surrounding area of ​​the first channel layer 50 by the gate structure 430, which is beneficial to improving the control ability of the gate structure 430 over the first channel layer 50, thereby reducing the leakage current of the device and improving the performance of the semiconductor structure.

[0171] For a detailed description of the gate structure 430 , reference may be made to the corresponding description of the aforementioned embodiment, which will not be repeated herein.

[0172] For a detailed description of the method for forming the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiments, which will not be repeated in this embodiment.

[0173] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A base, comprising a transversely extending region extending in a transverse direction, the transversely extending region comprising a first region and second regions located on both sides of the first region in the transverse direction; the base comprising: a substrate; and a raised portion, the raised portion protruding from the substrate in the second region, or the raised portion protruding from the substrate in the transversely extending region, and a top surface of the raised portion in the first region being lower than a top surface of the raised portion in the second region; a channel structure layer located above the substrate in the first region, with a bottom surface of the channel structure layer being higher than or flush with a top surface of the raised portion in the second region, the channel structure layer comprising a first channel layer and one or more second channel layers sequentially arranged from bottom to top, wherein the first channel layer and the second channel layer are both continuous channels along an extension direction, and a gap is formed between the first channel layer and the substrate; an isolation layer located on the substrate and surrounding the protrusion; a gate structure located on the isolation layer and spanning the channel structure layer, the gate structure filling between the first channel layer and the substrate, and between the first channel layer and the second channel layer, or the gate structure filling between the first channel layer and the substrate, between the first channel layer and the second channel layer, and between adjacent second channel layers; the gate structure surrounds the first channel layer and the second channel layer; The source-drain doped layers are located on the raised portions of the second region on both sides of the gate structure, and the source-drain doped layers are in contact with the first channel layer and end portions of one or more second channel layers along the extension direction.

2. The semiconductor structure according to claim 1, wherein The isolation layer includes a first isolation layer located at the bottom of the gate structure and a second isolation layer exposed from the gate structure, and a top surface of the first isolation layer is lower than a top surface of the second isolation layer.

3. The semiconductor structure according to claim 2, wherein: Along the direction perpendicular to the substrate surface, the distance between the first channel layer and the adjacent second channel layer is a first dimension; the height difference between the top surface of the first isolation layer and the top surface of the second isolation layer is a second dimension, and the second dimension is 90% to 110% of the first dimension.

4. The semiconductor structure according to claim 2, wherein: The protrusion protrudes from the substrate of the lateral extension region, and a top surface of the protrusion in the first region is flush with or lower than a top surface of the first isolation layer.

5. The semiconductor structure according to claim 1, wherein The gate structure includes a first portion spanning the channel structure layer, and a second portion located between the first channel layer and the substrate of the first region, between the first channel layer and the second channel layer, or between adjacent second channel layers; Along the transverse direction, the sidewall of the first portion is retracted relative to the sidewall of the first channel layer, and the sidewall of the second portion is retracted relative to the sidewall of the first channel layer; The semiconductor structure further includes: a gate spacer located on a sidewall of the first portion; The inner side wall is located on the side wall of the second part.

6. The semiconductor structure according to claim 1, wherein When the protrusion protrudes from the substrate of the lateral extension area, the protrusion is an integrated structure.

7. The semiconductor structure according to claim 1, wherein: The first channel layer and the protrusion are made of the same material.

8. The semiconductor structure according to claim 1, 6 or 7, wherein: The protrusion and the substrate are an integrated structure.

9. The semiconductor structure according to claim 1, wherein: The material of the substrate includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium; The material of the protrusion includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium; The material of the first channel layer includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium; The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon germanium oxide.

10. The semiconductor structure according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

11. The semiconductor structure according to claim 10, wherein: The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

12. A semiconductor structure, characterized in that include: A substrate comprising a transverse extension region extending in a transverse direction, wherein a direction parallel to the substrate and perpendicular to the transverse direction is a longitudinal direction; the transverse extension region comprises a first region and second regions located on both sides of the first region in the transverse direction; the substrate comprising: a substrate; a raised portion protruding from the substrate in the transverse extension region, the raised portion located in the first region comprising a support portion, and wherein a sidewall of the support portion is retracted relative to a sidewall of the raised portion in the second region on the same side as the raised portion in the longitudinal direction; a channel structure layer located on the support portion, the channel structure layer comprising a first channel layer and one or more second channel layers sequentially spaced from bottom to top, with a portion of the bottom surface of the first channel layer in contact with the support portion, the first channel layer and the second channel layer both being continuous channels along an extension direction, and a gap between the first channel layer and the substrate; an isolation layer located on the substrate and surrounding the protrusion; a gate structure located on the isolation layer, spanning the channel structure layer and surrounding the second channel layer, and the gate structure also surrounds the first channel layer exposed by the support portion; The source-drain doped layers are located on the raised portions of the second region on both sides of the gate structure, and the source-drain doped layers are in contact with the first channel layer and end portions of one or more second channel layers along the extension direction.

13. The semiconductor structure according to claim 12, wherein: The isolation layer includes a first isolation layer located at the bottom of the gate structure and a second isolation layer exposed from the gate structure, and a top surface of the first isolation layer is lower than a top surface of the second isolation layer.

14. The semiconductor structure according to claim 13, wherein: The raised portion located in the first region includes: a bottom raised portion located on the substrate of the first region, and the support portion protruding from the bottom raised portion; the top surface of the bottom raised portion is flush with or lower than the top surface of the first isolation layer; Alternatively, the support portion protrudes from the substrate in the first region.

15. The semiconductor structure according to claim 12, wherein: The protrusion and the first channel layer are an integrated structure.

16. The semiconductor structure according to claim 12 or 15, wherein: The protrusion and the substrate are an integrated structure.

17. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, comprising a substrate and a raised portion protruding from the substrate, wherein a stacked structure is formed on the raised portion, the stacked structure comprising a first channel layer and one or more channel stacks stacked sequentially from bottom to top and located on the first channel layer, each of the channel stacks comprising a sacrificial layer and a second channel layer located on the sacrificial layer; an isolation layer surrounding the raised portion is formed on the substrate, the isolation layer exposing the stacked structure, and the first channel layer and the second channel layer are both continuous channels along an extension direction; forming a dummy gate structure on the isolation layer and spanning the stacked structure; forming source-drain doped layers in the stacked structure on both sides of the dummy gate structure, wherein the source-drain doped layers are in contact with the first channel layer and end portions of one or more second channel layers along the extension direction; removing the dummy gate structure to form a gate opening, exposing the stacked structure and the isolation layer; removing a portion of the thickness of the isolation layer at the bottom of the gate opening to expose a portion of the sidewall of the protrusion; removing the protrusion exposed by the isolation layer along an extension direction perpendicular to the first channel layer to form a groove between the first channel layer and the remaining protrusion, with the first channel layer spaced apart from the remaining protrusion or the substrate; Alternatively, the sidewalls of the exposed protrusions are thinned along an extension direction perpendicular to the first channel layer, so that the first channel layer and the remaining protrusions form a groove, and a gap is formed between the first channel layer and the substrate; removing a sacrificial layer in the channel stack to form a through-groove, wherein the through-groove is surrounded by the second channel layer and the first channel layer, or by an adjacent second channel layer; A gate structure is filled in the gate opening, the through-groove, and the trench, and the gate structure surrounds the second channel layer. The gate structure also surrounds the first channel layer or the first channel layer exposed by the protrusion.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming a semiconductor structure further comprises: after forming the gate opening and before removing a portion of the thickness of the isolation layer at the bottom of the gate opening, forming a protective sidewall on the sidewall of the stacked structure exposed by the gate opening; After forming the trench, the sacrificial layer in the channel stack is removed, and before forming the through-groove, the protective sidewall is removed.

19. The method for forming a semiconductor structure according to claim 17, wherein: In the step of providing a substrate, the thickness of the sacrificial layer is a first thickness; in the step of removing part of the thickness of the isolation layer at the bottom of the gate opening, the removed thickness of the isolation layer is a second thickness, and the second thickness is 90% to 110% of the first thickness.

20. The method for forming a semiconductor structure according to claim 17, wherein: An isotropic etching process is adopted to remove the exposed protrusion or thin the sidewall of the exposed protrusion along an extension direction perpendicular to the first channel layer.

21. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming the trench, the bottom surface of the trench is lower than or flush with the top surface of the isolation layer at the bottom of the gate opening.

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