Light-emitting diode with improved fracture and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode (LED) with improved fracture resistance and a method for manufacturing the same, belonging to the field of optoelectronic manufacturing technology. The LED comprises: a substrate, an epitaxial layer, a first electrode, and a second electrode. The epitaxial layer has a rectangular projection on the substrate. The surface of the epitaxial layer has a groove, the groove being located at one side of the rectangle and extending from one end of the side to the other. The first electrode is located in the groove, and the second electrode is located outside the groove. The embodiments of the present disclosure can improve the strength of the LED and improve the problem of LEDs being easily fractured after the groove is formed in the epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved fracture resistance and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a light-emitting diode chip typically includes a substrate, an epitaxial layer, and two electrodes. The epitaxial layer includes an n-type layer, a multi-quantum well layer, and a p-type layer, stacked sequentially on the substrate. One electrode is located on the p-type layer and electrically connected to it. Furthermore, the epitaxial layer is provided with a groove that exposes the n-type layer, and the other electrode is placed in the groove to electrically connect it to the n-type layer.

[0004] After the grooves are formed by etching the epitaxial layer, the strength of the epitaxial layer will be weakened to a certain extent, which may cause the light emitting diode to be easily broken at the step where the grooves are formed. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode with improved fracture resistance and a method for manufacturing the same, which can improve the strength of the light-emitting diode and alleviate the problem of the light-emitting diode being easily fractured after grooves are formed in the epitaxial layer. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes: a substrate, an epitaxial layer, a first electrode and a second electrode, the epitaxial layer having an orthographic projection on the substrate being a rectangle, the surface of the epitaxial layer having a groove, the groove being located at a side of the rectangle and extending from one end of the side to the other end, the first electrode being located in the groove, and the second electrode being located outside the groove.

[0007] Optionally, the ratio of the groove width to the length of the side adjacent to the side of the rectangle where the groove is located is not greater than 1 / 5.

[0008] Optionally, the angle between the side wall of the groove and the bottom surface of the groove is an obtuse angle.

[0009] Optionally, the obtuse angle is not greater than 120°.

[0010] Optionally, the epitaxial layer includes an n-type layer, a multi-quantum well layer and a p-type layer stacked in sequence, the groove is located on the surface of the p-type layer and exposes the n-type layer; silicon ions are implanted in a first local area of ​​the p-type layer, and the first local area is adjacent to the groove.

[0011] Optionally, the first local area includes a first frame-shaped portion and a second frame-shaped portion, the first frame-shaped portion extends along an edge of the p-type layer, the second frame-shaped portion is located within the first frame-shaped portion, and the amount of silicon ions injected per unit volume in the first frame-shaped portion is higher than the amount of silicon ions injected per unit volume in the second frame-shaped portion.

[0012] Optionally, silicon ions are injected into a second local area of ​​the p-type layer, the second local area is arc-shaped, and is located within the second frame-shaped portion, and the amount of silicon ions injected per unit volume in the second local area is higher than the amount of silicon ions injected per unit volume in the second frame-shaped portion, and lower than the amount of silicon ions injected per unit volume in the first frame-shaped portion.

[0013] Optionally, in the thickness direction of the p-type layer, both the first local region and the second local region are located in the middle of the p-type layer.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode chip with improved luminous efficiency, the preparation method comprising: providing a substrate; forming an epitaxial layer on the substrate, the orthographic projection of the epitaxial layer on the substrate being a rectangle, the surface of the epitaxial layer having a groove, the groove being located at one side of the rectangle and extending from one end of the side to the other end; making a first electrode and a second electrode on the epitaxial layer, the first electrode being located in the groove, and the second electrode being located outside the groove.

[0015] Optionally, the epitaxial layer includes an n-type layer, a multi-quantum well layer and a p-type layer stacked in sequence, the groove is located on the surface of the p-type layer and exposes the n-type layer; silicon ions are injected into a first local area of ​​the p-type layer, and the first local area is adjacent to the groove. When growing the p-type layer, the preparation method includes: growing a first p-type material layer; forming a photoresist layer on the surface of the first p-type material layer, the photoresist layer having an injection groove exposing the first p-type material layer, the orthographic projection of the injection groove on the substrate coincides with the orthographic projection of the first local area on the substrate; injecting silicon ions into the first p-type material layer through the injection groove; removing the photoresist layer, growing a second p-type material layer, and obtaining the p-type layer.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode chip provided by the disclosed embodiments includes an epitaxial layer stacked on a substrate. The epitaxial layer's orthographic projection on the substrate is a rectangle. A groove in the epitaxial layer, used to connect the electrode and the semiconductor layer, is located along one side of the rectangle, extending from one side of the epitaxial layer to the other along the side of the rectangle. Because the groove is located along the side of the rectangle, the external force required to break the thinned area of ​​the epitaxial layer corresponding to the groove is greater. This effectively reduces the risk of breakage associated with the groove in the epitaxial layer, improves the problem of the light-emitting diode being easily broken after the groove is provided, and enhances the strength and stability of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a cross-sectional view of a light emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic structural diagram of an epitaxial layer provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic diagram of the hierarchical structure of an epitaxial layer provided by an embodiment of the present disclosure;

[0023] Figure 5 This is a flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0024] The descriptions of the marks in the figure are as follows:

[0025] 10. Substrate;

[0026] 20. epitaxial layer; 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer; 230. local region; 231. first frame portion; 232. second frame portion; 240. second local region; 24. groove;

[0027] 31. First electrode; 32. Second electrode;

[0028] 40. passivation layer; 41. first via hole; 42. second via hole;

[0029] 51. First soldering point block; 52. Second soldering point block. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0031] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] Figure 1 FIG. 1 is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the photodiode includes: a substrate 10, an epitaxial layer 20, a first electrode 31 and a second electrode 32. The orthographic projection of the epitaxial layer 20 on the substrate 10 is a rectangle. The surface of the epitaxial layer 20 has a groove 24. The groove 24 is located at the side of the rectangle and extends from one end of the side to the other end. The first electrode 31 is located in the groove 24, and the second electrode 32 is located outside the groove 24. Both are connected to the epitaxial layer 20.

[0033] For example, Figure 1 As shown, the orthographic projection of the epitaxial layer 20 on the substrate 10 may be a rectangle, and the groove is disposed at one long side of the rectangle and extends from one end to the other end of the long side.

[0034] The light-emitting diode chip provided in the embodiments of the present disclosure includes an epitaxial layer 20 stacked on a substrate 10. The orthographic projection of epitaxial layer 20 on substrate 10 is a rectangle. Grooves 24 in epitaxial layer 20, used to connect the electrode and the semiconductor layer, are distributed along the long sides of the rectangle. Grooves 24 extend from one side of epitaxial layer 20 to the other along the long sides of the rectangle. Compared to light-emitting diodes in the related art in which grooves 24 are arranged along the short sides, the placement of grooves 24 along the long sides of the rectangle increases the external force required to fracture the thinned areas of epitaxial layer 20 corresponding to grooves 24. Therefore, the risk of fracture caused by the formation of grooves 24 in epitaxial layer 20 is effectively reduced, improving the problem of the light-emitting diode being easily fractured after grooves 24 are formed in the epitaxial layer 20, and enhancing the strength and stability of the light-emitting diode.

[0035] It should be noted that the orthographic projection of the epitaxial layer 20 on the substrate 10 may also be a square, a parallelogram or other shapes, which is not limited in the embodiment of the present disclosure.

[0036] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0037] Figure 2 It is a cross-sectional view of a light-emitting diode provided by an embodiment of the present disclosure. Figure 2 Therefore Figure 1 The dotted line AA in the figure is the section cut by the section line. Figure 2 As shown, the epitaxial layer 20 may include a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 sequentially stacked outside the substrate 10. The groove 24 is located on the surface of the second semiconductor layer 23 and extends to the surface of the first semiconductor layer 21.

[0038] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0039] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0040] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0041] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0042] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0043] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0044] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0045] In the embodiment of the present disclosure, Figure 2 As shown, the light emitting diode further includes a passivation layer 40 , which is located at least on the first semiconductor layer 21 , the second semiconductor layer 23 , the groove 24 and the two electrodes of the epitaxial layer 20 .

[0046] Alternatively, the passivation layer 40 may be a distributed Bragg reflector (DBR) layer, which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0047] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0048] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0049] Alternatively, as Figure 2 As shown, the light-emitting diode further includes a first soldering point block 51 and a second soldering point block 52. The passivation layer 40 has a first via hole 41 exposing the first electrode 31 and a second via hole 42 exposing the second electrode 32. The first soldering point block 51 and the second soldering point block 52 are located on the passivation layer 40. The first soldering point block 51 is connected to the first electrode 31 through the first via hole 41, and the second soldering point block 52 is connected to the second electrode 32 through the second via hole 42.

[0050] A plurality of first via holes 41 may be provided on the passivation layer 40 so that the first soldering block 51 can have a larger area for connection with the first electrode 31 , thereby improving the electrical connection stability between the first soldering block 51 and the first semiconductor layer 21 .

[0051] For example, Figure 1 As shown, three first via holes 41 are provided on the passivation layer 40 , and the three first via holes 41 are distributed at intervals.

[0052] Optionally, the first soldering point block 51 and the second soldering point block 52 are both rectangular blocks to increase the area and facilitate electrical conduction.

[0053] Alternatively, as Figure 1 As shown, the ratio of the groove width L1 of the groove 24 to the length L2 of the side adjacent to the side where the upper rectangular groove 24 is located is not greater than 1 / 5.

[0054] By limiting the groove width of the groove 24 within the above range, it is possible to avoid setting the groove width of the groove 24 too large, which would cause the groove 24 to be too large and cause too much area on the epitaxial layer 20 to be thinned, thereby increasing the risk of fracture of the epitaxial layer 20 after the groove 24 is opened.

[0055] Exemplarily, the ratio of the groove width of the groove 24 to the short side of the rectangle is 1 / 10.

[0056] Alternatively, as Figure 2 As shown, the angle α between the sidewall of the groove 24 and the bottom surface of the groove 24 is an obtuse angle. Exemplarily, the sidewall of the groove 24 is an inclined surface, and the angle α between the sidewall and the bottom surface of the groove 24 is not greater than 120°.

[0057] By setting the sidewall of the groove 24 as a slope, the epitaxial layer 20 can transition more smoothly from the second semiconductor layer 23 to the bottom of the groove 24 at the step, thereby reducing stress concentration in this area and further reducing the risk of light-emitting diode breakage.

[0058] For example, Figure 2 As shown, the angle α between the side wall of the groove 24 and the bottom surface of the groove 24 is 120°.

[0059] In the embodiment of the present disclosure, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer. Figure 2 As shown, the epitaxial layer 20 includes an n-type layer, a multi-quantum well layer 22 and a p-type layer stacked in sequence, and the groove 24 is located on the surface of the p-type layer and exposes the n-type layer.

[0060] Figure 3 FIG. 2 is a schematic diagram of the structure of an epitaxial layer 20 provided in an embodiment of the present disclosure. Figure 3 As shown, silicon ions are implanted into the first local region 230 of the p-type layer, and the first local region 230 is adjacent to the groove 24 .

[0061] The first local region 230 of the p-type layer is adjacent to the groove 24 and is located near the side of the groove 24. Silicon ions are also injected into the first local region 230. The silicon ions replace the gallium ions in the semiconductor layer. Gallium ions are typically trivalent, while silicon ions are tetravalent. After the silicon ions replace the gallium ions, an additional electron is generated in the semiconductor layer. Because a large number of holes are distributed in the p-type layer, injecting silicon ions into the first local region 230 can neutralize the holes in the first local region 230, thereby reducing the number of neutralized carriers entering the first local region 230 from the n-type layer and causing a sharp drop in the current in the first local region 230. Because the first local region 230 is located near the side of the groove 24, it effectively reduces the current in the area of ​​the epitaxial layer 20 where the groove 24 is located, preventing leakage caused by defects in the semiconductor layer after etching the groove 24, thereby improving the light efficiency of the LED chip.

[0062] Alternatively, as Figure 3 As shown, the first local area 230 includes a first frame-shaped portion 231 and a second frame-shaped portion 232, the first frame-shaped portion 231 extends along the edge of the p-type layer, the second frame-shaped portion 232 is located within the first frame-shaped portion 231, and the amount of silicon ions injected per unit volume in the first frame-shaped portion 231 is higher than the amount of silicon ions injected per unit volume in the second frame-shaped portion 232.

[0063] In the embodiment of the present disclosure, the first frame portion 231 is closer to the groove 24, so the amount of silicon ions injected per unit volume in the first frame portion 231 is greater, so as to neutralize most of the holes in the first frame portion 231, thereby significantly reducing the current of the first frame portion 231, effectively preventing the problem of leakage caused by defects generated after etching the groove 24 on the semiconductor layer, and improving the light efficiency of the light-emitting diode.

[0064] For example, the amount of silicon ions implanted into the first frame portion 231 can neutralize 70% to 90% of the holes in the first frame portion 231 , so that the conductivity of the region where the first frame portion 231 is located reaches 10% to 30%.

[0065] In the embodiment of the present disclosure, the second frame-shaped portion 232 is an area connected to the first frame-shaped portion 231. The second frame-shaped portion 232 is farther away from the groove 24 than the first frame-shaped portion 231. Therefore, the amount of silicon ions injected per unit volume in the second frame-shaped portion 232 can be less than that in the first frame-shaped portion 231, so as to neutralize a portion of the holes in the second frame-shaped portion 232 and reduce the current in the second frame-shaped portion 232. In this way, the second frame-shaped portion 232 is provided as a transition structure between the first frame-shaped portion 231 and other film layers of the p-type layer, which can prevent the current density in the other film layers of the p-type layer from being too high and easily diffusing to the first frame-shaped portion 231, that is, preventing the current from diffusing to the area where the groove 24 is located, so that the light efficiency is significantly improved, thereby improving the brightness of the light-emitting diode.

[0066] For example, the amount of silicon ions implanted into the second frame portion 232 may neutralize 30% to 40% of the holes in the second frame portion 232 , so that the conductivity of the region where the second frame portion 232 is located reaches 60% to 70%.

[0067] In the embodiment of the present disclosure, the use of silicon ions to neutralize holes has a better effect, can effectively reduce the current density of the first local area 230, and effectively prevent the problem of leakage caused by defects generated after etching the grooves 24 on the semiconductor layer.

[0068] For example, Figure 3 As shown, the first frame portion 231 and the second frame portion 232 are both distributed along the edge of the second semiconductor layer 23 .

[0069] The edge of the second semiconductor layer 23 refers to the outer contour of the orthographic projection of the second semiconductor layer 23 on the substrate 10 .

[0070] like Figure 3 As shown, the first frame portion 231 and the second frame portion 232 are not only close to the sidewalls of the groove 24, but also close to the sidewalls of the epitaxial layer 20. In this way, the first frame portion 231 and the second frame portion 232 can effectively reduce the current in the area where the upper side of the epitaxial layer 20 is located, preventing the problem of leakage caused by defects in the sidewalls of the epitaxial layer 20, and improving the light efficiency of the LED chip.

[0071] Alternatively, as Figure 3 As shown, silicon ions are injected into the second local area 240 of the p-type layer. The second local area 240 is arc-shaped and is located within the second frame-shaped portion 232. The amount of silicon ions injected per unit volume in the second local area 240 is higher than the amount of silicon ions injected per unit volume in the second frame-shaped portion 232, and is lower than the amount of silicon ions injected per unit volume in the first frame-shaped portion 231.

[0072] By providing the second local region 240 in the second frame portion 232, and with the amount of silicon ions implanted per unit volume in the second local region 240 being between the amount of silicon ions implanted per unit volume in the first frame portion 231 and the second frame portion 232, the provision of the second local region 240 can effectively suppress current diffusion toward the groove 24, thereby significantly improving the light efficiency and thus the brightness of the light-emitting diode.

[0073] At the same time, the area of ​​the second local region 240 is smaller than that of the first frame portion 231 and the second frame portion 232. In this way, the second local region 240 with a smaller area is set to suppress the diffusion of current, and it can also avoid the area used for light emission in the epitaxial layer 20 from neutralizing too many holes, thereby ensuring the light-emitting effect of the epitaxial layer 20.

[0074] In the embodiment of the present disclosure, the second local area 240 is located between the first electrode 31 and the second electrode 32 , and the arc-shaped second local area 240 can be distributed around the second electrode 32 , so that the second electrode 32 can effectively prevent carriers from flowing from the second electrode 32 to the first electrode 31 .

[0075] Figure 4 Schematic diagram of the hierarchical structure of an epitaxial layer 20 provided in an embodiment of the present disclosure. Figure 4 Therefore Figure 3 The dotted line MM in the figure is the section cut by the section line. Figure 4 As shown, in the thickness direction of the p-type layer, the first local region 230 and the second local region 240 are located in the middle of the p-type layer.

[0076] In this way, the first local region 230 and the second local region 240 are spaced apart from the multi-quantum well layer 22 , thereby preventing the first local region 230 and the second local region 240 from directly contacting the multi-quantum well layer 22 and blocking current transfer.

[0077] Optionally, in the thickness direction of the p-type layer, the distance between the first local region 230 and the second local region 240 and the multi-quantum well layer 22 is 500 angstroms to 1500 angstroms.

[0078] By setting the distance between the first local region 230 and the second local region 240 and the multi-quantum well layer 22 within the above range, it is avoided that the distance between the first local region 230 and the second local region 240 and the multi-quantum well layer 22 is too small, so that the first local region 230 and the second local region 240 block current transmission.

[0079] For example, in the embodiment of the present disclosure, the distance between the first local region 230 and the second local region 240 and the multi-quantum well layer 22 is 1000 angstroms.

[0080] Optionally, the thickness of the first local region 230 and the second local region 240 are both 8000 angstroms to 12000 angstroms.

[0081] By setting the thickness of the first local area 230 and the second local area 240 within the above-mentioned range, it is possible to avoid the problem that the thickness of the first local area 230 and the second local area 240 is too small, which will fail to improve the problem of leakage caused by defects generated after etching the groove 24; it is also possible to avoid the problem that the thickness of the first local area 230 and the second local area 240 is too large, which will increase the amount of injected silicon ions, thereby increasing the preparation cost of the light-emitting diode chip.

[0082] For example, in the embodiment of the present disclosure, the thickness of the first local region 230 and the second local region 240 are both 10,000 angstroms.

[0083] Figure 5This is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figures 1 to 4 The light emitting diode chip shown. Figure 5 As shown, the preparation method comprises:

[0084] S11: providing a substrate 10.

[0085] S12 : forming an epitaxial layer 20 on the substrate 10 .

[0086] The orthographic projection of the epitaxial layer 20 on the substrate 10 is a rectangle. The surface of the epitaxial layer 20 has a groove 24 . The groove 24 is located at one side of the rectangle and extends from one end to the other end of the side.

[0087] For example, Figure 1 As shown, the orthographic projection of the epitaxial layer 20 on the substrate 10 may be a rectangle, and the groove is disposed at one long side of the rectangle and extends from one end to the other end of the long side.

[0088] S13: forming a first electrode and a second electrode on the epitaxial layer.

[0089] The light-emitting diode fabricated using this method includes an epitaxial layer 20 stacked on a substrate 10. The orthographic projection of epitaxial layer 20 on substrate 10 is a rectangle. Grooves 24 in epitaxial layer 20, used to connect the electrode and the semiconductor layer, are located along the long sides of the rectangle, extending from one side of epitaxial layer 20 to the other along the long sides of the rectangle. Compared to related art light-emitting diodes in which grooves 24 are arranged along the short sides, the placement of grooves 24 along the long sides of the rectangle increases the external force required to fracture the thinned areas of epitaxial layer 20 corresponding to grooves 24. This effectively reduces the risk of fracture associated with grooves 24 in epitaxial layer 20, improves the problem of the light-emitting diode being susceptible to fracture after grooves 24 are provided in the epitaxial layer 20, and enhances the strength and stability of the light-emitting diode.

[0090] In step S11, the substrate 10 is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0091] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate. Sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0092] The sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0093] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0094] Growing the epitaxial layer 20 on the substrate 10 in step S12 may include: sequentially forming a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 on the sapphire substrate by using MOCVD technology.

[0095] The first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0096] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0097] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 Torr to 300 Torr.

[0098] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0099] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 Torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0100] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0101] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0102] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0103] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0104] After the epitaxial layer 20 is formed in step S12 , the second semiconductor layer 23 may be etched to form a groove 24 exposing the first semiconductor layer 21 .

[0105] For example, in the embodiment of the present disclosure, the second semiconductor layer 23 may be a p-type layer.

[0106] When growing the p-type layer, the preparation method may include:

[0107] A first p-type material layer is grown; a photoresist layer is formed on the surface of the first p-type material layer, the photoresist layer having an injection groove exposing the first p-type material layer, the orthographic projection of the injection groove on the substrate 10 coincides with the orthographic projections of the first local area 230 and the second local area 240 on the substrate 10; silicon ions are injected into the first p-type material layer through the injection groove; the photoresist layer is removed, and a second p-type material layer is grown to obtain a p-type layer.

[0108] Specifically, when growing the first semiconductor layer 21 , a first p-type material layer may be formed first.

[0109] The thickness of the first p-type material layer may be 8500 angstroms to 13500 angstroms.

[0110] For example, a first p-type material layer is grown to a thickness of 11,000 angstroms.

[0111] Next, a first photoresist layer is formed on the surface of the grown first p-type material layer. The first photoresist layer exposes a first region of the first p-type material layer. Silicon ions are implanted into the first region to form a first frame portion 231 of the local region 230 .

[0112] Then, the first photoresist layer is removed and a second photoresist layer is formed on the surface of the first p-type material layer. The second photoresist layer exposes the second region of the first p-type material layer. Silicon ions are implanted into the second region to form a second frame portion 232 of the local region 230.

[0113] Next, the second photoresist layer is removed, and a third photoresist layer is formed on the surface of the first p-type material layer. The third photoresist layer exposes a third region of the first p-type material layer. Silicon ions are implanted into the third region to form a second local region 240 .

[0114] The amount of silicon ions implanted per unit volume in the first frame portion 231 is greater than the amount of silicon ions implanted per unit volume in the second frame portion 232. The amount of silicon ions implanted per unit volume in the second local region 240 is greater than the amount of silicon ions implanted per unit volume in the second frame portion 232, but less than the amount of silicon ions implanted per unit volume in the first frame portion 231.

[0115] In the embodiment of the present disclosure, the first frame portion 231 is closer to the groove 24, so the amount of silicon ions injected per unit volume in the first frame portion 231 is greater, so as to neutralize most of the holes in the first frame portion 231, thereby significantly reducing the current of the first frame portion 231, effectively preventing the problem of leakage caused by defects generated after etching the groove 24 on the semiconductor layer, and improving the light efficiency of the light-emitting diode.

[0116] Next, the third photoresist layer is removed, and a second p-type material layer is grown to form a p-type layer.

[0117] After forming the epitaxial layer 20, the preparation method further includes the following steps:

[0118] Step 1: etching the second semiconductor layer 23 to form a groove 24 exposing the first semiconductor layer 21 .

[0119] Specifically, the method may include: etching the second semiconductor layer 23 by dry etching to expose the first semiconductor layer 21 .

[0120] The sidewall of the groove 24 is an inclined surface, and the angle between the sidewall and the bottom surface of the groove 24 is no greater than 120°.

[0121] After the grooves 24 are formed, a transparent conductive layer may be formed on the second semiconductor layer 23 .

[0122] Optionally, the transparent conductive layer can be an indium tin oxide (ITO) film. ITO films have good transmittance and low resistivity. Using ITO as the transparent conductive layer allows more light to be transmitted through the transparent conductive layer, thereby ensuring the desired effect. Furthermore, due to its low resistivity, it facilitates carrier conduction and improves injection efficiency.

[0123] Exemplarily, the thickness of each transparent conductive layer may be 800 angstroms to 1200 angstroms.

[0124] Step 2: Prepare the first electrode 31 and the second electrode 32 on the first semiconductor layer 21 and the second semiconductor layer 23 respectively.

[0125] The forming of the electrodes may include: processing the two electrodes by negative resist stripping. The electrodes are deposited with chromium as the base material, and the thickness of the chromium is controlled within 100 angstroms to prevent the brightness from being affected.

[0126] Step three: forming a passivation layer 40 on the epitaxial wafer. The passivation layer 40 is located at least on the surface of the second semiconductor layer 23 , the first electrode 31 , the second electrode 32 , the surface of the first semiconductor layer 21 and the groove 24 .

[0127] The passivation layer 40 may be a distributed Bragg reflector layer, which may be a DBR layer. The DBR layer includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0128] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0129] In the fourth step, a first via hole 41 and a second via hole 42 are formed on the passivation layer 40 . The first via hole 41 extends to the first electrode 31 , and the second via hole 42 extends to the second electrode 32 .

[0130] In the fifth step, a first soldering block 51 and a second soldering block 52 are made on the surface of the passivation layer 40 . The first soldering block 51 is connected to the first electrode 31 through the first via 41 , and the second soldering block 52 is connected to the second electrode 32 through the second via 42 .

[0131] In the embodiment of the present disclosure, the first soldering block 51 and the second soldering block 52 may include a first Ti layer, a first Al layer, a second Ti layer, a second Al layer, a third Ti layer and an Au layer stacked in sequence.

[0132] Illustratively, the thickness of the first Ti layer may be 100 angstroms to 500 angstroms. For example, the thickness of the first Ti layer may be 200 angstroms.

[0133] Illustratively, the thickness of the first Al layer may be 8000 angstroms to 12000 angstroms. For example, the thickness of the first Al layer may be 10000 angstroms.

[0134] Illustratively, the thickness of the second Ti layer may be 100 angstroms to 500 angstroms. For example, the thickness of the second Ti layer may be 200 angstroms.

[0135] Illustratively, the thickness of the second Al layer may be 8000 angstroms to 12000 angstroms. For example, the thickness of the second Al layer may be 10000 angstroms.

[0136] Illustratively, the thickness of the third Ti layer may be 800 angstroms to 1200 angstroms. For example, the thickness of the third Ti layer may be 1000 angstroms.

[0137] Illustratively, the thickness of the Au layer may be 2000 angstroms to 5000 angstroms, for example, the thickness of the Au layer may be 3000 angstroms.

[0138] Finally, the sapphire can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light-emitting diode chip is obtained by testing.

[0139] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light-emitting diode comprises: a substrate (10), an epitaxial layer (20), a first electrode (31) and a second electrode (32); the orthographic projection of the epitaxial layer (20) on the substrate (10) is a rectangle; a surface of the epitaxial layer (20) has a groove (24); the groove (24) is located at a side of the rectangle and extends from one end of the side to the other end; the first electrode (31) is located in the groove (24); the second electrode (32) is located outside the groove (24); and the angle between the side wall of the groove (24) and the bottom surface of the groove (24) is an obtuse angle; The epitaxial layer (20) comprises an n-type layer, a multi-quantum well layer (22), and a p-type layer stacked in sequence, the groove (24) being located on the surface of the p-type layer and exposing the n-type layer; a first local region (230) of the p-type layer is implanted with silicon ions, and the first local region (230) is adjacent to the groove (24); the first local region (230) comprises a first frame-shaped portion (231) and a second frame-shaped portion (232); the first frame-shaped portion (231) extends along an edge of the p-type layer, the second frame-shaped portion (232) is located within the first frame-shaped portion (231), and the amount of silicon ions implanted per unit volume in the first frame-shaped portion (231) is greater than the amount of silicon ions implanted per unit volume in the second frame-shaped portion (232); Silicon ions are injected into the second local area (240) of the p-type layer. The second local area (240) is arc-shaped and is located within the second frame-shaped portion (232). The amount of silicon ions injected per unit volume in the second local area (240) is higher than the amount of silicon ions injected per unit volume in the second frame-shaped portion (232), and is lower than the amount of silicon ions injected per unit volume in the first frame-shaped portion (231).

2. The light emitting diode according to claim 1, characterized in that The ratio of the groove width of the groove (24) to the length of the side adjacent to the side of the rectangle where the groove (24) is located is not greater than 1 / 5.

3. The light emitting diode according to claim 1, characterized in that The obtuse angle is no greater than 120°.

4. The light emitting diode according to claim 1, characterized in that In the thickness direction of the p-type layer, the first local region (230) and the second local region (240) are both located in the middle of the p-type layer.

5. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: providing a substrate; An epitaxial layer is formed on the substrate, wherein the orthographic projection of the epitaxial layer on the substrate is a rectangle, and a surface of the epitaxial layer has a groove, the groove being located at one side of the rectangle and extending from one end of the side to the other end. The epitaxial layer includes an n-type layer, a multi-quantum well layer, and a p-type layer stacked in sequence, and the groove is located on the surface of the p-type layer and exposes the n-type layer. Silicon ions are implanted in a first local region of the p-type layer, and the first local region is adjacent to the groove. The first local region includes a first frame-shaped portion and a second frame-shaped portion. The first frame-shaped portion extends along an edge of the p-type layer, and the second frame-shaped portion is located within the first frame-shaped portion. The amount of silicon ions implanted per unit volume in the first frame-shaped portion is greater than the amount of silicon ions implanted per unit volume in the second frame-shaped portion. Silicon ions are implanted in a second local region of the p-type layer, the second local region is arc-shaped and located within the second frame-shaped portion. The amount of silicon ions implanted per unit volume in the second local region is greater than the amount of silicon ions implanted per unit volume in the second frame-shaped portion, and less than the amount of silicon ions implanted per unit volume in the first frame-shaped portion. A first electrode and a second electrode are fabricated on the epitaxial layer, wherein the first electrode is located in the groove, and the second electrode is located outside the groove, and an angle between a sidewall of the groove and a bottom surface of the groove is an obtuse angle.

6. The preparation method according to claim 5, characterized in that The epitaxial layer includes an n-type layer, a multi-quantum well layer, and a p-type layer stacked in sequence, the groove is located on the surface of the p-type layer and exposes the n-type layer; silicon ions are implanted in a first local area of ​​the p-type layer, and the first local area is adjacent to the groove. When growing the p-type layer, the preparation method includes: growing a first p-type material layer; forming a photoresist layer on a surface of the first p-type material layer, the photoresist layer having an injection groove exposing the first p-type material layer, wherein an orthographic projection of the injection groove on the substrate coincides with an orthographic projection of the first local area on the substrate; implanting silicon ions into the first p-type material layer through the implantation groove; The photoresist layer is removed, and a second p-type material layer is grown to obtain the p-type layer.

Images