An intelligent digital synchronous inspection relay and its implementation method

Abstract

The present invention provides an intelligent digital synchronization check relay, comprising a voltage processing unit, a control management unit, and an instruction execution unit. The voltage processing unit simultaneously preprocesses the AC voltage signals on the system side and the side to be combined in phase for collection by the control management unit. The control management unit collects the amplitude, frequency, and phase of the preprocessed voltage signals on the system side and the side to be combined, and based on the collected amplitude, frequency, and phase, calculates the amplitude difference, frequency difference, and phase difference between the system side and the side to be combined. Furthermore, based on the calculation results, combined with an externally input manual instruction and its validity and multiple preset fixed values, a locking instruction or a synchronization judgment instruction is generated. The instruction execution unit blocks the synchronization judgment according to the locking instruction, or directly executes the synchronization judgment according to the synchronization judgment instruction. The implementation of the present invention overcomes the problems of complex wiring, time-consuming and labor-intensive, and high cost associated with traditional static synchronization check relays.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage synchronization inspection, and in particular to an intelligent digital synchronization inspection relay. Background Art

[0002] The synchronization check relay is used to detect the relationship between the voltage vectors on the system side and the side to be paralleled. Specifically, it takes a phase voltage from each side (as long as they are the same phase), connects the tails of the two voltage vectors, and connects a voltage relay at the head of the two vectors to reflect the difference between the two vectors. At this time, if the amplitudes of the two voltages are unequal, the relay will operate, opening the closing circuit; if the phases of the two voltages are different, the relay will operate, opening the closing circuit; or if the frequencies of the two voltages are unequal (the amplitudes are equal), the relay will only release at the moment the vectors return, and operate at other times. Therefore, only when the amplitude, frequency, and phase of the voltages on both sides meet the requirements and the voltage vectors on both sides are almost back, the relay will remain released and connect the closing circuit. As long as the circuit is closed manually or automatically, a closing pulse will be issued, completing the synchronous paralleling.

[0003] Currently, synchronization check relays include electromagnetic synchronization check relays and static synchronization check relays. Electromagnetic synchronization check relays are increasingly less used in field applications due to their long operating time. While static synchronization check relays are increasingly used, they generally only detect voltage amplitude and phase difference. Detecting voltage frequency requires an additional frequency check relay, which is not only complex and time-consuming, but also increases costs. Summary of the Invention

[0004] The technical problem to be solved by the embodiments of the present invention is to provide an intelligent digital synchronization check relay, which overcomes the problems of complex wiring, time-consuming and labor-intensive, and high cost brought about by traditional static synchronization check relays.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an intelligent digital synchronous check relay, comprising a voltage processing unit, a control management unit and an instruction execution unit; wherein,

[0006] The voltage processing unit is used to simultaneously pre-process the AC voltage signals on the system side and the side to be combined in the same phase for collection by the control management unit;

[0007] The control management unit is used to collect the amplitude, frequency and phase of the voltage signals of the system side and the side to be connected after simultaneous preprocessing, and based on the collected amplitude, frequency and phase, calculate the amplitude difference, frequency difference and phase difference between the system side and the side to be connected, and further generate a locking instruction or a synchronization judgment instruction based on the calculation result, combined with the external input manual instruction and its validity and a plurality of preset fixed values;

[0008] The instruction execution unit is used to lock the synchronization judgment according to the locking instruction; or directly execute the synchronization judgment according to the synchronization judgment instruction.

[0009] The voltage processing unit includes a transformer circuit, a filter circuit, a full-wave rectifier circuit, a proportional operational amplifier circuit and a square wave generating circuit;

[0010] The transformer circuit is connected to the input end of the filter circuit and is used to convert the AC voltage signals on the system side and the side to be combined into low-level AC voltage signals at a certain ratio;

[0011] One output end of the filter circuit is connected to the input end of the full-wave rectifier circuit, and the other output end is connected to the input end of the square wave generating circuit, for filtering both low-level AC voltage signals obtained by the transformation;

[0012] The output end of the full-wave rectifier circuit is connected to the input end of the proportional operational amplifier circuit, and is used to convert the two filtered low-level AC voltage signals into two corresponding DC voltage signals;

[0013] The output end of the proportional operational amplifier circuit is connected to an input end of the control management unit, and is used to amplify the two DC voltage signals according to a predetermined ratio so that the control management unit can collect the corresponding amplitudes;

[0014] The output end of the square wave generating circuit is connected to the other input end of the control management unit, and is used to convert the two filtered low-level AC voltage signals into corresponding two square wave voltage signals for the control management unit to collect the corresponding frequency and phase.

[0015] Among them, the transformer circuit adopts an EI silicon steel sheet core transformer with a transformation ratio of 100:2; the filter circuit includes a low-pass filter circuit and a band-pass filter circuit; and the full-wave rectifier circuit includes a diode and an operational amplifier.

[0016] Wherein, the control management unit includes a manual instruction input module and a CPU controller; wherein,

[0017] The manual instruction input module is used to receive manual instructions input externally by the user;

[0018] The CPU controller includes an acquisition module, a first comparison instruction generation module, a second comparison instruction generation module, a third comparison instruction generation module, a fourth comparison instruction generation module, a fifth comparison instruction generation module and an instruction output module; wherein,

[0019] The acquisition module has an input end connected to the voltage processing unit, and an output end connected to an input end of the first comparison instruction generation module, an input end of the second comparison instruction generation module, an input end of the third comparison instruction generation module, an input end of the fourth comparison instruction generation module, and an input end of the fifth comparison instruction generation module, and is used to acquire the amplitude, frequency, and phase of the voltage signals of the system side and the side to be merged after simultaneous preprocessing;

[0020] The other input terminal of the first comparison instruction generation module is connected to the output terminal of the manual instruction input module, and the output terminal is connected to the input terminal of the instruction output module, and is used to determine that a busbar low voltage fault has occurred and generate the locking instruction if the amplitude of the collected system-side voltage signal or the amplitude of the to-be-parallel-side voltage signal is less than a preset low voltage set value by comparison;

[0021] The other input end of the second comparison instruction generation module is connected to the output end of the manual instruction input module, and the output end is connected to the input end of the instruction output module, and is used to subtract the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the to-be-parallel side to obtain an amplitude difference, and when the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, an amplitude difference over-limit fault is determined and the blocking instruction is generated;

[0022] The other input end of the third comparison instruction generation module is connected to the output end of the manual instruction input module, and the output end is connected to the input end of the instruction output module, and is used to subtract the frequency of the collected system-side voltage signal from the frequency of the voltage signal on the to-be-parallel side to obtain a frequency difference, and when the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, a frequency difference over-limit fault is determined, and the blocking instruction is generated;

[0023] The fourth comparison instruction generation module has another input terminal connected to the output terminal of the manual instruction input module, and an output terminal connected to the input terminal of the instruction output module, and is configured to subtract the phase of the collected system-side voltage signal from the phase of the voltage signal on the side to be paralleled to obtain a phase difference, and when the absolute value of the obtained phase difference is greater than a preset phase difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, a phase difference over-limit fault is determined, and the blocking instruction is generated;

[0024] The fifth comparison instruction generation module has another input terminal connected to the output terminal of the manual instruction input module, and an output terminal connected to the input terminal of the instruction output module, for generating the synchronization judgment instruction when the amplitudes of the collected system-side voltage signal and the amplitudes of the to-be-parallel-side voltage signal are both greater than the preset low-voltage set value, and when it is determined that the externally input manual instruction is valid and is a locking instruction;

[0025] The input end of the instruction output module is connected to the instruction execution unit and is used to output the locking instruction and the synchronization judgment instruction.

[0026] Wherein, the control management unit also includes a display module; wherein,

[0027] The display module is connected to the output ends of all modules in the CPU controller.

[0028] Among them, the manual instruction input module is a button; the CPU controller is a single chip microcomputer; and the display module is an LED liquid crystal display screen.

[0029] The instruction execution unit includes output optocoupler isolation, transistor driver and relay elements.

[0030] An embodiment of the present invention further provides a method for implementing an intelligent digital synchronization check relay, which is implemented on the aforementioned intelligent digital synchronization check relay. The method includes the following steps:

[0031] The intelligent digital synchronization check relay simultaneously pre-processes the AC voltage signals on the same phase on the system side and the side to be connected;

[0032] The intelligent digital synchronization check relay collects the amplitude, frequency and phase of the voltage signals of the system side and the side to be connected after simultaneous preprocessing, and calculates the amplitude difference, frequency difference and phase difference between the system side and the side to be connected based on the collected amplitude, frequency and phase, and further generates a locking instruction or a synchronization judgment instruction based on the calculation result, combined with the external input manual instruction and its validity and a plurality of preset fixed values;

[0033] The intelligent digital synchronization check relay blocks the synchronization judgment according to the blocking instruction; or directly executes the synchronization judgment according to the synchronization judgment instruction.

[0034] Wherein, the method further comprises:

[0035] If the intelligent digital synchronization check relay compares the amplitude of the collected system side voltage signal or the amplitude of the voltage signal on the side to be connected and finds that it is less than the preset low voltage set value, it determines that a busbar low voltage fault has occurred and generates the locking instruction;

[0036] The intelligent digital synchronization check relay subtracts the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the side to be paralleled to obtain an amplitude difference, and when the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and when it is determined that the externally input manual command is valid and is a non-locking command, an amplitude difference over-limit fault is determined and the locking command is generated;

[0037] The intelligent digital synchronization check relay subtracts the frequency of the collected system side voltage signal from the frequency of the voltage signal on the side to be paralleled to obtain a frequency difference, and when the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a frequency difference over-limit fault is determined and the locking instruction is generated;

[0038] The intelligent digital synchronization check relay subtracts the phase of the collected system side voltage signal from the phase of the to-be-parallel side voltage signal to obtain a phase difference, and when the absolute value of the obtained phase difference is greater than a preset phase difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a phase difference over-limit fault is determined and the locking instruction is generated; and

[0039] When the intelligent digital synchronization check relay compares the amplitudes of the collected system side voltage signal and the amplitudes of the voltage signal on the side to be connected and finds that both are greater than the preset low voltage set value, if it is determined that the external input manual instruction is valid and is a locking instruction, the synchronization judgment instruction is generated.

[0040] The implementation of the embodiments of the present invention has the following beneficial effects:

[0041] The present invention adopts digital operation algorithm and synchronous logic control program to realize synchronous acquisition, detection and rapid control of the amplitude, frequency and phase of the voltage signal on the system side and the side to be connected in the same phase, so as to achieve the intelligent digital function of the synchronous inspection relay, thereby overcoming the problems of complex wiring, time-consuming and labor-intensive, and high cost brought by the traditional static synchronous inspection relay, and at the same time realizes synchronous logic judgment, low voltage protection locking logic and power characteristic parameter display. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying any creative work, other drawings obtained based on these drawings still fall within the scope of the present invention.

[0043] Figure 1A schematic diagram of the system structure of an intelligent digital synchronous inspection relay provided by an embodiment of the present invention;

[0044] Figure 2 for Figure 1 Schematic diagram of the structure of the medium voltage processing unit;

[0045] Figure 3 for Figure 1 Schematic diagram of the structure of the control management unit;

[0046] Figure 4 for Figure 3 Synchronous judgment logic diagram of the control management unit;

[0047] Figure 5 The present invention provides a flowchart of a method for implementing an intelligent digital synchronous check relay. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be described in further detail below with reference to the accompanying drawings.

[0049] like Figure 1 As shown in the figure, an intelligent digital synchronous check relay proposed in an embodiment of the present invention includes a voltage processing unit 1, a control management unit 2 and an instruction execution unit 3; wherein,

[0050] The voltage processing unit 1 is used to pre-process the AC voltage signals on the system side and the side to be connected simultaneously for collection by the control management unit 2;

[0051] The control management unit 2 is used to collect the amplitude, frequency, and phase of the voltage signals on the system side and the side to be connected after simultaneous preprocessing, and based on the collected amplitude, frequency, and phase, calculate the amplitude difference, frequency difference, and phase difference between the system side and the side to be connected, and further generate a blocking instruction or a synchronization judgment instruction based on the calculation results, combined with the external input manual instruction and its validity and multiple preset fixed values;

[0052] The instruction execution unit 3 is used to lock the synchronization judgment according to the locking instruction; or directly execute the synchronization judgment according to the synchronization judgment instruction.

[0053] It should be noted that the predetermined multiple constants include a low voltage constant, an amplitude difference constant, a frequency difference constant, a phase difference constant, etc., and can be adjusted according to actual needs.

[0054] In the embodiment of the present invention, Figure 2 As shown, the voltage processing unit 1 includes a transformer circuit 11, a filter circuit 12, a full-wave rectifier circuit 13, a proportional operational amplifier circuit 14 and a square wave generating circuit 15; wherein,

[0055] The transformer circuit 11 is connected to the input end of the filter circuit 12 and is used to convert the AC voltage signals on the system side and the side to be paralleled into low-level AC voltage signals at a certain ratio. In one example, the transformer circuit 11 uses an EI silicon steel sheet core transformer with a transformation ratio of 100:2.

[0056] One output end of the filter circuit 12 is connected to the input end of the full-wave rectifier circuit 13, and the other output end is connected to the input end of the square wave generator circuit 15, for filtering both low-level AC voltage signals obtained by the transformation. In one example, the filter circuit 12 includes a low-pass filter circuit and a band-pass filter circuit. The band-stop filter circuit is composed of a symmetrical T-type resistor-capacitor circuit and an operational amplifier, and is used to prevent the third harmonic from passing through. The low-pass filter circuit is a circuit for filtering the power frequency, and its filter ratio is constantly greater than 50.

[0057] The output end of the full-wave rectifier circuit 13 is connected to the input end of the proportional operational amplifier circuit 14, and is used to convert the two low-level filtered AC voltage signals into two corresponding DC voltage signals. In one example, the full-wave rectifier circuit 13 includes a diode and an operational amplifier, which is used to extract the amplitude of the AC voltage signal.

[0058] The output terminal of the proportional operational amplifier circuit 14 is connected to an input terminal of the control management unit 2, and is used to amplify the two DC voltage signals according to a predetermined ratio so that the control management unit 2 can collect the corresponding amplitude. It should be noted that the proportional operational amplifier circuit 14 is used to flexibly fine-tune the value input to the control management unit 2 to fully meet the requirements of ratio and accuracy.

[0059] The output end of the square wave generating circuit 15 is connected to the other input end of the control management unit 2 , and is used to convert the two filtered low-level AC voltage signals into two corresponding square wave voltage signals for the control management unit 2 to collect the corresponding frequency and phase.

[0060] In the embodiment of the present invention, Figure 3 As shown, the control management unit 2 includes a manual instruction input module 21, a CPU controller 22 and a display module 23; wherein,

[0061] A manual instruction input module 21 is used to receive a manual instruction inputted externally by a user; in one example, the manual instruction input module 21 is a button;

[0062] The CPU controller 22 adopts a single chip microcomputer, which includes an acquisition module 221, a first comparison instruction generation module 222, a second comparison instruction generation module 223, a third comparison instruction generation module 224, a fourth comparison instruction generation module 225, a fifth comparison instruction generation module 226 and an instruction output module 227; wherein,

[0063] The input end of the acquisition module 221 is connected to the voltage processing unit 1, and the output end is connected to an input end of the first comparison instruction generation module 222, an input end of the second comparison instruction generation module 223, an input end of the third comparison instruction generation module 224, an input end of the fourth comparison instruction generation module 225, and an input end of the fifth comparison instruction generation module 226. It is used to collect (e.g., by a timer) the amplitude, frequency, and phase of the voltage signals of the system side and the side to be merged after preprocessing;

[0064] The other input end of the first comparison instruction generation module 222 is connected to the output end of the manual instruction input module 21, and the output end is connected to the input end of the instruction output module 227. If the amplitude of the collected system-side voltage signal or the amplitude of the voltage signal on the side to be connected is less than the preset low-voltage set value, it is determined that the busbar is under-voltage fault and a blocking instruction is generated.

[0065] The other input end of the second comparison instruction generation module 223 is connected to the output end of the manual instruction input module 21, and the output end is connected to the input end of the instruction output module 227. The module is used to subtract the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the side to be connected to obtain an amplitude difference. If the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and if it is determined that the externally input manual instruction is valid and is not a blocking instruction, an amplitude difference over-limit fault is determined and a blocking instruction is generated.

[0066] The other input end of the third comparison instruction generation module 224 is connected to the output end of the manual instruction input module 21, and the output end is connected to the input end of the instruction output module 227. The module is used to subtract the frequency of the collected system-side voltage signal from the frequency of the voltage signal on the side to be paralleled to obtain a frequency difference. When the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, a frequency difference over-limit fault is determined and a blocking instruction is generated.

[0067] The other input end of the fourth comparison instruction generation module 225 is connected to the output end of the manual instruction input module 21, and the output end is connected to the input end of the instruction output module 227. The fourth comparison instruction generation module 225 is used to subtract the phase of the collected system-side voltage signal from the phase of the voltage signal on the side to be connected to obtain a phase difference. After comparing the obtained phase difference, if the absolute value is greater than a preset phase difference value, and if it is determined that the externally input manual instruction is valid and is not a blocking instruction, a phase difference over-limit fault is determined and a blocking instruction is generated.

[0068] The fifth comparison instruction generation module 226 has another input terminal connected to the output terminal of the manual instruction input module 21, and an output terminal connected to the input terminal of the instruction output module 227. The fifth comparison instruction generation module 226 is configured to generate a synchronization determination instruction when, upon comparison, the amplitudes of the collected system-side voltage signal and the amplitudes of the to-be-parallel-side voltage signal are both greater than a preset low-voltage set value, and if it is determined that the externally input manual instruction is valid and is a blocking instruction;

[0069] The input end of the instruction output module 227 is connected to the instruction execution unit 3 and is used to output the locking instruction and the synchronization judgment instruction;

[0070] The display module 23 is connected to the output terminals of all the above modules in the CPU controller; in one example, the display module is an LED liquid crystal display screen.

[0071] like Figure 4 The figure shows the judgment logic diagram of the control management unit. Figure 4 middle, Represented as the AND logical operator, Represented as the OR logical operator; Represents the negation operator.

[0072] When the CPU controller 22 detects that the amplitude of the voltage signal on the system side or the side to be connected is lower than the low voltage set value, it will be judged as a bus low voltage fault and the synchronization judgment will be locked at the same time; when the CPU controller 22 detects that the external manual non-locking is valid and the frequency difference is greater than the frequency difference set value, it will be judged as a frequency difference over-limit fault and the synchronization judgment will be locked at the same time, and the screen will display the frequency difference over-limit fault in real time; similarly, when the CPU controller 22 detects that the external manual non-locking is valid and the phase difference is greater than the phase difference set value, it will be judged as a phase difference over-limit fault and the synchronization judgment will be locked at the same time; when the CPU controller 22 detects that the external manual non-locking is valid and the amplitude difference is greater than the amplitude difference set value, it will be judged as an amplitude difference over-limit fault and the synchronization judgment will be locked at the same time; when the CPU controller 22 detects that the external manual locking is valid, it will directly perform the synchronization judgment.

[0073] In an embodiment of the present invention, the instruction execution unit 3 includes an output optocoupler isolation, a transistor driver and a relay element. After executing the received locking instruction or synchronization judgment instruction, it controls the power supply and power loss of the output relay coil and controls the opening and closing of the output relay contacts.

[0074] It is understandable that the intelligent digital synchronization check relay also includes a power supply unit, which mainly converts the power supply into 12V and 3.3V power supplies to realize power supply to all units and modules of the internal device.

[0075] like Figure 5As shown in FIG, an embodiment of the present invention provides a method for implementing an intelligent digital synchronization check relay, which is implemented on an intelligent digital synchronization check relay in an embodiment of the present invention. The method includes the following steps:

[0076] Step S1, the intelligent digital synchronization check relay simultaneously pre-processes the AC voltage signals on the same phase on the system side and the side to be paralleled;

[0077] Step S2, the intelligent digital synchronization check relay collects the amplitude, frequency and phase of the voltage signals of the system side and the side to be combined after simultaneous preprocessing, and calculates the amplitude difference, frequency difference and phase difference between the system side and the side to be combined based on the collected amplitude, frequency and phase, and further generates a locking instruction or a synchronization judgment instruction based on the calculation result, combined with the external input manual instruction and its validity and a plurality of preset fixed values;

[0078] Step S3: The intelligent digital synchronization check relay blocks the synchronization judgment according to the blocking instruction; or directly executes the synchronization judgment according to the synchronization judgment instruction.

[0079] Wherein, the method further comprises:

[0080] If the intelligent digital synchronization check relay compares the amplitude of the collected system side voltage signal or the amplitude of the voltage signal on the side to be connected and finds that it is less than the preset low voltage set value, it determines that a busbar low voltage fault has occurred and generates the locking instruction;

[0081] The intelligent digital synchronization check relay subtracts the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the side to be paralleled to obtain an amplitude difference, and when the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and when it is determined that the externally input manual command is valid and is a non-locking command, an amplitude difference over-limit fault is determined and the locking command is generated;

[0082] The intelligent digital synchronization check relay subtracts the frequency of the collected system side voltage signal from the frequency of the voltage signal on the side to be paralleled to obtain a frequency difference, and when the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a frequency difference over-limit fault is determined and the locking instruction is generated;

[0083] The intelligent digital synchronization check relay subtracts the phase of the collected system side voltage signal from the phase of the to-be-parallel side voltage signal to obtain a phase difference, and when the absolute value of the obtained phase difference is greater than a preset phase difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a phase difference over-limit fault is determined and the locking instruction is generated; and

[0084] When the intelligent digital synchronization check relay compares the amplitudes of the collected system side voltage signal and the amplitudes of the voltage signal on the side to be connected and finds that both are greater than the preset low voltage set value, if it is determined that the external input manual instruction is valid and is a locking instruction, the synchronization judgment instruction is generated.

[0085] The implementation of the embodiments of the present invention has the following beneficial effects:

[0086] The present invention adopts digital operation algorithm and synchronous logic control program to realize synchronous acquisition, detection and rapid control of the amplitude, frequency and phase of the voltage signal on the system side and the side to be connected in the same phase, so as to achieve the intelligent digital function of the synchronous inspection relay, thereby overcoming the problems of complex wiring, time-consuming and labor-intensive, and high cost brought by the traditional static synchronous inspection relay, and at the same time realizes synchronous logic judgment, low voltage protection locking logic and power characteristic parameter display.

[0087] It is worth noting that in the above-mentioned device embodiment, the various units included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0088] The above disclosure is merely a preferred embodiment of the present invention and certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An intelligent digital synchronous check relay, characterized in that: It includes a voltage processing unit, a control management unit and an instruction execution unit; wherein, The voltage processing unit is used to simultaneously pre-process the AC voltage signals on the system side and the side to be connected in phase, so as to provide the control management unit with data for collection; The control management unit is used to collect the amplitude, frequency and phase of the voltage signals of the system side and the side to be connected after simultaneous preprocessing, and based on the collected amplitude, frequency and phase, calculate the amplitude difference, frequency difference and phase difference between the system side and the side to be connected, and further generate a locking instruction or a synchronization judgment instruction based on the calculation result, combined with the external input manual instruction and its validity and a plurality of preset fixed values; The instruction execution unit is used to lock the synchronization judgment according to the locking instruction; or directly execute the synchronization judgment according to the synchronization judgment instruction; Wherein, the control management unit includes a manual instruction input module and a CPU controller; wherein, The manual instruction input module is used to receive manual instructions input externally by the user; The CPU controller includes an acquisition module, a first comparison instruction generation module, a second comparison instruction generation module, a third comparison instruction generation module, a fourth comparison instruction generation module, a fifth comparison instruction generation module and an instruction output module; wherein, The acquisition module has an input end connected to the voltage processing unit, and an output end connected to an input end of the first comparison instruction generation module, an input end of the second comparison instruction generation module, an input end of the third comparison instruction generation module, an input end of the fourth comparison instruction generation module, and an input end of the fifth comparison instruction generation module, and is used to acquire the amplitude, frequency, and phase of the voltage signals of the system side and the side to be merged after simultaneous preprocessing; The other input terminal of the first comparison instruction generation module is connected to the output terminal of the manual instruction input module, and the output terminal is connected to the input terminal of the instruction output module, and is used to determine that a busbar low voltage fault has occurred and generate the locking instruction if the amplitude of the collected system-side voltage signal or the amplitude of the to-be-parallel-side voltage signal is less than a preset low voltage set value by comparison; The other input end of the second comparison instruction generation module is connected to the output end of the manual instruction input module, and the output end is connected to the input end of the instruction output module, and is used to subtract the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the to-be-parallel side to obtain an amplitude difference, and when the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, an amplitude difference over-limit fault is determined and the blocking instruction is generated; The other input end of the third comparison instruction generation module is connected to the output end of the manual instruction input module, and the output end is connected to the input end of the instruction output module, and is used to subtract the frequency of the collected system-side voltage signal from the frequency of the voltage signal on the to-be-parallel side to obtain a frequency difference, and when the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, a frequency difference over-limit fault is determined, and the blocking instruction is generated; The fourth comparison instruction generation module has another input terminal connected to the output terminal of the manual instruction input module, and an output terminal connected to the input terminal of the instruction output module, and is configured to subtract the phase of the collected system-side voltage signal from the phase of the voltage signal on the side to be paralleled to obtain a phase difference, and when the absolute value of the obtained phase difference is greater than a preset phase difference value after comparison, and when it is determined that the externally input manual instruction is valid and is not a blocking instruction, a phase difference over-limit fault is determined, and the blocking instruction is generated; The fifth comparison instruction generation module has another input terminal connected to the output terminal of the manual instruction input module, and an output terminal connected to the input terminal of the instruction output module, for generating the synchronization judgment instruction when the amplitudes of the collected system-side voltage signal and the amplitudes of the to-be-parallel-side voltage signal are both greater than the preset low-voltage set value, and when it is determined that the externally input manual instruction is valid and is a locking instruction; The input end of the instruction output module is connected to the instruction execution unit and is used to output the locking instruction and the synchronization judgment instruction.

2. The intelligent digital synchronization check relay according to claim 1, characterized in that: The voltage processing unit includes a transformer circuit, a filter circuit, a full-wave rectifier circuit, a proportional operational amplifier circuit and a square wave generating circuit; wherein, The transformer circuit is connected to the input end of the filter circuit and is used to convert the AC voltage signals on the system side and the side to be combined into low-level AC voltage signals at a certain ratio; One output end of the filter circuit is connected to the input end of the full-wave rectifier circuit, and the other output end is connected to the input end of the square wave generating circuit, for filtering both low-level AC voltage signals obtained by the transformation; The output end of the full-wave rectifier circuit is connected to the input end of the proportional operational amplifier circuit, and is used to convert the two filtered low-level AC voltage signals into two corresponding DC voltage signals; The output end of the proportional operational amplifier circuit is connected to an input end of the control management unit, and is used to amplify the two DC voltage signals according to a predetermined ratio so that the control management unit can collect the corresponding amplitudes; The output end of the square wave generating circuit is connected to the other input end of the control management unit, and is used to convert the two filtered low-level AC voltage signals into corresponding two square wave voltage signals for the control management unit to collect the corresponding frequency and phase.

3. The intelligent digital synchronization check relay according to claim 2, characterized in that: The transformer circuit adopts an EI silicon steel sheet core transformer with a transformation ratio of 100:2; the filter circuit includes a low-pass filter circuit and a band-pass filter circuit; and the full-wave rectifier circuit includes a diode and an operational amplifier.

4. The intelligent digital synchronization check relay according to claim 1, characterized in that: The control management unit also includes a display module; wherein, The display module is connected to the output ends of all modules in the CPU controller.

5. The intelligent digital synchronization check relay according to claim 4, characterized in that: The manual instruction input module is a button; the CPU controller is a single chip microcomputer; and the display module is an LED liquid crystal display screen.

6. The intelligent digital synchronization check relay according to claim 1, characterized in that: The instruction execution unit includes output optocoupler isolation, transistor drive and relay elements.

7. A method for implementing an intelligent digital synchronous check relay, characterized in that: The method is implemented on the intelligent digital synchronization check relay according to claim 1, and the method comprises the following steps: The intelligent digital synchronization check relay simultaneously pre-processes the AC voltage signals on the same phase on the system side and the side to be connected; The intelligent digital synchronization check relay collects the amplitude, frequency and phase of the voltage signals of the system side and the side to be connected after simultaneous preprocessing, and calculates the amplitude difference, frequency difference and phase difference between the system side and the side to be connected based on the collected amplitude, frequency and phase, and further generates a locking instruction or a synchronization judgment instruction based on the calculation result, combined with the external input manual instruction and its validity and a plurality of preset fixed values; The intelligent digital synchronization check relay blocks the synchronization judgment according to the blocking instruction; or directly executes the synchronization judgment according to the synchronization judgment instruction.

8. The method for implementing the intelligent digital synchronization check relay according to claim 7, wherein: The method further comprises: If the intelligent digital synchronization check relay compares the amplitude of the collected system side voltage signal or the amplitude of the voltage signal on the side to be connected and finds that it is less than the preset low voltage set value, it determines that a busbar low voltage fault has occurred and generates the locking instruction; The intelligent digital synchronization check relay subtracts the amplitude of the collected system-side voltage signal from the amplitude of the voltage signal on the side to be paralleled to obtain an amplitude difference, and when the absolute value of the obtained amplitude difference is greater than a preset amplitude difference value after comparison, and when it is determined that the externally input manual command is valid and is a non-locking command, an amplitude difference over-limit fault is determined and the locking command is generated; The intelligent digital synchronization check relay subtracts the frequency of the collected system side voltage signal from the frequency of the voltage signal on the side to be paralleled to obtain a frequency difference, and when the absolute value of the obtained frequency difference is greater than a preset frequency difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a frequency difference over-limit fault is determined and the locking instruction is generated; The intelligent digital synchronization check relay subtracts the phase of the collected system side voltage signal from the phase of the to-be-parallel side voltage signal to obtain a phase difference, and when the absolute value of the obtained phase difference is greater than a preset phase difference value after comparison, and when it is determined that the externally input manual instruction is valid and is a non-locking instruction, a phase difference over-limit fault is determined and the locking instruction is generated; and When the intelligent digital synchronization check relay compares the amplitudes of the collected system side voltage signal and the amplitudes of the voltage signal on the side to be connected and finds that both are greater than the preset low voltage set value, if it is determined that the external input manual instruction is valid and is a locking instruction, the synchronization judgment instruction is generated.

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