Battery pack two-branch non-dissipative equalization system and its equalization method

Abstract

The present invention relates to a battery pack two-branch non-dissipative equalization system and its equalization method, which includes an equalization subunit and batteries B1 and B2 connected thereto, constituting an equalization control module; the equalization subunit is used to control the charging and discharging of batteries B1 and B2 according to the received control signal to achieve equalization control of the batteries. The present invention can shorten the equalization path and improve the equalization efficiency. Compared with the dissipative equalization circuit, the equalization efficiency is increased by 4.1 times; compared with the traditional inductor non-dissipative equalization, the equalization efficiency is increased by 1.49 times.

Description

Technical Field

[0001] The present invention belongs to the field of power battery management systems, and specifically relates to a battery pack two-part non-dissipative equalization system and its equalization method. Background Art

[0002] Equalization management means that during the use of a battery pack, the inconsistency state of the battery pack is judged in real time according to preset conditions. When the conditions are not met, the equalization module is activated, and the battery with higher energy charges the equalization module, and then the equalization module charges the battery with lower energy, so that the battery pack finally meets the set consistency conditions, thereby improving the capacity utilization rate of the battery pack.

[0003] Currently, common equalization circuits are classified according to their operating principles into energy dissipative and non-dissipative equalization circuits.

[0004] The resistor-type equalization circuit is an energy dissipative equalization circuit. During the charge and discharge process, the battery cell with higher energy discharges through the resistor R i to finally achieve equalization of the battery pack. The disadvantage of this circuit is that the equalization current is small and the equalization speed is slow; when the consistency of the battery pack is poor, more energy will be converted into heat loss, which is likely to damage the stability of the thermal balance state of the battery pack.

[0005] Energy non-dissipative equalization circuits mostly use energy storage elements to equalize battery cells, but can only equalize between adjacent two batteries, and the equalization path is long, which is most obvious when the target battery cell is at the head or tail of the battery pack. Summary of the Invention

[0006] In view of the deficiencies of energy dissipative and non-dissipative equalization circuits, the present invention provides an inductive energy non-dissipative equalization circuit. To shorten the equalization path and improve the equalization efficiency, based on the inductive equalization circuit, an equalization circuit with hierarchical and multi-criterion limitations is designed by adjusting the equalization path, equalization duty cycle, and equalization threshold, and is named a two-part non-dissipative equalization circuit.

[0007] The technical solution adopted by the present invention to achieve the above object is: a battery pack two-part non-dissipative equalization system, including an equalization sub-unit and battery B1 and battery B2 connected thereto, constituting an equalization control module; the equalization sub-unit is used to control the charge and discharge of battery B1 and battery B2 according to the received control signal to achieve equalization control of the battery;

[0008] Among them, the equalization sub-unit includes two series-connected MOS transistors S a and MOS transistor S b ;

[0009] The gate of the MOS transistor S b and the MOS transistor S aThe gate of is used to receive a control signal, MOS transistor S b The source of is connected to the positive electrode of battery B2, MOS transistor S b The drain of is connected to the drain of MOS transistor S a The drain of is connected, and is also connected to the negative electrode of battery B2 and the positive electrode of battery B1 through an inductor; MOS transistor S a The source of is connected to the negative electrode of battery B1;

[0010] The MOS transistor S b Between the source and the drain of, between the source and the drain of MOS transistor S a Parasitic diodes are respectively connected between the source and the drain.

[0011] For 2 m Series-connected batteries, the equalizer sub-unit is m layers, and the number of equalizer sub-units in the i-th layer is 2 m-i Individuals, i = 1…m;

[0012] For the j-th equalizer sub-unit in the i-th layer, the 2 i Individual batteries are divided into two battery groups with equal numbers. The battery group and the equalizer sub-unit of the i-1th layer connected thereto form an equalization control module. The equalization control module is regarded as a battery for the j-th equalizer sub-unit in the i-th layer to perform equalization control, j = 1…2 m-i .

[0013] For 2 m +1 series-connected battery numbers, the last battery is connected to the last equalizer sub-unit of the second layer, and is combined with the equalization control module where the last equalizer sub-unit of the first layer is located as the last equalization control module of the first layer for the last equalizer sub-unit of the second layer to perform equalization control.

[0014] The battery group two-part non-dissipative equalization system further includes a control circuit. The control circuit is used to output a control signal to control the on and off of MOS transistors a and b in the equalizer sub-unit.

[0015] The battery group two-part non-dissipative equalization control method includes the following steps:

[0016] Obtain the state of charge of each battery;

[0017] Judge the state of charge SOC of battery B1 connected to the equalizer sub-unit a , the state of charge SOC of battery B2 b , and perform equalization control on the battery by controlling the on and off of MOS transistor S a And MOS transistor S b :

[0018] SOC a -SOC b> Threshold MOS transistor S a Turn on;

[0019] SOC b -SOC a > Threshold MOS transistor S b Turn on.

[0020] When the number of batteries is odd, the last battery does not perform the balancing operation and directly performs the balancing operation through the last balancing subunit in the upper layer.

[0021] The threshold for the i-th layer of balancing subunits to perform balancing control is less than the threshold for the (i + 1)-th layer of balancing subunits to perform balancing control.

[0022] The switching frequency of the (i + 1)-th layer of balancing subunits is twice that of the i-th layer of balancing subunits.

[0023] The present invention has the following beneficial effects and advantages:

[0024] 1. The present invention can shorten the balancing path, improve the balancing efficiency, and reduce energy loss. Compared with the existing dissipative balancing circuit, the balancing efficiency of the binary balancing circuit is increased by 4.1 times, and the energy loss is only 1 / 25. Compared with the traditional inductive non-dissipative balancing, the balancing efficiency is increased by 1.49 times, and the energy loss is only 3 / 4.

[0025] 2. The present invention reduces the circuit complexity and the balancing control complexity.

[0026] 3. The circuit structure is clear and the scalability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The binary balancing circuit structure diagram of the present invention;

[0028] Figure 2 The schematic diagram of the battery voltage fluctuation during the balancing process of the present invention (a: B1 voltage; b: B2 voltage);

[0029] Figure 3 The schematic diagram of the inductive charging principle of the present invention;

[0030] Figure 4 The schematic diagram of the inductive discharging principle of the present invention;

[0031] Figure 5 The schematic diagram of the working current of the balancing subunit Si of the present invention (a: S1b current; b: S1a current);

[0032] Figure 6 The schematic diagram of the switching state of the balancing subunit of the present invention;

[0033] Figure 7 The SOC simulation curve of the battery pack;

[0034] Figure 8 Current waveform diagram of the balancing subunit S1;

[0035] Figure 9 Inductance voltage waveform diagram of the balancing subunit S1;

[0036] Figure 10 Balancing result diagram of the battery pack;

[0037] Figure 11 SOC curve diagram of the dissipative balancing;

[0038] Figure 12 SOC curve diagram of the traditional non-dissipative balancing. Specific implementation manner

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0040] The main idea of the balancing circuit based on the hierarchical strategy is hierarchical merging. A balancing sub-circuit is designed, and corresponding control frequencies, start thresholds and other conditions are set for each layer. During the use of the battery pack, the part with more power in the single battery or battery module is supplemented to the battery or battery pack with low power through the balancing sub-circuit, preventing overcharging and over-discharging of some battery monomers caused by the imbalance of the battery pack.

[0041] As Figure 1 shown, the balancing principle of the circuit is analyzed by connecting four 18650 lithium batteries in series.

[0042] The MCU analyzes and processes the battery module data, gives the PWM control signal to the balancing sub-circuit, and balances the power among the bottom-layer battery monomers and modules. The overall balancing strategy is hierarchical control. The general balancing idea is: in the first layer, the bottom-layer battery monomers of the battery pack are B i , and the balancing subunit S i is responsible for the balancing between two adjacent bottom-layer battery monomers B i . In the second layer, the balancing control module M i is regarded as a monomer, and the balancing subunit E i is used to perform the balancing control between M i .

[0043] The more the number of batteries, the more the number of layers, and so on. If the number of batteries is even, two adjacent battery modules are combined into a balancing unit. If the number of batteries is odd, the last battery module directly enters the second-level circuit.

[0044] Among them, the control circuit includes six branches. Each branch includes a MOS tube and a resistor. The gate of the MOS tube is connected to the MCU, the drain is connected to the resistor and the balancing subunit, and the source is grounded. One end of the resistor is connected to the drain of the MOS tube, and the other end is connected to the power supply.

[0045] Because the number of batteries connected in each layer of the binary equalization circuit is different, different battery equalization paths, PWM frequencies, start thresholds and other data are set according to the position of the equalization sub-units to control the equalization sub-circuits. During the charging and discharging process of the battery pack, the current of the battery modules with high power is reduced, and the current of the battery modules with low power is increased to prevent overcharging and over-discharging of the batteries. The charging equalization and the discharging equalization are the same in principle.

[0046] There is a large non-linearity in the charging and discharging process of lithium batteries. The change rate of the battery SOC does not match the change rate of the terminal voltage during this process. That is, the terminal voltage can only be used as the external characteristic of the battery and cannot accurately represent the change of the battery capacity. In addition, as Figure 2 shown, during the equalization process of the battery pack, the terminal voltage of the battery will fluctuate greatly, up to 100 mV. In order to avoid incorrect activation of the equalization control, the equalization threshold judgment condition in this paper selects SOC.

[0047] The equalization strategy limited by multiple criteria designed in this section is as follows:

[0048] (1) Select the equalization path: During the equalization process of the battery pack, the equalization of the single cells in the same module M i is carried out through the equalization sub-unit S i , and the equalization between the battery packs M i in the same module E i is carried out through the equalization sub-unit E i . The equalization of the entire battery pack can be realized through two layers of equalization sub-circuits.

[0049] (2) Select the equalization threshold: Each layer of the equalization circuit of the control modules such as S i and E i has an equalization threshold. When the number of batteries is large, the number of corresponding control module layers is also more. Similarly, the number of equalization thresholds will also be more. Currently, there are 4 batteries, corresponding to two layers of equalization control modules. Only when all the equalization threshold limitations are met at the same time, the battery equalization circuit will stop working and complete the equalization task.

[0050] It can be seen from Figure 1 that each S i equalization sub-unit controls two battery cells, denoted as a and b. The opening condition of the MOS tube S i in S a is:

[0051] SOC a -SOC b >0.3 (1)

[0052] The opening condition of the MOS tube S i in S b is:

[0053] SOC b -SOC a >0.3 (2)

[0054] When the number of batteries n is odd, the last battery does not perform the balancing operation and directly enters the second-layer circuit.

[0055] In the second-layer circuit, each E i balancing sub-circuit controls two M i modules, denoted as a and b. The enabling condition of E i is: a

[0056] SOC a -SOC b >0.5 (3)

[0057] The enabling condition of E i is: b

[0058] SOC b -SOC a >0.5 (4)

[0059] When the number k of the balancing control modules M i is odd, the last balancing control module does not perform the balancing operation, and the balancing control module M directly enters the third-layer circuit.

[0060]

[0061] (3) Adjustment of the switching frequency: The balancing pulse current of this balancing circuit is relatively large. In order to protect the battery and extend its service life, it is necessary to limit the magnitude of the balancing pulse current. In the first-layer balancing sub-unit, the inductor is connected to one battery, and in the second-layer balancing sub-unit, the inductor is connected to two batteries. Therefore, the switching frequency of E i is set to be twice that of S i .

[0061] Taking the first-layer balancing sub-unit as an example to analyze the working principle of the balancing circuit. During the charging and discharging process of the battery pack, assume that the SOC of the battery cell B 2 is higher than that of the battery B 1 , and the battery pack balancing process can be divided into two stages.

[0062] Stage 1: Charge the balancing sub-unit S 1 . As Figure 3 shown.

[0063] S 1b is a P-channel MOS transistor, S 1b is closed, i c gradually increases, and the monomer B 2Charge the inductor, and part of the electrical energy is stored in the inductor and converted into magnetic energy. The maximum value of the balancing current is I max It is determined by the closing time of S 1b .

[0064] The on-resistance of S 1b and the total resistance of the circuit such as the DC resistance of the inductor are represented by R on . The inductance value of the inductor is represented by L, and i L represents the current value passing through the inductor. The closing time of S 1b is represented by t on .

[0065] During this process, the inductor in the balancing subunit S 1 absorbs the current of the battery B 2 to charge and store energy, reducing the charge of the battery B 2 .

[0066] Phase 2: The balancing subunit S 1 discharges. As shown in Figure 4 .

[0067] S 1a is an N-channel MOS transistor. When t > t on , S 1b disconnects. The inductor charges the battery B 1a through the parasitic diode of S 1 , completing the transfer of energy from the battery B 2 to the battery B 1 . The inductor is a first-order full response in this process.

[0068] The inductor of the balancing subunit charges the battery B 1a by the way of freewheeling through the parasitic diode of the MOS transistor S 1 , increasing the charge of the battery B 1 .

[0069] Similarly, when the SOC of the battery cell B 1 is greater than the SOC of the battery cell B 2 and the startup condition of the balancing sub-circuit S 1 is satisfied, it is necessary to perform discharge balancing on the battery cell B 1 and charge balancing on the battery cell B 2 . The balancing process can also be completed through two similar stages. In the second-layer E i control circuit, the balancing process can also be divided into two similar stages, which will not be elaborated here.

[0070] To verify the effectiveness of the binary equalization circuit, simulations and experiments were conducted using the equalization circuit. Four 2600 mAH lithium batteries and a 33 uH inductor with a DC resistance of 0.6 Ω were selected. The equalization sub-unit S i has a PWM of 16.6 kHz determined, and the equalization sub-unit E i has a PWM of 33.3 kHz determined, with a certain margin left for the duty cycle, and 40% was selected.

[0071] In the initial stage, the SOC of battery cell B1 was set to 80%, and the SOCs of battery cells B2, B3, and B4 were set to 95% to test the equalization effect of the circuit.

[0072] It can be seen from the schematic diagram that when the Si equalization sub-unit is working, the voltage across the inductor is approximately equal to the battery cell voltage. Therefore, the test was conducted by observing the change in current. The magnitudes of the currents passing through S1a and S1b are as Figure 5 shown. First, S1b corresponding to Figure (a) conducts, and the current starts to increase from 0. When S1b turns off, the corresponding current reaches its maximum value, with a maximum current of 1.574 A, which is also the current value passing through the inductor. Then, the inductor discharges through the parasitic diode of S1a, as shown in Figure (b), charging battery cell B1. Before S1a conducts in the next cycle, the inductor current drops to 0. This prevents charge accumulation and wasted power. The waveforms of the Ei equalization sub-unit are similar and will not be elaborated here.

[0073] During the 2500 s of simulation, the control signals output by the Fun module are as Figure 6 shown. The discharge equalization time period of S1b for battery cell B2 is [0, 2196 s], and the continuous discharge equalization time period of E1b for battery pack M2 is [0, 521.8 s], with intermittent discharge in the period [521.8 s, 2196 s]. None of the other equalization sub-units are turned on during the entire process.

[0074] During the simulation process, the changes in the SOC of the battery pack are as Figure 7 shown. At the 2500 s mark, the SOCs of the four batteries are 64.201%, 64.331%, 64.626%, and 64.647% respectively.

[0075] The initial values of the SOC of the battery cells at each stage are shown in Table 1. The overall equalization control is basically completed. The equalization results are very satisfactory.

[0076] Table 1 Initial values of the battery SOC (%) at each stage of active equalization

[0077]

[0078] Based on the simulation circuit, an embedded hardware circuit was designed in this paper for experimental verification. The parameters are the same as those in the simulation, with an inductance value of 33 uH and switching frequencies of 16.67 kHz and 33.3 kHz respectively.

[0079] To facilitate debugging, a host computer was programmed using Qt software to display and store data.

[0080] The waveform of the S1 balancing sub-unit is as Figure 8 shown. CH1 is the PWM control signal with a frequency of 16.67 kHz. CH2 is the current waveform through the inductor. When PWM is at a high level, MOS transistor S1b conducts, and battery 2 charges the inductor. At this time, the inductor is the load, and the current increases approximately linearly. When PWM is at a low level, the inductor discharges through the parasitic diode of S1a. At this time, the inductor is the power source, and the current decreases approximately linearly to charge battery B1. The peak-to-peak value of the CH2 waveform is 328 mV. The current is measured by a Hall sensor with a range of 3 A and a rated output of 1.65 ± 0.625 V. The maximum current of the inductor in this balancing sub-unit is 1.57 A.

[0081] During the balancing process, the waveform of the inductor voltage of the balancing sub-unit is as Figure 9 shown. When PWM in CH1 is at a high level, the inductor is the load, and the voltage difference across the inductor is -3.6 V, and battery B2 charges it. When PWM is at a low level, the inductor outputs energy, similar to a power source, and the terminal voltage is 5 V to charge battery B1. The waveform of the E1 balancing sub-unit is similar.

[0082] The discharge current of the battery pack is set to 1 A. During the discharge process, the SOC values and MOS transistor states of the four single cells are shown in Table 2. It is divided into three stages: in the first stage, within the range of [0, 500 s], MOS transistors S1b and E1b conduct; in the second stage, within the range of [500, 2226 s], MOS transistor S1b conducts, and E1b conducts intermittently; in the third stage, within the range of [2226 s, 2500 s], the battery balancing is basically completed, and the MOS transistors are in the off state. The whole process lasts for 2500 s, and the balance is achieved at 2226 s.

[0083] Table 2 Initial values of battery SOC (%) in each stage of active balancing

[0084]

[0085] During the discharge balancing process of the battery pack, the SOC curves of each battery cell are as Figure 10 shown.

[0086] Comparative analysis

[0087] Dissipative equalization: For voltage acquisition, the LTC6803 chip is also selected. The energy dissipation resistor is selected as 30 Ω, and the dissipative equalization current range is [0.126 A, 0.143 A].

[0088] Similar to the non-dissipative equalization experiment, the SOC of each battery cell is the same as before. A 1 A current discharge is also selected. The specific waveform is as Figure 11 shown. At 7500 s, the SOC of battery B2 drops to 0, and the discharge must be stopped. At this moment, the SOC of other battery cells is 2.9%. To determine the dissipative equalization time, the battery pack is charged with a 1 A current. The equalization is completed at 9248 s, and the SOC of the battery cells is 25.93%, 25.94%, 25.94%, and 25.94% respectively.

[0089] In the non-dissipative equalization experiment, the battery equalization is completed at 2219 s. At 7500 s, the average remaining battery charge is 10.1%. In the dissipative equalization experiment, at 7500 s, the equalization is still in an unfinished state, and the average charge at this time is 2.2%. The dissipative equalization completes the battery equalization at 9248 s.

[0090] Using the traditional inductive non-dissipative equalization circuit, the initial SOC state is the same as before. The simulation results of the battery pack SOC equalization are as Figure 12 shown.

[0091] When the charge of battery cell B1 is quite different from that of other batteries, the equalization path is long and the equalization process is very slow. The comparative analysis of the three equalization methods of dissipative equalization, traditional non-dissipative equalization, and binary non-dissipative equalization is shown in Table 3.

[0092] Table 3 Comparison of Equalization Methods

[0093]

[0094]

[0095] Compared with the existing dissipative equalization circuit, the equalization efficiency of the binary equalization circuit is increased by 4.1 times, and the energy loss is only 1 / 25. Compared with the traditional inductive non-dissipative equalization, the equalization efficiency is increased by 1.49 times, and the energy loss is only 3 / 4. Moreover, the binary non-dissipative equalization has obvious advantages in terms of circuit complexity, equalization control complexity, occupied space, scalability, etc.

Claims

1. Battery pack two - branch non - dissipative equalization system, Characterized in that, It includes an equalization sub - unit and batteries B1 and B2 connected thereto, forming an equalization control module; the equalization sub - unit is used to control the charge and discharge of batteries B1 and B2 according to the received control signal to achieve equalization control of the batteries; Among them, the equalizing subunit includes two MOS transistors S connected in series a and MOS transistor S b ; The MOS transistor S b The gate of the MOS transistor S a The gate is used to receive a control signal. The source of the MOS transistor S b is connected to the positive electrode of the battery B2. The drain of the MOS transistor S b is connected to the drain of the MOS transistor S a and is also connected to the negative electrode of the battery B2 and the positive electrode of the battery B1 through an inductor; The source of the MOS transistor S a is connected to the negative electrode of the battery B1; The source and drain of the MOS transistor S b are respectively connected with parasitic diodes between the source and drain of the MOS transistor S a ; Battery pack two - branch non - dissipative equalization control method, including the following steps: Obtain the state of charge of each battery; Judge the state of charge (SOC) of battery B1 connected to the balancing subunit a and the state of charge (SOC) of battery B2 b , and perform balancing control on the batteries by controlling the on / off states of MOS transistor S a and MOS transistor S b : During the battery pack balancing process, for the same module M i the cell balancing within it is carried out by the balancing subunit S i and for the same module E i the balancing between the battery packs M i in the modules is carried out by the balancing subunit E i ; Each S i balancing subunit controls two battery cells, denoted as a and b. S i The MOS transistor S a is turned on under the following conditions: SOC a -SOC b >0.3 S i The S of the medium MOS transistor b The turn-on condition is: SOC b -SOC a >0.3 When the number of batteries n is odd, the last battery does not perform equalization operation and directly enters the second - layer circuit; In the second-layer circuit, each E i equalizer sub-circuit controls two M i modules, denoted as a and b. The i enable condition of E a is as follows: SOC a -SOC b >0.5 E i In E b The opening condition is: SOC b -SOC a >0.5 When the equalization control module M i When the number k is odd, the last equalization control module does not perform equalization operations, and the equalization control module M directly enters the third-layer circuit; Set E i The switching frequency is S i twice that of.

2. The battery pack two - branch non - dissipative equalization system according to claim 1, Characterized in that, For 2 m series-connected batteries, the equalization subunit has m layers, and the number of equalization subunits in the i-th layer is 2 m-i , where i = 1...m; For the j-th equalization subunit of the i-th layer, the 2 i batteries corresponding to it are divided into two battery groups with equal numbers. The battery groups and the equalization subunits of the (i - 1)-th layer connected to them form an equalization control module. The equalization control module is regarded as a battery for the j-th equalization subunit of the i-th layer to perform equalization control, where j = 1…2 m-i .

3. The battery pack two - branch non - dissipative equalization system according to claim 2, Characterized in that, For 2 m For the number of +1 series-connected batteries, the last battery is connected to the last equalization subunit in the second layer and merged with the equalization control module where the last equalization subunit in the first layer is located as the last equalization control module in the first layer for the last equalization subunit in the second layer to perform equalization control.

4. The battery pack two - branch non - dissipative equalization system according to claim 1, Characterized in that, It further includes a control circuit, and the control circuit is used to output a control signal to control the on - off of MOS transistor a and MOS transistor b in the equalization sub - unit.

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