IQ double balanced fet resistive mixer

Abstract

The application discloses an IQ double-balanced FET resistive mixer, an oscillator signal is input from an oscillator quadrature coupler, passes through an oscillator first power amplifier and an oscillator second power amplifier, and then passes through two parallel oscillator first and second baluns to convert the oscillator signal into four oscillator output signals which are connected with four oscillator impedance matching networks respectively and used for two double-balanced FET resistive mixers; a radio frequency signal is input from a radio frequency balun and connected with two radio frequency T junction power dividers respectively to convert the radio frequency signal into four balanced output ports which are used for the two double-balanced FET resistive mixers; four intermediate frequency signals with a phase difference of 90 degrees are led out from the two double-balanced FET resistive mixers, the conversion loss and the image rejection system are improved, the area of the mirror frequency rejection mixer chip part is reduced, and the cost is lowered.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microwave millimeter wave signal source, and particularly relates to an IQ double-balanced FET resistive mixer. BACKGROUND

[0002] The mixer is an indispensable component in the radio frequency microwave circuit system. Whether it is microwave communication, radar, remote control, remote sensing, or reconnaissance and electronic countermeasures, and microwave measurement system, the microwave signal must be reduced to a low frequency by the mixer for processing. In practice, most amplitude modulation, single sideband and digital transmitters need a mixer to transform the signal frequency to a higher frequency, and then transmit it to the air. In order to facilitate the digital processing of the system backend, the received signal frequency needs to be transformed to a lower intermediate frequency band by the mixer, so as to facilitate effective amplification and filtering at the intermediate frequency band, and also easy to optimize the frequency band, thereby improving the gain and selectivity of the receiver.

[0003] The prior art structure is shown in Figure 1 The differential signal generated by the radio frequency signal and the local oscillator signal after the transformer is added to the four same diodes. The advantage of the prior art structure is that the even harmonic components of the local oscillator signal and the radio frequency signal can be suppressed, and the isolation between the ports is good. However, the prior art double-balanced mixer structure has a narrow bandwidth and poor conversion loss, and needs to be improved to solve these problems.

[0004] The mixer using the IQ double-balanced FET resistive mixer structure generally has better performance with higher local oscillator power, so it is difficult to increase the local oscillator power without losing the balance of the local oscillator signal, which increases the difficulty of system design.

[0005] The double-balanced mixer can well suppress the parasitic production, and the isolation of each port is good, so it is an excellent choice for mixer structure design. The isolation of the radio frequency signal port and the local oscillator signal port basically depends on the balance of the FET resistive mixer. The image isolation mainly depends on the balance of the local oscillator signal reaching the gate of the transistor. The radio frequency signal reaches the drain of each double-balanced transistor through the radio frequency balun and T-type junction power divider, and the local oscillator signal needs to pass through the power amplifier and then the balun to reach the gate of the transistor.

[0006] With the change of frequency, the working characteristics of the quadrature coupler and the balun will deteriorate, so it is of great significance to have good isolation between each port and good image isolation and low conversion loss for the mixer. Therefore, it has great application value to research an IQ double-balanced FET resistive mixer with good isolation between each port and image suppression, and low conversion loss. SUMMARY

[0007] In order to overcome the problems existing in the above-mentioned technology, the present application provides an IQ double balanced FET resistive mixer, comprising a local oscillator quadrature coupler, a local oscillator first power amplifier, a local oscillator second power amplifier, a local oscillator first balun, a local oscillator second balun, two double balanced FET resistive mixers, four local oscillator impedance matching networks, two radio frequency T junction power dividers and a radio frequency balun, wherein,

[0008] The local oscillator signal is input from the local oscillator quadrature coupler, passes through the local oscillator first power amplifier and the local oscillator second power amplifier, the local oscillator first power amplifier output is connected to the local oscillator first balun, the local oscillator second power amplifier output is connected to the local oscillator second balun, the local oscillator signal is converted into four local oscillator output signals, which are connected to four local oscillator impedance matching networks respectively, the two local oscillator impedance matching networks connected through the local oscillator first balun input the first double balanced FET resistive mixer, the two local oscillator impedance matching networks connected through the local oscillator second balun input the second double balanced FET resistive mixer, the outputs of the two double balanced FET resistive mixers are input into a radio frequency balun after passing through a radio frequency T junction power divider respectively, and four intermediate frequency signals with a phase difference of 90 degrees are led out from the two double balanced FET resistive mixers.

[0009] Preferably, the first double balanced FET resistive mixer comprises a first FET tube f1, a second FET tube f2, a third FET tube f3 and a fourth FET tube f4, and the second double balanced FET resistive mixer comprises a fifth FET tube f5, a sixth FET tube f6, a seventh FET tube f7 and an eighth FET tube f8, wherein,

[0010] The gate of the first FET tube f1 is connected to the gate of the third FET tube f3, the drain of the first FET tube f1 is connected to the drain of the second FET tube f2, the source of the first FET tube f1 is connected to the source of the fourth FET tube f4, the gate of the second FET tube f2 is connected to the gate of the fourth FET tube f4, the source of the second FET tube f2 is connected to the source of the third FET tube f3, and the drain of the third FET tube f3 is connected to the drain of the fourth FET tube f4.

[0011] The gate of the fifth FET tube f5 is connected to the gate of the seventh FET tube f7, the drain of the fifth FET tube f5 is connected to the drain of the seventh FET tube f7, the source of the fifth FET tube f5 is connected to the source of the eighth FET tube f8, the gate of the sixth FET tube f6 is connected to the gate of the eighth FET tube f8, the source of the sixth FET tube f6 is connected to the source of the seventh FET tube f7, and the drain of the seventh FET tube f7 is connected to the drain of the eighth FET tube f8.

[0012] Preferably, the source of the first FET tube f1 and the source of the fourth FET tube f4 output a signal of a first intermediate frequency IF1, and the source of the second FET tube f2 and the source of the third FET tube f3 output a signal of a second intermediate frequency IF2, as a pair of differential signal output; the source of the sixth FET tube f6 and the source of the seventh FET tube f7 output a signal of a third intermediate frequency IF3, and the source of the fifth FET tube f5 and the source of the eighth FET tube f8 output a signal of a fourth intermediate frequency IF4, as a pair of differential signal output; IF1 and IF3 are a pair of quadrature signals.

[0013] Preferably, the local oscillator first power amplifier includes capacitors C5, C6, C7, C8, C9, C10, C11, C12, resistors R5, R6, R7, inductors L1, L2, L3, L4, and microstrip lines W5, W6; wherein,

[0014] One end of the capacitor C7 is grounded, and the other end is connected to the resistor R7. The other end of the resistor R7 is connected to the gate of the power amplifier tube M1;

[0015] One end of the capacitor C5 is grounded, and the other end is connected to the resistor R5. The other end of the resistor R5 is connected to the capacitor C6. The other end of the capacitor C6 is grounded. One end of the inductor L1 is connected to the capacitor C6, and the other end is connected to the drain of the power amplifier tube M1;

[0016] One end of the capacitor C8 is connected to the gate of the power amplifier tube M1, and the other end is connected to the resistor R6. The other end of the resistor R6 is connected to the drain of the power amplifier tube M1;

[0017] One end of the capacitor C9 is connected to the gate of the power amplifier tube M1, and the other end is connected to the inductor L3. The other end of the inductor L3 is connected to the ground. One end of the inductor L2 is connected to the capacitor C9, and the other end is connected to the capacitor C10. The other end of the capacitor C10 is connected to the ground. One end of the microstrip line W5 is connected to the local oscillator quadrature coupler, and the other end is connected to the inductor L2;

[0018] One end of the capacitor C11 is connected to the drain of the power amplifier tube M1, and the other end is connected to the inductor L4. The other end of the inductor L4 is connected to the capacitor C12. The other end of the capacitor C12 is connected to the ground. One end of the microstrip line W6 is connected to the capacitor C12, and the other end is connected to the local oscillator first balun.

[0019] Preferably, the local oscillator second power amplifier is the same as the local oscillator first power amplifier in composition and structure.

[0020] Preferably, the local oscillator impedance matching network includes capacitors C1, C2, C3, C4, and microstrip lines W1, W2, W3, W4; wherein,

[0021] One end of the capacitor C1 is connected to the local oscillator first balun, and the other end is connected to the gates of the first FET tube f1 and the third FET tube f3;

[0022] One end of the capacitor C2 is connected with the first local oscillator balun, and the other end is connected with the gate of the second FET tube f2 and the fourth FET tube f4;

[0023] One end of the capacitor C3 is connected with the second local oscillator balun, and the other end is connected with the gate of the fifth FET tube f5 and the seventh FET tube f7;

[0024] One end of the capacitor C4 is connected with the second local oscillator balun, and the other end is connected with the gate of the sixth FET tube f6 and the eighth FET tube f8;

[0025] One end of the microstrip line W1 and W2 is connected with the first local oscillator balun, and the other end is connected with the ground;

[0026] One end of the microstrip line W3 and W4 is connected with the second local oscillator balun, and the other end is connected with the ground.

[0027] Preferably, one end of the first local oscillator balun is connected with the microstrip line W6, and the other two output ends are connected with the capacitor C1 and the capacitor C2.

[0028] Preferably, one end of the radio frequency T-junction power divider is connected with the radio frequency balun, and the two output ends are connected with the drain of the two double-balanced FET resistive mixers.

[0029] The beneficial effects of the present application at least include: the local oscillator quadrature coupler adopts a two-stage lumped quadrature coupler, which improves the bandwidth and performance compared with a single-stage lumped quadrature coupler, and in order to save the chip area, an on-chip interleaved winding spiral structure is adopted, which greatly reduces the area compared with a commonly used lange coupler; the local oscillator balun and the radio frequency balun adopt a three-wire spiral balun to improve the overall performance of the balun, thereby optimizing the performance of the mixer; the present application adds a stage of power amplifier between the local oscillator quadrature coupler and the local oscillator balun, which can increase the output power of the four local oscillators as much as possible under the condition that the balance degree of the four local oscillator signals after passing through the local oscillator quadrature coupler, the power amplifier and the local oscillator balun is not affected, that is, increasing the gate power of each FET tube, thereby improving the overall performance of the mixer. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to make the purpose, technical scheme and beneficial effects of the present application clearer, the present application provides the following drawings for illustration:

[0031] Figure 1 It is a structure schematic diagram of a double-balanced mixer of the prior art;

[0032] Figure 2 It is a structure schematic diagram of an IQ double-balanced FET resistive mixer of an embodiment of the present application;

[0033] Figure 3is a two double balanced FET resistive mixer circuit principle diagram of an IQ double balanced FET resistive mixer of an embodiment of the present application;

[0034] Figure 4 is a local oscillator quadrature coupler structure schematic diagram of an IQ double balanced FET resistive mixer of an embodiment of the present application;

[0035] Figure 5 is a local oscillator first power amplifier structure schematic diagram of an IQ double balanced FET resistive mixer of an embodiment of the present application;

[0036] Figure 6 is a local oscillator first balun structure schematic diagram of an IQ double balanced FET resistive mixer of an embodiment of the present application. DETAILED DESCRIPTION

[0037] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0038] Referring to Figure 2 , a structure diagram of an IQ double balanced FET resistive mixer of an embodiment of the present application is shown, comprising a local oscillator quadrature coupler 10, a local oscillator first power amplifier 21, a local oscillator second power amplifier 22, a local oscillator first balun 31, a local oscillator second balun 32, two double balanced FET resistive mixers, four local oscillator impedance matching networks 50, two radio frequency T junction power dividers 60 and a radio frequency balun 70, wherein,

[0039] The local oscillator signal is input from the local oscillator quadrature coupler 10, passes through the local oscillator first power amplifier 21 and the local oscillator second power amplifier 22, the local oscillator first power amplifier 21 output is connected to the local oscillator first balun 31, the local oscillator second power amplifier 22 output is connected to the local oscillator second balun 32, the local oscillator signal is converted into four local oscillator output signals, which are respectively connected to the four local oscillator impedance matching networks 50, the two local oscillator impedance matching networks 50 connected through the local oscillator first balun 31 input the first double balanced FET resistive mixer 41, the two local oscillator impedance matching networks 50 connected through the local oscillator second balun 32 input the second double balanced FET resistive mixer, the outputs of the two double balanced FET resistive mixers are each input to a radio frequency balun 70 after passing through a radio frequency T junction power divider 60, and four intermediate frequency signals with a phase difference of 90 degrees from each other are led out from the two double balanced FET resistive mixers.

[0040] Figure 3 is a schematic diagram of an IQ double balanced FET resistive mixer of the present application. The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings. Figure 2The application is described. The IQ double balanced FET resistive mixer of the application comprises a first and a second double balanced FET resistive mixer, a local oscillator quadrature coupler 10, a local oscillator first power amplifier 21, a local oscillator second power amplifier 22, a local oscillator first balun 31, a local oscillator second balun 32, four local oscillator impedance matching networks 50, a radio frequency balun 70, and two radio frequency T junction power dividers 60. The first and the second double balanced FET resistive mixer comprises a first FET tube f1, a second FET tube f2, a third FET tube f3, a fourth FET tube f4, a fifth FET tube f5, a sixth FET tube f6, a seventh FET tube f7, and an eighth FET tube f8. The first double balanced resistive FET mixer specifically connects the gate of the first FET tube f1 to the gate of the third FET tube f3, connects the drain of the first FET tube f1 to the drain of the second FET tube f2, connects the source of the first FET tube f1 to the source of the fourth FET tube f4, connects the gate of the second FET tube f2 to the gate of the fourth FET tube f4, connects the source of the second FET tube f2 to the source of the third FET tube f3, and connects the drain of the third FET tube f3 to the drain of the fourth FET tube f4. The second double balanced resistive FET mixer specifically connects the gate of the fifth FET tube f5 to the gate of the seventh FET tube f7, connects the drain of the fifth FET tube f5 to the drain of the seventh FET tube f7, connects the source of the fifth FET tube f5 to the source of the eighth FET tube f8, connects the gate of the sixth FET tube f6 to the gate of the eighth FET tube f8, connects the source of the sixth FET tube f6 to the source of the seventh FET tube f7, and connects the drain of the seventh FET tube f7 to the drain of the eighth FET tube f8.

[0041] The radio frequency signal is introduced into the radio frequency balun 70 through the input end 2, and two radio frequency differential signals are generated after passing through the radio frequency balun 70. One of the radio frequency differential signals generates two signals with the same amplitude and phase through the radio frequency T junction power divider 60, and is connected to the drain of the first FET tube f1 and the drain of the second FET tube f2 and the drain of the fifth FET tube f5 and the drain of the sixth FET tube f6, respectively. The other radio frequency differential signal generates two signals with the same amplitude and phase through the radio frequency T junction power divider 60, and is connected to the drain of the third FET tube f3 and the drain of the fourth FET tube f4 and the drain of the seventh FET tube f7 and the drain of the eighth FET tube f8, respectively.

[0042] The local oscillator signal is introduced into the local oscillator quadrature coupler 10 through the input end 1 to generate two local oscillator quadrature signals, one of which is increased in power by the local oscillator first power amplifier 21 and then introduced into the local oscillator first balun 31 to generate two local oscillator differential signals, one of which is introduced into the gate of the first FET f1 and the third FET f3 after passing through the local oscillator impedance matching network 50 capacitor C1 and microstrip line W1, and the other is introduced into the gate of the second FET f2 and the fourth FET f4 after passing through the local oscillator impedance matching network 50 capacitor C2 and microstrip line W2. The other local oscillator quadrature signal is increased in power by the second local oscillator power amplifier and then introduced into the local oscillator second balun 32 to generate two local oscillator differential signals, one of which is introduced into the gate of the fifth FET f5 and the seventh FET f7 after passing through the local oscillator impedance matching network 50 capacitor C3 and microstrip line W3, and the other is introduced into the gate of the sixth FET f6 and the eighth FET f8 after passing through the local oscillator impedance matching network 50 capacitor C4 and microstrip line W4.

[0043] The source of the first FET f1 and the source of the fourth FET f4 output a first intermediate frequency IF1, and the source of the second FET f2 and the source of the third FET f3 output a second intermediate frequency IF2 as a pair of differential signals. The source of the sixth FET f6 and the source of the seventh FET f7 output a third intermediate frequency IF3, and the source of the fifth FET f5 and the source of the eighth FET f8 output a fourth intermediate frequency IF4 as a pair of differential signals. IF1 and IF3 are a pair of quadrature signals.

[0044] The bias network is VG1 introduced into the gate of the first FET f1 and the third FET f3 connected through the resistor R1; VG2 is introduced into the gate of the second FET f2 and the fourth FET f4 connected through the resistor R2; VG3 is introduced into the gate of the fifth FET f5 and the seventh FET f7 connected through the resistor R3; and VG4 is introduced into the gate of the sixth FET f6 and the eighth FET f8 connected through the resistor R4.

[0045] The local oscillator impedance matching network 50 is composed of capacitors and microstrip lines, and includes capacitors C1, C2, C3, C4, microstrip lines W1, W2, W3, and W4.

[0046] One end of the capacitor C1 is connected with the first local oscillator balun 31, and the other end is connected with the gate of the first and third FET f3. One end of the capacitor C2 is connected with the first local oscillator balun 31, and the other end is connected with the gate of the second and fourth FET f4. One end of the capacitor C3 is connected with the second local oscillator balun 32, and the other end is connected with the gate of the fifth and seventh FET f7. One end of the capacitor C4 is connected with the second local oscillator balun 32, and the other end is connected with the gate of the sixth and eighth FET f8. One end of the microstrip line W1 and W2 in the local oscillator impedance matching network 50 is connected with the first local oscillator balun 31, and the other end is connected with the ground. One end of the microstrip line W3 and W4 is connected with the second local oscillator balun 32, and the other end is connected with the ground.

[0047] Figure 4 The structure diagram of the local oscillator quadrature coupler 10 is shown. The local oscillator signal enters from port 3, and outputs from port 4 and port 5. The capacitor C13 and C14 are used to adjust the balance of the output quadrature signal, and the resistor R8 is an isolation resistor. The commonly used lange coupler is to realize tight coupling by means of the interdigital structure of two microstrip lines with a length of one quarter wavelength. However, since the quarter wavelength is too long at the working frequency, a lumped parameter quadrature coupler 10 is used to save area. The local oscillator quadrature coupler 10 uses a two-stage lumped quadrature coupler 10, which improves the bandwidth and performance compared with a single-stage lumped quadrature coupler 10. In order to save the chip area, an on-chip staggered spiral structure is used.

[0048] Figure 5The shown is the first local oscillator power amplifier 21 schematic diagram, the structure and composition of the second local oscillator power amplifier 22 are same. Signal is input from port IN, and is output from port OUT, after passing through power amplifier, under the condition of not affecting the balance of signal, the power of signal is increased. It includes grid bias network, drain bias network, input impedance matching network 50, output impedance matching network 50, negative feedback network. The grid bias network includes capacitor C7, resistor R7. One end of capacitor C7 is grounded, and the other end is connected to resistor R7, the other end of the resistor R7 is connected to the gate of power amplifier tube M1, which provides the gate voltage for power amplifier tube M1. The drain bias network includes capacitor C5, capacitor C6, resistor R5, inductor L1. One end of capacitor C5 is grounded, and the other end is connected to resistor R5, the other end of the resistor R5 is connected to capacitor C6, the other end of the capacitor C6 is grounded, one end of inductor L1 is connected to capacitor C6, and the other end is connected to the drain of power amplifier tube M1. It provides the drain voltage for power amplifier tube M1. The negative feedback network includes capacitor C8, resistor R6, capacitor C8 is connected to the gate of power amplifier tube M1, and the other end of the resistor R6 is connected to the drain of power amplifier tube M1. In order to improve the stability of the tube, in order to make the tube work normally and not to be in self-excited state. The input impedance matching network 50 includes microstrip line W5, capacitor C9, capacitor C10, inductor L2, inductor L3. One end of capacitor C9 is connected to the gate of the tube, and the other end is connected to inductor L3, the other end of the inductor L3 is connected to the ground, one end of inductor L2 is connected to capacitor C9, and the other end is connected to capacitor C10, the other end of the capacitor C10 is connected to the ground, one end of microstrip line W5 is connected to the local oscillator quadrature coupler 10, and the other end is connected to inductor L2. The output impedance matching network 50 includes microstrip line W6, capacitor C11, capacitor C12, inductor L4. One end of capacitor C11 is connected to the drain of power amplifier tube M1, and the other end is connected to inductor L4, the other end of the inductor L4 is connected to capacitor C12, the other end of the capacitor C12 is connected to the ground, one end of microstrip line W6 is connected to capacitor C12, and the other end is connected to the first and second local oscillator balun 32.

[0049] Figure 6 The first local oscillator balun 31 structure schematic diagram, the structure and composition of the second local oscillator balun 32 and the radio frequency balun 70 are same, and are not described. The three-wire spiral balun structure is adopted in the application, signal is input from port 6, and a pair of differential signals is output from port 7 and port 8. Multi-conductor coupler is usually used to realize high coupling coefficient, multi-conductor Marchand balun can expand the working bandwidth, but multiple coupling lines will increase the area of the balun, and three coupling line balun can solve the contradiction between working bandwidth and area. In order to reduce the area, spiral planar structure is adopted.

[0050] Finally, it should be noted that the above preferred embodiments are merely intended to illustrate the technical solutions of the present application but not to limit the present application. Although the present application has been described in detail through the above preferred embodiments, those skilled in the art should understand that various modifications can be made in form and details without departing from the scope of the present application defined by the claims.

Claims

1. An IQ dual-balanced FET resistive mixer, characterized in that, This includes a local oscillator quadrature coupler, a first local oscillator power amplifier, a second local oscillator power amplifier, a first local oscillator balun, a second local oscillator balun, two double-balanced FET resistive mixers, four local oscillator impedance matching networks, two RF T-junction power dividers, and an RF balun. The local oscillator signal is input from the local oscillator quadrature coupler, passes through the first local oscillator power amplifier and the second local oscillator power amplifier. The output of the first local oscillator power amplifier is connected to the first local oscillator balun, and the output of the second local oscillator power amplifier is connected to the second local oscillator balun, converting the local oscillator signal into four local oscillator output signals, which are respectively connected to four local oscillator impedance matching networks. The two local oscillator impedance matching networks connected by the first local oscillator balun are input to the first double-balanced FET resistive mixer, and the two local oscillator impedance matching networks connected by the second local oscillator balun are input to the second double-balanced FET resistive mixer. The outputs of the two double-balanced FET resistive mixers are each input to an RF T-junction power divider after passing through an RF balun. Four intermediate frequency signals with a 90-degree phase difference are drawn from the two double-balanced FET resistive mixers. The first double-balanced FET resistive mixer includes a first FET f1, a second FET f2, a third FET f3, and a fourth FET f4; the second double-balanced resistive FET mixer includes a fifth FET f5, a sixth FET f6, a seventh FET f7, and an eighth FET f8. The gate of the first FET f1 is connected to the gate of the third FET f3, the drain of the first FET f1 is connected to the drain of the second FET f2, the source of the first FET f1 is connected to the source of the fourth FET f4, the gate of the second FET f2 is connected to the gate of the fourth FET f4, the source of the second FET f2 is connected to the source of the third FET f3, and the drain of the third FET f3 is connected to the drain of the fourth FET f4. The gate of the fifth FET f5 is connected to the gate of the seventh FET f7, the drain of the fifth FET f5 is connected to the drain of the seventh FET f7, the source of the fifth FET f5 is connected to the source of the eighth FET f8, the gate of the sixth FET f6 is connected to the gate of the eighth FET f8, the source of the sixth FET f6 is connected to the source of the seventh FET f7, and the drain of the seventh FET f7 is connected to the drain of the eighth FET f8. The local oscillator first power amplifier includes capacitors C5, C6, C7, C8, C9, C10, C11, and C12; resistors R5, R6, and R7; inductors L1, L2, L3, and L4; and microstrip lines W5 and W6; wherein, One end of capacitor C7 is grounded, and the other end is connected to resistor R7. The other end of resistor R7 is connected to the gate of power amplifier transistor M1. One end of capacitor C5 is grounded, and the other end is connected to resistor R5. The other end of resistor R5 is connected to capacitor C6, and the other end of capacitor C6 is grounded. One end of inductor L1 is connected to capacitor C6, and the other end is connected to the drain of power amplifier tube M1. One end of capacitor C8 is connected to the gate of power amplifier transistor M1, and the other end is connected to resistor R6. The other end of resistor R6 is connected to the drain of power amplifier transistor M1. One end of capacitor C9 is connected to the gate of power amplifier tube M1, and the other end is connected to inductor L3. The other end of inductor L3 is grounded. One end of inductor L2 is connected to capacitor C9, and the other end is connected to capacitor C10. The other end of capacitor C10 is grounded. One end of microstrip line W5 is connected to the local oscillator quadrature coupler, and the other end is connected to inductor L2. One end of capacitor C11 is connected to the drain of power amplifier tube M1, and the other end is connected to inductor L4. The other end of inductor L4 is connected to capacitor C12, and the other end of capacitor C12 is grounded. One end of microstrip line W6 is connected to capacitor C12, and the other end is connected to the first balun of the local oscillator.

2. The IQ dual-balanced FET resistive mixer as described in claim 1, characterized in that, The source output signal of the first FET f1 and the source output signal of the fourth FET f4 are the first intermediate frequency IF1, and the source output signal of the second FET f2 and the source output signal of the third FET f3 are the second intermediate frequency IF2, which are output as a pair of differential signals; the source output signal of the sixth FET f6 and the source output signal of the seventh FET f7 are the third intermediate frequency IF3, and the source output signal of the fifth FET f5 and the source output signal of the eighth FET f8 are the fourth intermediate frequency IF4, which are output as a pair of differential signals; IF1 and IF3 are a pair of quadrature signals.

3. The IQ dual-balanced FET resistive mixer as described in claim 1, characterized in that, The second local oscillator power amplifier has the same composition and structure as the first local oscillator power amplifier.

4. The IQ dual-balanced FET resistive mixer as described in claim 1, characterized in that, The local oscillator impedance matching network includes capacitors C1, C2, C3, and C4, and microstrip lines W1, W2, W3, and W4; wherein, One end of the capacitor C1 is connected to the first balun of the local oscillator, and the other end is connected to the gates of the first FET f1 and the third FET f3. One end of the capacitor C2 is connected to the first balun of the local oscillator, and the other end is connected to the gates of the second FET f2 and the fourth FET f4. One end of the capacitor C3 is connected to the second balun of the local oscillator, and the other end is connected to the gates of the fifth FET f5 and the seventh FET f7. One end of the capacitor C4 is connected to the second balun of the local oscillator, and the other end is connected to the gates of the sixth FET f6 and the eighth FET f8. One end of the microstrip lines W1 and W2 is connected to the first balun of the local oscillator, and the other end is connected to ground; One end of the microstrip lines W3 and W4 is connected to the second balun of the local oscillator, and the other end is connected to ground.

5. The IQ dual-balanced FET resistive mixer as described in claim 4, characterized in that, One end of the first balun of the local oscillator is connected to the microstrip line W6, and the other two output ends are connected to capacitors C1 and C2.

6. The IQ dual-balanced FET resistive mixer as described in claim 1, characterized in that, One end of the RF T-junction power divider is connected to an RF balun, and the two output terminals are connected to the drains of two double-balanced FET resistive mixers.

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