Duty cycle signal processing circuit, method, and audio signal processing device

Abstract

The application discloses a duty cycle signal processing circuit, a method and an audio signal processing device; the duty cycle signal processing circuit comprises an amplitude detector and an operation unit; the amplitude detector is used for detecting a first amplitude of an audio signal, generating a second amplitude, and sending the second amplitude to the operation unit; the operation unit is used for acquiring a power supply voltage, and performing operation processing on the second amplitude and the power supply voltage to obtain a duty cycle control signal matched with at least one parameter in the second amplitude and the power supply voltage. The application can improve the conversion efficiency of a corresponding power amplifier unit.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a duty cycle signal processing circuit, method, and audio signal processing device. Background Technology

[0002] Class D amplifiers and their corresponding duty cycle signal processing circuits are essential components of audio signal processing equipment. Taking Class D amplifiers as an example, they can be used for pulse width modulation of audio signals. Compared to traditional linear amplifiers, Class D amplifiers have high conversion efficiency, which not only extends the lifespan of the chip's power supply battery but also reduces heat dissipation. For high-power amplifier chips, only a small heatsink is needed, or none at all, saving on chip packaging costs. With continuous improvements in chip manufacturing processes and circuit design, Class D amplifiers are increasingly approaching the sound quality of traditional linear amplifiers, making them extremely popular in the audio amplifier market.

[0003] Class D power amplifiers consist of two complementary switching power transistors in their output stage. Driven by high-frequency control pulses, these transistors operate in an on-state, similar to an inverter. When one transistor is on, the other is off. Therefore, the switching power transistors do not require quiescent current, resulting in high conversion efficiency. Theoretically, this type of amplifier can achieve 100% efficiency. However, in practice, power losses due to the on-resistance of the switching power transistors and the charging and discharging of the LC filter at the amplifier output can affect the conversion efficiency. Summary of the Invention

[0004] In view of this, this application provides a duty cycle signal processing circuit, method, and audio signal processing device to solve the technical problem that traditional solutions affect the conversion efficiency of power amplifier units.

[0005] The first aspect of this application provides a duty cycle signal processing circuit, including an amplitude detector and an arithmetic unit;

[0006] The amplitude detector is used to detect a first amplitude of the audio signal, generate a second amplitude, and send the second amplitude to the processing unit;

[0007] The arithmetic unit is used to acquire the power supply voltage, perform arithmetic processing on the second amplitude and the power supply voltage, and obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage.

[0008] Optionally, the arithmetic unit is further configured to calculate the theoretical duty cycle using a preset arithmetic formula, and determine the duty cycle control signal based on the theoretical duty cycle and the expected duty cycle level. The arithmetic formula is used to characterize the relationship between the theoretical duty cycle, the power supply voltage, and the second amplitude.

[0009] Optionally, the calculation formula includes:

[0010] D PWM *V SUP =V amp_out +V HR ,

[0011] Among them, D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR Indicates the margin of amplitude.

[0012] Optionally, the arithmetic unit includes a comparison subunit and a transcoder; the comparison subunit is used to compare the second amplitude with a plurality of comparison thresholds respectively, and output the comparison result to the transcoder, wherein each comparison threshold is determined according to the power supply voltage, the amplitude margin and the duty cycle level, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage; the transcoder is used to transcode the comparison result to obtain the duty cycle control signal corresponding to the comparison result.

[0013] Optionally, the comparison subunit includes a first comparator, a second comparator, a third comparator, and a fourth comparator, and the comparison threshold includes a first threshold, a second threshold, a third threshold, and a fourth threshold; the first input terminal of the first comparator is connected to the second amplitude, the second input terminal is connected to the first threshold, and the output terminal is connected to the first input terminal of the transcoder; the first input terminal of the second comparator is connected to the second amplitude, the second input terminal is connected to the second threshold, and the output terminal is connected to the second input terminal of the transcoder; the first input terminal of the third comparator is connected to the second amplitude, the second input terminal is connected to the third threshold, and the output terminal is connected to the third input terminal of the transcoder; the first input terminal of the fourth comparator is connected to the second amplitude, the second input terminal is connected to the fourth threshold, and the output terminal is connected to the fourth input terminal of the transcoder.

[0014] Optionally, the expected duty cycle levels include a first duty cycle, a second duty cycle, a third duty cycle, and a fourth duty cycle;

[0015] The first threshold includes: V T1 =A1×V SUP -V HR ;

[0016] The second threshold includes: V T2 =A2×V SUP -V HR ;

[0017] The third threshold includes: V T3 =A3×V SUP -V HR ;

[0018] The fourth threshold includes: V T4 =A4×V SUP -V HR ;

[0019] Among them, V T1 A1 represents the first threshold, V represents the first duty cycle, and V represents the first duty cycle. T2 A2 represents the second threshold, A2 represents the second duty cycle, and V represents the second duty cycle. T3 A3 represents the third threshold, V represents the third duty cycle, and V represents the third threshold. T4 A4 represents the fourth threshold and the fourth duty cycle.

[0020] Optionally, the duty cycle signal processing circuit further includes a common-mode voltage control unit; the input terminal of the common-mode voltage control unit is connected to the output terminal of the arithmetic unit, and is used to perform arithmetic processing according to the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal.

[0021] Optionally, the common-mode voltage control unit includes a voltage divider subunit and a multiplexer; the voltage divider subunit is used to perform multiple voltage divider processes on the input reference voltage to obtain the voltage divider signal after each voltage divider process; the control terminal of the multiplexer is connected to the duty cycle control signal, and selects the corresponding voltage output channel according to the duty cycle control signal to output the corresponding common-mode voltage.

[0022] Optionally, the voltage divider subunit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; the first end of the first resistor is connected to the reference voltage, and the second end is connected to the first end of the second resistor and the first input terminal of the multiplexer; the second end of the second resistor is connected to the first end of the third resistor and the second input terminal of the multiplexer; the second end of the third resistor is connected to the first end of the fourth resistor and the third input terminal of the multiplexer; the second end of the fourth resistor is connected to the first end of the fifth resistor and the fourth input terminal of the multiplexer; the second end of the fifth resistor is connected to the first end of the sixth resistor and the fifth input terminal of the multiplexer; and the second end of the sixth resistor is grounded.

[0023] Optionally, the duty cycle signal processing circuit further includes an analog-to-digital converter; the analog-to-digital converter is used to acquire the power supply voltage, convert the power supply voltage into a digital signal, and output the converted power supply voltage to the arithmetic unit.

[0024] This application also provides a duty cycle signal processing method, applied to any of the above-mentioned duty cycle signal processing circuits, including:

[0025] Detect the first amplitude of the audio signal and generate the second amplitude;

[0026] The power supply voltage is acquired, and the second amplitude and the power supply voltage are processed to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage.

[0027] Optionally, the method of performing calculations on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: calculating the theoretical duty cycle using a preset calculation formula, and determining the duty cycle control signal based on the theoretical duty cycle and the expected duty cycle level, wherein the calculation formula is used to characterize the relationship between the theoretical duty cycle, the power supply voltage, and the second amplitude.

[0028] Optionally, the calculation formula includes:

[0029] D PWM *V SUP =V amp_out +V HR ,

[0030] Among them, D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR Indicates the margin of amplitude.

[0031] Optionally, the method of performing calculations on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: comparing the second amplitude with a plurality of comparison thresholds respectively, outputting comparison results to the transcoder, wherein each comparison threshold is determined based on the power supply voltage, the amplitude margin, and the duty cycle level, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage; and transcoding the comparison results to obtain the duty cycle control signal corresponding to the comparison results.

[0032] Optionally, the duty cycle signal processing method further includes: performing calculations based on the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal.

[0033] This application also provides an audio signal processing device, including an audio processing unit, a power amplifier unit, a driver, and any of the above-described duty cycle signal processing circuits;

[0034] The audio processing unit is used to perform a first modulation processing on the incoming audio signal to obtain a first modulation signal, and send the first modulation signal to the power amplifier unit.

[0035] The power amplifier unit is used to receive the first modulation signal and the common-mode voltage output by the duty cycle signal processing circuit, perform a second modulation processing on the common-mode voltage according to the first modulation signal to obtain a second modulation signal, and send the second modulation signal to the driver;

[0036] The driver is used to drive the corresponding playback component according to the second modulation signal to play the audio signal.

[0037] Optionally, the audio processing unit includes a delay unit, a DSM modulator, and a digital-to-analog converter; the delay unit is used to delay the audio signal and output the delayed audio signal to the DSM modulator; the DSM modulator is used to perform DSM modulation on the delayed audio signal and output an initial modulation signal; the digital-to-analog converter is used to perform digital-to-analog conversion on the initial modulation signal and output the first modulation signal.

[0038] Optionally, the power amplifier unit includes a PWM modulator; the PWM modulator is used to perform a second modulation process on the common-mode voltage to obtain a second modulation signal.

[0039] Optionally, the power amplifier unit further includes an integrator; the integrator is used to receive the first modulation signal and the common-mode voltage, filter the common-mode voltage according to the first modulation signal, and output the filtered common-mode voltage to the PWM modulator.

[0040] Optionally, the audio signal processing device further includes a playback component connected to the output of the driver.

[0041] In the duty cycle signal processing circuit, method, and audio signal processing device provided in this application, the amplitude detector can send a second amplitude corresponding to the audio signal amplitude to the arithmetic unit, so that the arithmetic unit performs calculations on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage. This signal is then used by subsequent power amplifier units such as Class D power amplifiers to perform driving operations based on the duty cycle control signal. The duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage, so that the power amplifier unit can adaptively adjust the common-mode duty cycle in the power amplifier unit according to at least one parameter of the audio signal amplitude and the power supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will decrease accordingly, reducing the corresponding switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging. This can improve the conversion efficiency of the power amplifier unit, reduce the driving power consumption, thereby reducing the power consumption of the entire audio signal processing device, and will not cause audio signal distortion. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 These are waveform diagrams related to the inventor's research plan;

[0044] Figure 2 This is a schematic diagram of the duty cycle signal processing circuit structure according to an embodiment of this application;

[0045] Figure 3a and Figure 3b This is a schematic diagram of the operational unit structure according to an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of the duty cycle signal processing circuit structure according to another embodiment of this application;

[0047] Figure 5a and Figure 5b This is a schematic diagram of the common-mode voltage control unit structure according to an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the duty cycle signal processing circuit structure according to another embodiment of this application;

[0049] Figure 7 This is a schematic flowchart of a duty cycle signal processing method according to an embodiment of this application;

[0050] Figure 8This is a schematic diagram of the structure of an audio signal processing device according to an embodiment of this application;

[0051] Figure 9 This is a schematic diagram of the structure of an audio signal processing device according to another embodiment of this application;

[0052] Figure 10a , Figure 10b and Figure 10c This is a waveform analysis diagram in one embodiment of this application. Detailed Implementation

[0053] The inventors researched audio processing devices for amplifier units such as Class D sampling amplifiers and found that some solutions employ BD modulation, using pulse width modulation (such as PWM) and a triangular wave (or sawtooth) waveform generator or oscillator to encode the audio input signal. BD modulation modulates the duty cycle of the difference in the output signal so that its average content corresponds to the input analog signal. BD modulation provides superior audio performance to some extent (e.g., reduced pops and ticks). However, when using a low-pass LC filter, BD modulation with no (or low-level) audio signal consumes significantly more power than other common modulation techniques such as AD modulation. BD modulation has a significant common-mode content in its output. Therefore, common-mode duty cycle, inductor current ripple, and power consumption are correlated. Power consumption is highest when the common-mode duty cycle is at or near 50%, because the ripple current is largest at these duty cycles. The scheme employs a common-mode duty cycle of 50% when the analog input signal level is below a threshold level. When the analog input signal level is below the threshold level, the modulator shifts the common-mode duty cycle of each of the first and second quantized signals, making the common-mode duty cycle greater than or less than 50%. Using this method, the power consumed by the load (such as a speaker) is reduced accordingly, thereby improving the efficiency of the power amplifier to some extent; however, the improvement is limited.

[0054] The inventors also discovered that in existing solutions, the common-mode duty cycle of the PWM (Pulse Width Modulation) output is fixed at a small value (e.g., 15%), which can reduce switching on-time and LC charging / discharging time, reduce power consumption, and improve efficiency. However, when the audio signal amplitude is large, a 15% common-mode duty cycle cannot meet the amplitude requirements of signal modulation. It needs to adjust the common-mode reference voltage of the integrator by comparing the output signal of the integrator with the DC reference level, thereby increasing the duty cycle of signal modulation. However, this method will cause the Class D amplifier to enter a single-sided modulation mode, such as... Figure 1As shown in the waveform, only one side of PWM_P and PWM_N flips. In this case, the THD (Total Harmonic Distortion) performance of the audio signal is poor. Therefore, this solution improves the conversion efficiency of the Class D power amplifier, but entering the single-sided pulse width modulation mode will introduce relatively serious signal distortion, resulting in poor THD+N performance of large-signal audio signals. For example, when the signal amplitude is large, the power amplifier entering the single-sided modulation mode will cause audio signal distortion, etc.

[0055] To address the aforementioned issues, this application generates a common-mode voltage that matches at least one parameter of the signal amplitude and the supply voltage through a duty cycle signal processing circuit. This enables the power amplifier unit to adaptively adjust the PWM common-mode duty cycle based on the audio signal amplitude and the supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will decrease accordingly, reducing the switching on time, lowering the static power loss due to the on-resistance, and reducing the power loss due to LC charging and discharging. This improves conversion efficiency, reduces drive power consumption, and thus reduces the power consumption of the entire audio signal processing device without causing audio signal distortion.

[0056] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0057] The first aspect of this application provides a duty cycle signal processing circuit, referencing... Figure 2 As shown, the duty cycle signal processing circuit includes an amplitude detector 110 and an arithmetic unit 200. The input terminal of the amplitude detector 110 is connected to an audio signal, and the output terminal is connected to the first input terminal of the arithmetic unit 200. The second input terminal of the arithmetic unit 200 is connected to a power supply voltage, and the output terminal outputs a duty cycle control signal.

[0058] Specifically, the amplitude detector 110 is used to detect the first amplitude of the audio signal, generate the second amplitude, and send the second amplitude to the arithmetic unit 200; the arithmetic unit 200 is used to acquire the power supply voltage, perform arithmetic processing on the second amplitude and the power supply voltage, and obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that subsequent power amplifier units such as Class D power amplifiers can perform driving operations based on the duty cycle control signal, so that the duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage. In this way, the common mode duty cycle in the power amplifier unit can be adaptively adjusted according to the amplitude of the audio signal and at least one parameter of the power supply voltage. When the signal amplitude is low or in an idle state, the common mode duty cycle will decrease accordingly, reducing the corresponding switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging, thereby improving the conversion efficiency of the power amplifier unit.

[0059] In one example, amplitude detector 110 can perform gain processing on the obtained amplitude after detecting a first amplitude of the audio signal to determine a second amplitude. Optionally, the gain processing performed by amplitude detector 110 on the amplitude may include:

[0060] V amp_out =V amp_in *Gain, where V amp_out Indicates the second amplitude, V amp_in The first amplitude represents the amplitude of the input audio signal, Gain represents the gain parameter, and the symbol * indicates multiplication. Optionally, the audio signal may include a digital audio signal, and the amplitude detector 110 can detect the level amplitude of the digital audio signal to obtain the amplitude of the audio signal.

[0061] In one example, the arithmetic unit 200 may include devices such as comparators and / or transcoders capable of processing the second amplitude and power supply voltage to obtain the desired duty cycle control signal. Optionally, this example may set expected duty cycle levels, such as 50%, 40%, 30%, 20%, and 10%. This allows the arithmetic unit 200 to process the second amplitude, power supply voltage, and the corresponding duty cycles for these expected duty cycle levels to obtain the corresponding duty cycle, simplifying the calculation process and improving its stability.

[0062] In one embodiment, the arithmetic unit is further configured to calculate the theoretical duty cycle using a preset arithmetic formula, and determine the duty cycle control signal based on the theoretical duty cycle and the expected duty cycle level. The arithmetic formula characterizes the relationship between the theoretical duty cycle, the power supply voltage, and the second amplitude, so that the theoretical duty cycle calculated using the arithmetic formula matches at least one parameter among the second amplitude and the power supply voltage. Optionally, in this embodiment, the theoretical duty cycle can be rounded up to obtain the corresponding duty cycle signal, or the duty cycle level that is greater than or equal to and closest to the theoretical duty cycle from the expected duty cycle levels can be selected as the duty cycle control signal.

[0063] Optionally, the calculation formula includes: D PWM *V SUP =V amp_out +V HR , where D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR This represents the amplitude margin, V. HR The margin of the maximum allowable signal amplitude relative to the actual maximum signal amplitude without distortion in the theory characterizing the common-mode duty cycle setting can be set through configuration, for example, it can be set to a value of 1V (volts). The above calculation formula for the duty cycle control signal can enable the calculation unit 200 to obtain a more accurate duty cycle control signal.

[0064] In one embodiment, reference Figure 3a and Figure 3b As shown, the arithmetic unit 200 includes a comparison subunit 210 and a transcoder 220. The comparison subunit 210 compares the second amplitude with multiple comparison thresholds and outputs the corresponding comparison results to the transcoder 220. The transcoder 220 transcodes the comparison results to obtain the duty cycle control signal corresponding to the comparison results. Each comparison threshold is based on the power supply voltage V. SUP The amplitude margin V HR The expected duty cycle level is determined so that the duty cycle control signal corresponding to the comparison result matches at least one parameter of the second amplitude and the power supply voltage. Optionally, as... Figure 3a As shown, the comparison threshold may include V T1 To V Tn There are n threshold values. The number of comparison thresholds can be determined based on the number of duty cycle positions to be designed. For example, if N duty cycle positions need to be set to be adjustable, then N-1 comparison thresholds and N-1 corresponding comparators can be set, etc.

[0065] In one example, refer to Figure 3b As shown, the comparison subunit 210 includes a first comparator CMP1, a second comparator CMP2, a third comparator CMP3, and a fourth comparator CMP4, and the comparison threshold includes a first threshold V. T1 Second threshold V T2 Third threshold V T3 and the fourth threshold V T4 The first input terminal of the first comparator CMP1 is connected to the second amplitude V. amp_out The second input terminal is connected to the first threshold V. T1 The output terminal is connected to the first input terminal of the transcoder 220; the first input terminal of the second comparator CMP2 is connected to the second amplitude V. amp_out The second input terminal is connected to the second threshold V. T2 The output terminal is connected to the second input terminal of the transcoder 220; the first input terminal of the third comparator CMP3 is connected to the second amplitude V. amp_out The second input terminal is connected to the third threshold V. T3 The output terminal is connected to the third input terminal of the transcoder 220; the first input terminal of the fourth comparator CMP4 is connected to the second amplitude V. amp_out The second input terminal is connected to the fourth threshold V. T4 The output terminal is connected to the fourth input terminal of the transcoder 220.

[0066] Specifically, the expected duty cycles include four levels: a first duty cycle A1, a second duty cycle A2, a third duty cycle A3, and a fourth duty cycle A4; correspondingly, the first threshold includes: V T1 =A1×V SUP -V HR The second threshold includes: V T2 =A2×V SUP -V HR The third threshold includes: V T3 =A3×V SUP -V HR The fourth threshold includes: V T4 =A4×V SUP -V HR Among them, V T1 A1 represents the first threshold, V represents the first duty cycle, and V represents the first duty cycle. T2 A2 represents the second threshold, A2 represents the second duty cycle, and V represents the second duty cycle. T3 A3 represents the third threshold, V represents the third duty cycle, and V represents the third threshold. T4 A4 represents the fourth threshold and the fourth duty cycle.

[0067] Optionally, the expected duty cycle may also include a fifth duty cycle, A5. The values ​​of the first duty cycle A1, second duty cycle A2, third duty cycle A3, fourth duty cycle A4, and fifth duty cycle A5 can be set according to the modulation requirements of the corresponding Class D power amplifier unit. For example, the first duty cycle A1 can be set to 10%, the second duty cycle A2 to 20%, the third duty cycle A3 to 30%, the fourth duty cycle A4 to 40%, and the fifth duty cycle A5 to 50%. In this case, the fourth threshold V... T4 This represents the judgment threshold corresponding to the 50% level. When V amp_out >V T4 When the 50% setting is selected, the transcoder 220 outputs a duty cycle control signal corresponding to 50% (such as a 50% duty cycle indicator signal, etc.). The third threshold V T3 This represents the judgment threshold corresponding to the 40% level. When V T4 ≥V amp_out >V T3 When the 40% setting is selected, the transcoder 220 outputs the duty cycle control signal corresponding to 40%. The second threshold V... T2 This represents the judgment threshold corresponding to the 30% level. When V T3 ≥V amp_out >V T2 When the 30% setting is selected, the transcoder 220 outputs the duty cycle control signal corresponding to 30%. First threshold V T1 This represents the judgment threshold corresponding to the 20% level. When V T2 ≥V amp_out >V T1 When the 20% setting is selected, the transcoder 220 outputs the duty cycle control signal corresponding to 20%, V amp_out ≤V T1 When the 10% setting is selected, the transcoder 220 outputs a duty cycle control signal corresponding to 10%. Accordingly, as... Figure 3b As shown, the duty cycle control signal output by the transcoder 220 can be denoted as VCM_SEL<4:0>. VCM_SEL<4:0> includes five duty cycle control signals: VCM_SEL4, VCM_SEL3, VCM_SEL2, VCM_SEL1, and VCM_SEL0.

[0068] In one embodiment, reference Figure 4 As shown, the duty cycle signal processing circuit also includes a common-mode voltage control unit 120. The input terminal of the common-mode voltage control unit 120 is connected to the output terminal of the arithmetic unit 200. It is used to perform arithmetic processing according to the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal, so as to provide the common-mode voltage to power amplifier units such as Class D power amplifiers, adjust the common-mode duty cycle of Class D power amplifier units, and thereby improve the conversion efficiency.

[0069] Optionally, the common-mode voltage control unit 120 may include a voltage divider subunit or other unit for obtaining multiple voltage levels, so as to perform voltage division processing according to factors such as the expected duty cycle level, and obtain the common-mode voltage corresponding to the duty cycle control signal.

[0070] In one example, refer to Figure 5a and Figure 5b As shown, the common-mode voltage control unit 120 includes a voltage divider subunit 121 and a multiplexer 122; the voltage divider subunit 121 is used to perform multiple voltage divider processes on the input reference voltage VDD to obtain the voltage divider signals after each voltage divider process, such as... Figure 5b VCM_D10 to VCM_D50 are shown; the control terminal of the multiplexer 22 is connected to the duty cycle control signal, and the corresponding voltage output channel is selected according to the duty cycle control signal to output the corresponding common mode voltage. Here, the common mode voltage includes the voltage divider signal output by the corresponding voltage output channel.

[0071] Specifically, refer to Figure 5bAs shown, the voltage divider subunit 121 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The voltage divider signals include a first signal VCM_D10, a second signal VCM_D20, a third signal VCM_D30, a fourth signal VCM_D40, and a fifth signal VCM_D50. The first terminal of the first resistor R1 is connected to the reference voltage VDD, and the second terminal is connected to the first terminal of the second resistor R2 and the first input terminal of the multiplexer 122. The second end of R2 is connected to the first end of the third resistor R3 and the second input end of the multiplexer 122; the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and the third input end of the multiplexer 122; the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5 and the fourth input end of the multiplexer 122; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the fifth input end of the multiplexer 122; the second end of the sixth resistor R6 is grounded. The multiplexer 122 may include five voltage output channels, which are connected to a duty cycle control signal VCM_SEL<4:0>. The multiplexer selects the corresponding voltage output channel according to the duty cycle control signal. For example, when receiving VCM_SEL4, the multiplexer 122 may select the first channel and output the first signal VCM_D10 as the common-mode voltage; when receiving VCM_SEL3, it may select the second channel and output the second signal VCM_D20 as the common-mode voltage; when receiving VCM_SEL2, it may select the third channel and output the third signal VCM_D30 as the common-mode voltage; when receiving VCM_SEL1, it may select the fourth channel and output the fourth signal VCM_D40 as the common-mode voltage; and when receiving VCM_SEL0, it may select the fifth channel and output the fifth signal VCM_D50 as the common-mode voltage.

[0072] In one embodiment, reference Figure 6 As shown, the duty cycle signal processing circuit also includes an analog-to-digital converter 130; the analog-to-digital converter 130 is used to acquire the power supply voltage, convert the power supply voltage into a digital signal, and output the converted power supply voltage to the arithmetic unit 200, so that the arithmetic unit 200 performs arithmetic processing based on the digital form of the power supply voltage, thereby improving the stability of the processing.

[0073] In the above audio signal processing device, the amplitude detector 110 can send a second amplitude corresponding to the audio signal amplitude to the arithmetic unit 200, so that the arithmetic unit 200 performs calculations on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage. This signal is then used to drive subsequent power amplifier units such as Class D power amplifiers. The duty cycle control signal matches at least one parameter of the second amplitude and the power supply voltage, so that the common-mode duty cycle in the power amplifier unit can be adaptively adjusted according to at least one parameter of the audio signal amplitude and the power supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will decrease accordingly, reducing the corresponding switch-on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging, thereby improving the conversion efficiency of the power amplifier unit.

[0074] This application provides a duty cycle signal processing method in a second aspect, applied to the duty cycle signal processing circuit described in any of the above embodiments, with reference to... Figure 7 As shown, the duty cycle control signal processing method includes S310 and S320.

[0075] S310 detects the first amplitude of the audio signal and generates the second amplitude;

[0076] S320: Obtain the power supply voltage, perform calculations on the second amplitude and the power supply voltage, and obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage.

[0077] In one embodiment, the method of performing calculations on the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: calculating the theoretical duty cycle using a preset calculation formula, and determining the duty cycle control signal based on the theoretical duty cycle and the expected duty cycle level, wherein the calculation formula is used to characterize the relationship between the theoretical duty cycle, the power supply voltage, and the second amplitude.

[0078] Optionally, the calculation formula includes:

[0079] D PWM *V SUP =V amp_out +V HR ,

[0080] Among them, D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR Indicates the margin of amplitude.

[0081] In one embodiment, Figure 7 In step S320, the method for processing the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes:

[0082] The second amplitude is compared with multiple comparison thresholds, and the comparison results are output to the transcoder. Each comparison threshold is determined based on the power supply voltage, the amplitude margin, and the duty cycle level, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage.

[0083] The comparison result is transcoded to obtain the duty cycle control signal corresponding to the comparison result.

[0084] In one embodiment, the duty cycle signal processing method further includes: performing calculations based on the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal.

[0085] The duty cycle signal processing method described above, when applied to the duty cycle signal processing circuit described in any of the above embodiments, has all the beneficial effects of the duty cycle signal processing circuit described in any of the above embodiments, and will not be repeated here.

[0086] This application provides an audio signal processing device in a third aspect, with reference to... Figure 8 As shown, the audio signal processing device includes an audio processing unit 410, a power amplifier unit 420, a driver 430, and a duty cycle signal processing circuit 500 as described in any of the above embodiments.

[0087] The audio processing unit 410 is used to perform a first modulation processing on the incoming audio signal to obtain a first modulation signal, and send the first modulation signal to the power amplifier unit 420.

[0088] The power amplifier unit 420 is used to receive the first modulation signal and the common-mode voltage output by the duty cycle signal processing circuit 500, perform a second modulation processing on the common-mode voltage according to the first modulation signal to obtain a second modulation signal, and send the second modulation signal to the driver 430.

[0089] The driver 430 is used to drive the corresponding playback component 440 according to the second modulation signal to play the audio signal.

[0090] Optionally, the audio processing unit 410 may include components such as a DSM modulator for transmitting and modulating audio signals. The power amplifier unit 420 may include a Class D power amplifier. Optionally, the driver 430 and the analog-to-digital converter 130 in the duty cycle signal processing circuit 500 are also connected to an external power supply, the voltage of which is the power supply voltage V. SUP .

[0091] The aforementioned audio signal processing device uses the duty cycle signal processing circuit 500 described in any of the above embodiments to generate a common-mode voltage power amplifier unit 420 for second modulation processing, enabling the power amplifier unit 420 to adaptively adjust the PWM common-mode duty cycle according to the audio signal amplitude and power supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will decrease accordingly, reducing the switching on time, reducing the static power loss of the on-resistance, and the power loss of LC charging and discharging, thereby improving the conversion efficiency.

[0092] In one embodiment, reference Figure 9 As shown, the audio processing unit 410 includes a delay unit 411, a DSM modulator (triangular integral modulator) 412, and a digital-to-analog converter 413; the input of the delay unit 411 is connected to an audio signal, which may include a digital audio signal, and the output is connected to the digital-to-analog converter 413 through the DSM modulator 412.

[0093] The delay unit 411 is used to delay the audio signal and output the delayed audio signal to the DSM modulator 412; the DSM modulator 412 is used to perform DSM modulation on the delayed audio signal and output an initial modulation signal; the digital-to-analog converter 413 is used to perform digital-to-analog conversion on the initial modulation signal and output the first modulation signal. Optionally, the delay time of the delay unit 411 can be set according to factors such as the response characteristics of the audio signal, for example, it can be set to a delay time of 1ms (milliseconds). The delay unit 411 delays the audio signal, which can make the duty cycle control signal in the duty cycle signal processing circuit 500 respond to the audio signal and / or power supply voltage in advance, thereby improving the corresponding modulation effect.

[0094] In one embodiment, reference Figure 9 As shown, the power amplifier unit includes a PWM modulator 422; the PWM modulator 422 is used to perform a second modulation process on the common-mode voltage to obtain a second modulation signal, and output the second modulation signal to the driver 430. Optionally, as... Figure 9As shown, if the power amplifier unit includes an integrator 421, the PWM modulator 422 can be connected between the integrator 421 and the driver 430. If the power amplifier unit does not include an integrator 411, the PWM modulator 422 can be connected between the audio processing unit 410 (such as a digital-to-analog converter 413) and the driver 430. In this case, one input terminal of the PWM modulator 422 can also be connected to the output terminal of the duty cycle signal processing circuit 500 (such as a common-mode voltage control unit 120).

[0095] Optionally, such as Figure 9 As shown, the power amplifier unit 420 further includes an integrator 421; the integrator 421 is used to receive the first modulation signal and the common-mode voltage, filter the common-mode voltage according to the first modulation signal, and output the filtered common-mode voltage to the PWM modulator 422 so that the PWM modulator 422 generates a corresponding control waveform according to the common-mode voltage, and the driver 430 performs driving operation according to the control waveform.

[0096] In one example, the audio signal processing device further includes a playback component 440 connected to the output of the driver 430 to play a corresponding audio signal under the drive of the driver 430. Optionally, the playback component 440 may include a speaker or other component for playing audio signals.

[0097] In one example, the inventors analyzed the operation of the PWM modulator 422 in the power amplifier unit 420 and found that the PWM modulator 422 performs a second modulation process to generate a control waveform, which includes the PWM common-mode duty cycle. If the supply voltage remains constant, the variation characteristics of the PWM common-mode duty cycle with the audio signal amplitude can be referenced. Figure 10a As shown, from Figure 10a As can be seen, with the supply voltage remaining constant, when the input audio signal level (amplitude) is high, the PWM common-mode duty cycle remains at 50%; when the audio signal level decreases, the common-mode duty cycle gradually decreases (for example, successively becoming 40%, 30%, 20%, and 10%); when the input is idle, the output duty cycle remains at 10%. If the audio signal amplitude remains constant, the variation characteristics of the PWM common-mode duty cycle with the supply voltage can be referenced. Figure 10b As shown, from Figure 10b It can be seen that when the audio signal amplitude remains constant, a higher power supply voltage results in a smaller PWM common-mode duty cycle, while a lower power supply voltage results in a larger PWM common-mode duty cycle. Specifically, for example... Figure 10bAs shown, when a high power supply voltage is detected, the common-mode duty cycle will decrease after a certain delay, demonstrating that the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a slow exit function; when a low power supply voltage is detected, the PWM common-mode duty cycle increases rapidly, and the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a fast entry function. Figure 10a As shown, when the audio signal level is detected to be low, the common-mode duty cycle will decrease after a certain delay, demonstrating that the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a slow exit function; when the audio signal level is detected to be high, the PWM common-mode duty cycle increases rapidly, and the duty cycle control signal generated by the duty cycle signal processing circuit 500 can provide a fast entry function. The inventors also studied the traditional PWM modulation process and found that the common-mode of the triangular wave in traditional PWM modulation is the same as the common-mode of the input audio signal, for example, 0.5AVDD. Therefore, the common-mode duty cycle of the output signal is usually 50%. To change the duty cycle of the output common-mode signal, the DC reference level of the signal must be changed, such as... Figure 10c As shown, when the corresponding common-mode voltage VC increases, the duty cycle of the static output signal decreases significantly, wherein the amplitude V of the triangular wave... OSC =0.5*AVDD±0.058*AVCC, the common-mode output signal duty cycle D is:

[0098] ,

[0099] in, Indicates the amplitude V of the triangular wave OSC The highest value, Indicates the amplitude V of the triangular wave OSCThe lowest value. The above formula gives the relationship between the static output signal duty cycle and the DC reference level. The circuit for generating the DC reference level is as follows. In the figure, VH and VL are the peak values ​​of the triangular wave. The operational amplifier clamps 1 / 2*AVDD as the intermediate value of VH and VL. Through voltage division by resistors, the common-mode levels of the integrator corresponding to 10%, 20%, 30%, 40%, and 50% are obtained. The audio processing device provided in this application can use adaptive duty cycle modulation technology to monitor the amplitude of the audio signal and the power supply voltage. After relevant calculations, it is determined that the signal voltage will not exceed the maximum DC reference voltage of the power supply level. Through comparative analysis, the inventors found that the audio processing device using the duty cycle signal processing circuit 500 described in any of the above embodiments has the following advantages: 1. According to the amplitude of the audio signal and the power supply voltage, the common-mode duty cycle of the power amplifier output is adaptively adjusted, reducing the power loss of the switching resistor and LC charging and discharging, improving the power amplifier efficiency, and without causing audio signal distortion. 2. Pre-detecting the audio signal amplitude allows for prediction of the output audio signal. If an increase in audio signal amplitude is predicted, the common-mode duty cycle can be adjusted to the corresponding level in advance. 3. Detecting the current power amplifier voltage and using it as a reference for common-mode duty cycle adjustment allows for adaptation to a wide range of power supply voltage variations. 4. Controlling the common-mode duty cycle adjustment slowly prevents audio signal anomalies caused by sudden large common-mode duty cycle switching. 5. The comparison threshold can be flexibly configured.

[0100] In the aforementioned audio signal processing device, the duty cycle signal processing circuit 500 generates a common-mode voltage that matches at least one parameter of the signal amplitude and the power supply voltage. The power amplifier unit 420 can adaptively adjust the PWM common-mode duty cycle according to the audio signal amplitude and the power supply voltage. When the signal amplitude is low or in an idle state, the common-mode duty cycle will decrease accordingly, reducing the switching on time, reducing the static power loss of the on-resistance and the power loss of LC charging and discharging, improving the conversion efficiency, reducing the driving power consumption, and thus reducing the power consumption of the entire audio signal processing device.

[0101] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0102] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A duty cycle signal processing circuit, characterized in that, Includes an amplitude detector and a processing unit; The amplitude detector is used to detect a first amplitude of the audio signal, generate a second amplitude, and send the second amplitude to the processing unit; The arithmetic unit is used to acquire the power supply voltage, perform arithmetic processing on the second amplitude and the power supply voltage, and obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that the power amplifier unit adaptively adjusts the common mode duty cycle according to at least one parameter of the second amplitude and the power supply voltage. The duty cycle signal processing circuit further includes a common-mode voltage control unit; the input terminal of the common-mode voltage control unit is connected to the output terminal of the arithmetic unit, and is used to perform arithmetic processing according to the duty cycle control signal to obtain the common-mode voltage corresponding to the duty cycle control signal; the common-mode voltage is used to input the power amplifier unit of the audio signal processing device, so that the power amplifier unit performs a second modulation processing on the common-mode voltage according to the first modulation signal corresponding to the audio signal to obtain a second modulation signal for driving the playback component.

2. The duty cycle signal processing circuit according to claim 1, wherein the arithmetic unit is further configured to calculate the theoretical duty cycle using a preset arithmetic formula, and determine the duty cycle control signal based on the theoretical duty cycle and the expected duty cycle level, wherein the arithmetic formula is used to characterize the relationship between the theoretical duty cycle, the power supply voltage and the second amplitude.

3. The duty cycle signal processing circuit according to claim 2, characterized in that, The calculation formula includes: D PWM *V SUP =V amp_out +V HR , Among them, D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR Indicates the margin of amplitude.

4. The duty cycle signal processing circuit according to claim 3, characterized in that, The arithmetic unit includes a comparison subunit and a transcoder; The comparison subunit is used to compare the second amplitude with a plurality of comparison thresholds respectively, and output the comparison result to the transcoder. Each of the comparison thresholds is determined according to the power supply voltage, the amplitude margin and the duty cycle level, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage. The transcoder is used to transcode the comparison result to obtain the duty cycle control signal corresponding to the comparison result.

5. The duty cycle signal processing circuit according to claim 4, characterized in that, The comparison subunit includes a first comparator, a second comparator, a third comparator, and a fourth comparator, and the comparison threshold includes a first threshold, a second threshold, a third threshold, and a fourth threshold; The first input terminal of the first comparator is connected to the second amplitude, the second input terminal is connected to the first threshold, and the output terminal is connected to the first input terminal of the transcoder. The first input of the second comparator is connected to the second amplitude, the second input is connected to the second threshold, and the output is connected to the second input of the transcoder. The first input terminal of the third comparator is connected to the second amplitude, the second input terminal is connected to the third threshold, and the output terminal is connected to the third input terminal of the transcoder. The first input of the fourth comparator is connected to the second amplitude, the second input is connected to the fourth threshold, and the output is connected to the fourth input of the transcoder.

6. The duty cycle signal processing circuit according to claim 5, characterized in that, The expected duty cycle levels include the first duty cycle, the second duty cycle, the third duty cycle, and the fourth duty cycle; The first threshold includes: V T1 =A1×V SUP -V HR ; The second threshold includes: V T2 =A2×V SUP -V HR ; The third threshold includes: V T3 =A3×V SUP -V HR ; The fourth threshold includes: V T4 =A4×V SUP -V HR ; Among them, V T1 A1 represents the first threshold, V represents the first duty cycle, and V represents the first duty cycle. T2 A2 represents the second threshold, A2 represents the second duty cycle, and V represents the second duty cycle. T3 A3 represents the third threshold, V represents the third duty cycle, and V represents the third threshold. T4 A4 represents the fourth threshold and the fourth duty cycle.

7. The duty cycle signal processing circuit according to claim 1, characterized in that, The common-mode voltage control unit includes a voltage divider subunit and a multiplexer; The voltage divider subunit is used to perform multiple voltage divider processes on the input reference voltage to obtain the voltage divider signal after each voltage divider process. The control terminal of the multiplexer is connected to the duty cycle control signal, and the corresponding voltage output channel is selected according to the duty cycle control signal to output the corresponding common-mode voltage.

8. The duty cycle signal processing circuit according to claim 7, characterized in that, The voltage divider subunit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; The first terminal of the first resistor is connected to the reference voltage, and the second terminal is connected to the first terminal of the second resistor and the first input terminal of the multiplexer. The second terminal of the second resistor is connected to the first terminal of the third resistor and the second input terminal of the multiplexer. The second terminal of the third resistor is connected to the first terminal of the fourth resistor and the third input terminal of the multiplexer. The second terminal of the fourth resistor is connected to the first terminal of the fifth resistor and the fourth input terminal of the multiplexer. The second terminal of the fifth resistor is connected to the first terminal of the sixth resistor and the fifth input terminal of the multiplexer. The second terminal of the sixth resistor is grounded.

9. The duty cycle signal processing circuit according to claim 1, characterized in that, It also includes an analog-to-digital converter; the analog-to-digital converter is used to acquire the power supply voltage, convert the power supply voltage into a digital signal, and output the converted power supply voltage to the arithmetic unit.

10. A duty cycle signal processing method, characterized in that, The circuit applied to the duty cycle signal processing circuit according to any one of claims 1 to 9 includes: Detect the first amplitude of the audio signal and generate the second amplitude; The power supply voltage is acquired, and the second amplitude and the power supply voltage are processed to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage, so that the power amplifier unit adaptively adjusts the common mode duty cycle according to at least one parameter of the second amplitude and the power supply voltage. The common-mode voltage corresponding to the duty cycle control signal is obtained by performing calculations based on the duty cycle control signal.

11. The duty cycle signal processing method according to claim 10, characterized in that, The method for processing the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: The theoretical duty cycle is calculated using a preset calculation formula. The duty cycle control signal is determined based on the theoretical duty cycle and the expected duty cycle level. The calculation formula is used to characterize the relationship between the theoretical duty cycle, the power supply voltage, and the second amplitude.

12. The duty cycle signal processing method according to claim 11, characterized in that, The calculation formula includes: D PWM *V SUP =V amp_out +V HR , Among them, D PWM V represents the theoretical duty cycle. SUP Indicates the power supply voltage, V amp_out Indicates the second amplitude, V HR Indicates the margin of amplitude.

13. The duty cycle signal processing method according to claim 12, characterized in that, The method for processing the second amplitude and the power supply voltage to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage further includes: The second amplitude is compared with multiple comparison thresholds, and the comparison results are output to the transcoder. Each comparison threshold is determined based on the power supply voltage, the amplitude margin, and the duty cycle level, so that the duty cycle control signal corresponding to the comparison threshold matches at least one parameter of the second amplitude and the power supply voltage. The comparison result is transcoded to obtain the duty cycle control signal corresponding to the comparison result.

14. An audio signal processing device, characterized in that, Includes an audio processing unit, a power amplifier unit, a driver, and a duty cycle signal processing circuit as described in any one of claims 1 to 9; The audio processing unit is used to perform a first modulation processing on the incoming audio signal to obtain a first modulation signal, and send the first modulation signal to the power amplifier unit. The power amplifier unit is used to receive the first modulation signal and the common-mode voltage output by the duty cycle signal processing circuit, perform a second modulation processing on the common-mode voltage according to the first modulation signal to obtain a second modulation signal, and send the second modulation signal to the driver; The driver is used to drive the corresponding playback component according to the second modulation signal to play the audio signal.

15. The audio signal processing device according to claim 14, characterized in that, The audio processing unit includes a delay unit, a DSM modulator, and a digital-to-analog converter; The delay unit is used to delay the audio signal and output the delayed audio signal to the DSM modulator; The DSM modulator is used to perform DSM modulation on the delayed audio signal and output an initial modulated signal. The digital-to-analog converter is used to perform digital-to-analog conversion on the initial modulation signal and output the first modulation signal.

16. The audio signal processing device according to claim 14, characterized in that, The power amplifier unit includes a PWM modulator; the PWM modulator is used to perform a second modulation process on the common-mode voltage to obtain a second modulation signal.

17. The audio signal processing device according to claim 16, characterized in that, The power amplifier unit further includes an integrator; the integrator is used to receive the first modulation signal and the common-mode voltage, filter the common-mode voltage according to the first modulation signal, and output the filtered common-mode voltage to the PWM modulator.

18. The audio signal processing device according to claim 14, characterized in that, It also includes a playback component, which is connected to the output of the driver.

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