A capacitance test structure and test method

Abstract

The present invention discloses a capacitance test structure and test method. The test method comprises the following steps: step S1, applying a fixed drain voltage less than the turn-on voltage of the MOS device to the shorted source and drain terminals; step S2, applying a scan voltage to the gate terminal to keep the capacitor device in a linear operating state; step S3, obtaining the drain current and establishing a relationship model between the drain current and the gate-source voltage; and step S4, obtaining a transconductance-gate voltage curve based on the obtained relationship model between the drain current and the gate-source voltage, thereby obtaining a curve showing the change in capacitance with gate voltage. The present invention solves the problem that traditional C-V scan testing cannot accurately measure the actual capacitance change of small-sized MOS devices under operating conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device testing, and in particular to a novel device capacitance testing structure and testing method. Background Art

[0002] In the field of semiconductor testing, to accurately characterize and measure the capacitance of MOS devices, the gate-substrate capacitance test method is generally used. That is, a voltage signal is applied to the gate end and the signal is collected at the bulk end of the substrate. In other words, a simple CV scan (gate to substrate) can be performed on the MOS capacitor to characterize the change trend of the MOS gate capacitance with the gate end voltage. However, this test method is only suitable for accurately testing the capacitance of MOS devices with a large width / length size.

[0003] For example Figure 1 The NMOS device shown in the structure has a high-concentration N-type doping (N+) 22, a high-concentration N-type doping (N+) 24, and a high-concentration P-type doping (P+) 26 arranged sequentially from one side to the other in a P-well (PW) 80. Between the high-concentration N-type doping (N+) 22 and the high-concentration N-type doping (N+) 24 is a portion of the P-well (PW) 80, on which silicon dioxide (SiO2) 30 is deposited. A gate (Gate) is then formed on 30. A shallow trench (STI) 10 is used to isolate the high-concentration N-type doping (N+) 24 and the high-concentration P-type doping (P+) 26. Polysilicon is grown on 22, 24, and 26, and electrodes are drawn out to form the source, drain, and substrate bulk. In the prior art, the drain and source are short-circuited, and the MOS capacitor to be measured is formed between the gate and the substrate bulk.

[0004] like Figure 2 As shown, the prior art applies a scan voltage signal (force Sweep signal) to the gate, collects the signal at the bulk end of the substrate, and measures the current (measure I). F is a probe for applying voltage V, G is a probe for measuring current I, and the source and drain are short-circuited and left floating.

[0005] The traditional CV curve test method has a convergent and stable curve for traditional planar structures (bulk structures) with a large width / length ratio, such as Figure 3a As shown in the figure, when the device width is large enough and the length is small, the boundary effect brought by the AA edge process has a greater impact on the actual capacitance of the device, such as Figure 3bAs shown, this will affect the actual test results. The figure shows CAP Vd = 0V, CAP Vd = 0.1V, CAP Vd = 0.6V, and CAP Vd = 1.2V, which are the capacitance-voltage data when the voltage Vd from the drain / source to the substrate is 0V, 0.1V, 0.6V, and 1.2V respectively. When the device size is small, the parasitic capacitance accounts for a large proportion of the total capacitance, and the impact of AA / Poly edge on capacitance is more significant, such as Figure 3c As shown in the figure, CAPV0, CAP V0D1, CAP V0D6, and CAP V1D2 are the capacitance-voltage data when the voltage Vd from the drain / source to the substrate is 0V, 0.1V, 0.6V, and 1.2V respectively; the capacitance change in the actual operation of a small-size device is tested by the CV curve. The AA / Poly edge boundary effect has too great an impact and cannot reflect the capacitance change in a real device.

[0006] For smaller devices, they are easily affected by the parasitic capacitance caused by the gate poly edge and the AA edge (active area edge), which will greatly reduce the test accuracy. Summary of the Invention

[0007] In order to overcome the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a capacitance test structure and test method to solve the problem that traditional CV scan test cannot accurately measure the actual capacitance change of small-size MOS devices under working conditions.

[0008] To achieve the above and other purposes, the present invention proposes a capacitance test structure, including a source terminal, a drain terminal, a gate terminal and a substrate terminal. The source and drain terminals are short-circuited, a fixed drain voltage (Vds) less than the turn-on voltage of the MOS device is applied to the short-circuited source and drain terminals, and a scanning voltage is applied to the gate terminal to keep the capacitance device always in a linear working state.

[0009] Preferably, by monitoring the curve of the drain current (Id) changing with the gate-source voltage (Vgs), the transconductance gate voltage curve is obtained according to the curve of the drain current (Id) changing with the gate-source voltage (Vgs), thereby obtaining a curve of the capacitance changing with the gate voltage.

[0010] Preferably, the scanning voltage has a voltage range of 0-1.2V.

[0011] Preferably, the drain current (Id) is measured by connecting an ammeter in series with the short-circuited source and drain terminals to obtain a curve of the drain current (Id) changing with the gate-source voltage (Vgs).

[0012] Preferably, the transconductance (Gm) is obtained by taking the derivative of the drain current (Id) with respect to the gate-source voltage (Vgs), thereby obtaining the transconductance-gate voltage curve.

[0013] To achieve the above object, the present invention further provides a capacitance testing method, comprising the following steps:

[0014] Step S1, applying a fixed drain voltage (Vds) smaller than the threshold voltage of the MOS device to the short-circuited source and drain terminals;

[0015] Step S2, applying a scanning voltage to the gate terminal to keep the capacitor device in a linear working state;

[0016] Step S3, obtaining the drain current and establishing a relationship model between the drain current and the gate-source voltage;

[0017] Step S4: obtaining a transconductance-gate voltage curve based on the obtained relationship model between the drain current and the gate-source voltage, thereby obtaining a curve showing a change in capacitance with gate voltage.

[0018] Preferably, in step S4, the transconductance is obtained by taking the derivative of the drain current with respect to the gate-source voltage, thereby obtaining the transconductance-gate voltage curve.

[0019] Preferably, the scanning voltage has a voltage range of 0-1.2V.

[0020] Compared with the prior art, the capacitance test structure and test method of the present invention applies a fixed drain voltage Vds to the short-circuited source and drain terminals and applies a scanning voltage to the gate terminal, so that the MOS device is always in a linear working state. By monitoring the changing trend of Gm with VGs, the changing trend of the total capacitance with VGs in the actual working state of the MOS is monitored, which solves the problem that traditional CV scanning test cannot accurately measure the actual capacitance change of small-sized MOS devices in the working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A structural diagram of a MOS capacitor with an NMOS device structure;

[0022] Figure 2 This is a schematic diagram of the testing principle of the prior art;

[0023] Figure 3a The capacitance-voltage data diagram of a large-size, small-length device measured by the prior art;

[0024] Figure 3b The capacitance-voltage data diagram of a small-width device measured by the prior art;

[0025] Figure 3cThe capacitance-voltage data diagram of a small-sized device measured by the prior art;

[0026] Figure 4 1 is a schematic structural diagram of a capacitance test structure in an exemplary embodiment of the present invention;

[0027] Figure 5 A flow chart of the steps of a capacitance testing method of the present invention;

[0028] Figure 6a and Figure 6b They are respectively the Id-Vg curve and the Gm-Vg curve of the embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention using specific examples and accompanying drawings. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through other different specific examples, and the details in this specification may be modified and altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 4 FIG. 1 is a schematic diagram of a capacitance test structure in an exemplary embodiment of the present invention. Figure 4 As shown, in an embodiment of the present invention, the capacitance test structure is a capacitance test structure of a MOS device, including a source terminal (Source), a drain terminal (Drain), a gate (Gate) and a substrate bulk terminal, wherein the source and drain terminals (Source / Drain) are short-circuited, and a fixed drain voltage Vds is applied to the short-circuited source and drain terminals (Source / Drain). The fixed drain voltage Vds is less than the turn-on voltage of the MOS device, typically 0.1V, and the substrate is grounded; a scanning voltage is applied to the gate (Gate) terminal to keep the MOS device in a linear working state. In this embodiment, the voltage range of the scanning voltage is 0-1.2V. By monitoring the change curve of the drain current Id with the gate-source voltage Vgs, the transconductance gate voltage curve Gm-Vg curve is obtained according to the change curve of the drain current Id with the gate-source voltage Vgs, thereby obtaining a curve of capacitance change with gate voltage, i.e., C-Vg curve, and monitoring the change trend of capacitance C with gate voltage Vg.

[0031] In the embodiment of the present invention, an ammeter is connected in series to the short-circuited source / drain terminals to measure the drain current Id, and a curve showing the change of the drain current Id with the gate-source voltage Vgs is obtained.

[0032] When the drain voltage is small, the MOS device operates in the linear region. At this time, the physical model relationship between the drain current Id and the gate-source voltage Vgs is as follows:

[0033]

[0034] Among them, Z Un is the device width (device Width), L is the device length (Length).

[0035] According to this relationship, the transconductance Gm can be directly calculated by taking the derivative of the drain current Id with respect to the gate-source voltage Vgs:

[0036]

[0037] When the drain voltage Vds is fixed at 0.1V, the transconductance Gm and the capacitance C have a linear relationship with a constant coefficient. Therefore, the variation trend of the capacitance C with Vg can be monitored through the Gm-Vg curve.

[0038] Figure 5 This is a flow chart of the steps of a capacitance testing method of the present invention. Figure 5 As shown, the present invention provides a capacitance testing method, which is applied to the testing of capacitance of MOS devices, and includes the following steps:

[0039] In step S1 , a fixed drain voltage Vds is applied to the shorted source / drain terminals. The fixed drain voltage Vds is lower than the threshold voltage of the MOS device, typically 0.1V, and the substrate is grounded.

[0040] Step S2: Apply a sweep voltage to the gate terminal to keep the MOS device in a linear operating state. In an embodiment of the present invention, the sweep voltage range is 0-1.2V. Apply a sweep voltage to the gate terminal to keep the MOS device in a linear operating state.

[0041] Step S3: Obtain the drain current and establish a relationship model between the drain current Id and the gate-source voltage Vgs.

[0042] In the embodiment of the present invention, an ammeter may be connected in series to the shorted source / drain terminals to measure the drain current Id.

[0043] When the drain voltage is small, the MOS device operates in the linear region. At this time, the physical model relationship between the drain current Id and the gate-source voltage Vgs is as follows:

[0044]

[0045] Among them, Z Un is the device width (device Width), L is the device length (Length).

[0046] Step S4: Obtain a transconductance gate voltage curve based on the relationship model between the drain current Id and the gate-source voltage Vgs, thereby obtaining a curve showing the change of capacitance with gate voltage.

[0047] According to the physical model relationship between the drain current Id and the gate-source voltage Vgs, the transconductance Gm can be directly calculated by taking the derivative of the drain current with respect to the gate-source voltage Vgs:

[0048]

[0049] When the drain voltage Vds is fixed at 0.1V, the transconductance Gm and the capacitance C have a linear relationship with a constant coefficient. Therefore, the variation trend of the capacitance C with Vg can be monitored through the Gm-Vg curve.

[0050] Example

[0051] In this embodiment, an NMOS device with a width of 9 μm and a length of 0.054 μm was used to verify the test results of the present invention. A sweep voltage of 0-1.2 V was applied to the Gate terminal of the MOS device, and the drain current Id was measured when the drain voltage was fixed at Vds = 0.1 V / 0.6 / V / 1.2 V. A curve of Id changing with Vg was obtained. When the Vd voltage was small, Id and Vgs showed a linear relationship.

[0052] Figure 6a The relationship between drain current and gate voltage is the Id-Vg curve. The transconductance-gate voltage relationship on the right side is obtained by derivation, namely the Gm-Vg curve, as shown in Figure 6b According to the derivation of step S4 above, the C-Vg curve can now be truly obtained through the Gm-Vg curve, reflecting the capacitance change under the actual working state of the MOS. For example, the lower curve in the right figure reflects the change of the capacitance C with the gate Vg of the NMOS under the working voltage of the drain voltage Vds = 0.1V.

[0053] It can be seen that the capacitance test structure and test method of the present invention apply a fixed drain voltage Vds to the short-circuited source and drain terminals and apply a scan voltage to the gate terminal, so that the MOS device is always in a linear working state. By monitoring the change trend of Gm with VGs, the change trend of the total capacitance with VGs in the actual working state of the MOS is monitored, which solves the problem that the traditional CV scan test cannot accurately measure the actual capacitance change of small-sized MOS devices in the working state.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. A MOS device capacitance test device, comprising a source terminal, a drain terminal, a gate terminal, and a substrate terminal, wherein the source and drain terminals are short-circuited, and characterized in that: A fixed drain voltage Vds, which is less than the turn-on voltage of the MOS device, is applied to the short-circuited source and drain terminals, and a scanning voltage is applied to the gate terminal, so that the capacitor device is always in a linear working state; By monitoring the curve of the drain current Id changing with the gate-source voltage Vgs, a transconductance gate voltage curve is obtained according to the curve of the drain current Id changing with the gate-source voltage Vgs, thereby obtaining a curve of the capacitance changing with the gate voltage; The transconductance Gm is obtained by taking the derivative of the drain current Id with respect to the gate-source voltage Vgs, thereby obtaining the transconductance-gate voltage curve, where: , is the device width, L is the device length, and C is the device capacitance.

2. A MOS device capacitance testing device according to claim 1, characterized in that: The scanning voltage has a voltage range of 0-1.2V.

3. The MOS device capacitance testing device according to claim 1, wherein: The drain current Id is measured by connecting an ammeter in series with the short-circuited source and drain terminals to obtain a curve of the drain current Id changing with the gate-source voltage Vgs.

4. A method for testing capacitance of a MOS device, comprising the following steps: Step S1, applying a fixed drain voltage that is less than the turn-on voltage of the MOS device to the short-circuited source and drain terminals; Step S2, applying a scanning voltage to the gate terminal to keep the capacitor device in a linear working state; Step S3, obtaining the drain current and establishing a relationship model between the drain current and the gate-source voltage; Step S4, obtaining a transconductance-gate voltage curve based on the obtained relationship model between the drain current and the gate-source voltage, thereby obtaining a curve showing a change in capacitance with gate voltage; The transconductance is obtained by taking the derivative of the drain current with respect to the gate-source voltage, thereby obtaining the transconductance-gate voltage curve, wherein, , Gm is transconductance, Id is drain current, Vgs is gate-source voltage, Vds is drain voltage, is the device width, L is the device length, and C is the device capacitance.

5. A MOS device capacitance testing method according to claim 4, characterized in that: The scanning voltage has a voltage range of 0-1.2V.

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