Mask pattern correction method and device, and semiconductor device manufacturing method

Abstract

The application provides a mask pattern correction method and device and a semiconductor device manufacturing method. The mask pattern correction method comprises: obtaining an initial pattern of a mask, the initial pattern comprising a scribe slot region and a plurality of spaced chip regions, the scribe slot region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe slot region comprising a scribe slot sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent, and the first sub-TEG region and the second sub-TEG region forming a TEG region; and performing optical proximity correction on a region of the initial pattern other than the TEG region to obtain a final pattern. The method ensures that the final pattern obtained after the OPC does not have a fine gap, avoids the problem that the mask after the OPC has a fine gap in the prior art, and ensures that the final pattern formed has a good effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a mask pattern correction method and device, a computer readable storage medium, a processor, an electronic device and a semiconductor device manufacturing method. BACKGROUND

[0002] In the design process of the early stage of mask manufacturing, some layers need to use OPC (Optical Proximity Correction) to correct the patterns on the mask. As shown in FIG. 1, the patterns of the mask include a chip area 102 and a scribe lane area 100. In the prior art, the chip area 102 and the scribe lane area 100 are first separated for OPC, and then the chip area after OPC is combined with the scribe lane area 100. However, the connection between the scribe lane area 100 and the chip area 102 after combination has a fine gap 103, as shown in FIG. 2, which produces a fine gap pattern, thereby affecting the quality of the mask and the subsequent exposure effect. Figure 1 Figure 2 The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can include some information which is not known to those skilled in the art as prior art.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can include some information which is not known to those skilled in the art as prior art. SUMMARY

[0004] The main purpose of the present application is to provide a mask pattern correction method and device, a computer readable storage medium, a processor, an electronic device and a semiconductor device manufacturing method, to solve the problem of fine gap on the mask after OPC in the prior art.

[0005] According to an aspect of an embodiment of the present application, a mask pattern correction method is provided, comprising: obtaining an initial pattern of a mask, the initial pattern comprising a scribe lane area and a plurality of spaced chip areas, the scribe lane area being located between two adjacent chip areas, the chip area comprising a chip sub-area and a first sub-TEG area, the scribe lane area comprising a scribe lane sub-area and a second sub-TEG area, the first sub-TEG area and the second sub-TEG area being adjacent, the first sub-TEG area and the second sub-TEG area constituting a TEG area; performing optical proximity correction on the area of the initial pattern except the TEG area to obtain a final pattern.

[0006] ​Optionally, the optical proximity correction on the region of the initial pattern other than the TEG region comprises: generating a script for the optical proximity correction, the script having a function of identifying the boundary of the TEG region and not performing the optical proximity correction on the TEG region; and performing the optical proximity correction on the initial pattern by using the script to obtain the final pattern.

[0007] Optionally, the performing the optical proximity correction on the initial pattern by using the script to obtain the final pattern comprises: decomposing the initial pattern into a plurality of first correction regions and a plurality of second correction regions by using the script, the first correction regions comprising the chip sub-regions, the second correction regions comprising the scribe lane sub-regions, and the first correction regions having no overlapping part with the second correction regions; performing the optical proximity correction on the plurality of first correction regions and the plurality of second correction regions respectively; and matching and merging the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

[0008] Optionally, after the matching and merging of the corrected first correction regions and the corrected second correction regions, the method further comprises: detecting whether the overlapping length of the boundary of the merged first correction region and the corresponding boundary of the merged second correction region is greater than or equal to a predetermined length; and determining that the merging is successful in the case that the overlapping length is greater than or equal to the predetermined length.

[0009] Optionally, the initial pattern further comprises a plurality of guard ring regions, and the plurality of guard ring regions are located in the TEG region.

[0010] Optionally, part of the plurality of guard ring regions are located in the first sub-TEG region, and the other guard ring regions are located in the second sub-TEG region.

[0011] According to another aspect of the embodiments of the present application, there is also provided a mask pattern correction device, comprising an acquisition unit and a correction unit, wherein the acquisition unit is configured to acquire an initial pattern of a mask, the initial pattern comprising a scribe lane region and a plurality of spaced chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent to each other and constituting a TEG region; and the correction unit is configured to perform optical proximity correction on a region of the initial pattern other than the TEG region to obtain a final pattern.

[0012] Optionally, the correction unit comprises a generating module and a correction module, wherein the generating module is configured to generate a script for the optical proximity correction, the script having a function of identifying the boundary of the TEG region and not performing the optical proximity correction on the TEG region; and the correction module is configured to perform the optical proximity correction on the initial pattern by using the script to obtain the final pattern.

[0013] Optionally, the correction module comprises a decomposition sub-module, a correction sub-module and a matching sub-module, wherein the decomposition sub-module is configured to decompose the initial pattern into a plurality of first correction regions and a plurality of second correction regions by using the script, the first correction regions comprising the chip sub-regions, the second correction regions comprising the scribe lane sub-regions, and the first correction regions and the second correction regions having no overlapping part; the correction sub-module is configured to perform the optical proximity correction on the plurality of first correction regions and the plurality of second correction regions respectively; and the matching sub-module is configured to match and combine the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

[0014] Optionally, the apparatus further comprises a detection unit and a determination unit, wherein the detection unit is configured to detect whether an overlapping length of a boundary of the combined first correction region and a corresponding boundary of the combined second correction region is greater than or equal to a predetermined length after matching and combining the corrected first correction regions and the corrected second correction regions; and the determination unit is configured to determine that the combination is successful in a case that the overlapping length is greater than or equal to the predetermined length.

[0015] Optionally, the initial pattern further comprises a guard ring region, and the guard ring region is located in the TEG region.

[0016] According to another aspect of embodiments of the present application, a computer readable storage medium is provided, the computer readable storage medium includes a stored program, wherein the program performs any of the methods.

[0017] According to another aspect of embodiments of the present application, a processor is provided, the processor is configured to run a program, wherein the program performs any of the methods when running.

[0018] According to another aspect of embodiments of the present application, an electronic device is provided, comprising one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the methods.

[0019] According to another aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is also provided, comprising: providing a wafer to be processed, a structure layer on a surface of the wafer to be processed being a photoresist layer; placing a mask on the photoresist layer to obtain an exposure assembly, a pattern of the mask being obtained by using any of the correction methods; exposing the exposure assembly; and developing the wafer after exposure.

[0020] In the method for correcting a pattern of a mask, an initial pattern of the mask is first obtained, the initial pattern comprising a scribe lane region and a plurality of spaced-apart chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, and the first sub-TEG region and the second sub-TEG region being adjacent to each other, the first sub-TEG region and the second sub-TEG region constituting a TEG region, that is, the TEG region is adjacent to the chip sub-region and the scribe lane sub-region respectively; and then, performing optical proximity correction on regions of the initial pattern other than the TEG region to obtain a final pattern. Compared with the prior art in which the chip region and the frame are respectively subjected to OPC, and then the chip region and the frame after OPC are combined, resulting in a problem of a thin gap at a connection between the scribe lane and the chip region after combination, in the method, the TEG region between the chip sub-region and the scribe lane sub-region is not subjected to OPC in the process of performing OPC on the initial pattern, so that the polygon edges added to the chip sub-region after correction and the polygon edges added to the scribe lane sub-region after correction both extend to the TEG region, which ensures that the final pattern obtained after OPC does not have a thin gap, avoids the problem of a thin gap on the mask after OPC in the prior art, ensures that the final pattern formed has a good effect, and thus ensures that the photoresist pattern obtained after exposure and development of the wafer according to the final pattern has a good effect. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which form a part of the present description, illustrate the present application and together with the written description serve to explain the principles of the present application. In the drawings:

[0022] Figure 1 A schematic diagram of a pattern of a mask in the prior art is shown;

[0023] Figure 2 A schematic diagram of a pattern of a mask in the prior art subjected to OPC processing is shown;

[0024] Figure 3 A flowchart of a method for correcting a mask layout according to an embodiment of the present application is shown;

[0025] Figure 4 A schematic diagram of an initial layout of a mask according to an embodiment of the present application is shown;

[0026] Figure 5 A schematic diagram of a correcting device for a mask layout according to an embodiment of the present application is shown.

[0027] Wherein, the above figures include the following reference signs:

[0028] 100, scribe lane region; 101, TEG region; 102, chip region; 103, fine slit; 104, chip sub-region; 105, scribe lane sub-region; 106, first sub-TEG region; 107, second sub-TEG region; 108, first guard ring region; 109, second guard ring region. DETAILED DESCRIPTION

[0029] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0030] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should belong to the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0032] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or connected to the other element through a third element.

[0033] For the convenience of description, the following describes some nouns or terms related to the embodiments of the present application:

[0034] OPC: optical proximity correction, the pattern on the mask is projected onto the photoresist through the exposure system, due to the imperfection of the optical system and the diffraction effect, the pattern on the photoresist and the pattern on the mask are not completely consistent, and the optical proximity correction is to correct the pattern on the mask using a calculation method.

[0035] As mentioned in the background, the mask after OPC in the prior art has a fine seam, in order to solve the above problems, in a typical embodiment of the present application, a mask pattern correction method, device, computer readable storage medium, processor, electronic equipment and semiconductor device manufacturing method are provided.

[0036] According to the embodiments of the present application, a mask pattern correction method is provided.

[0037] Figure 3 is a flowchart of the mask pattern correction method according to the embodiments of the present application. As shown in Figure 3 , the method comprises the following steps:

[0038] Step S101, obtaining the initial pattern of the mask, as shown in Figure 4 , the initial pattern comprises a scribe lane region 100 and a plurality of spaced chip regions 102, the scribe lane region 100 is located between two adjacent chip regions 102, the chip region 102 comprises a chip sub-region 104 and a first sub-TEG region 106, the scribe lane region 100 comprises a scribe lane sub-region 105 and a second sub-TEG region 107, the first sub-TEG region 106 and the second sub-TEG region 107 are adjacent, and the first sub-TEG region 106 and the second sub-TEG region 107 constitute a TEG region 101;

[0039] Step S102, performing optical proximity correction on the region of the initial pattern except the TEG region 101 to obtain a final pattern.

[0040] The method for correcting the mask pattern comprises the following steps: firstly, obtaining an initial pattern of a mask, wherein the initial pattern comprises a scribe lane region and a plurality of spaced chip regions, the scribe lane region is located between two adjacent chip regions, the chip region comprises a chip sub-region and a first sub-TEG region, the scribe lane region comprises a scribe lane sub-region and a second sub-TEG region, and the first sub-TEG region and the second sub-TEG region are adjacent, the first sub-TEG region and the second sub-TEG region constitute a TEG region, that is, the TEG region is adjacent to the chip sub-region and the scribe lane sub-region respectively; and then, performing optical proximity correction on the region of the initial pattern except the TEG region to obtain a final pattern. Compared with the prior art in which the chip region and the frame are subjected to OPC respectively, and then the chip region and the frame after OPC are combined, so that the connection between the scribe lane and the chip region after combination has a thin gap, in the method, the TEG region between the chip sub-region and the scribe lane sub-region is not subjected to OPC in the process of performing OPC on the initial pattern, so that the polygon edges added to the chip sub-region after correction and the polygon edges added to the scribe lane sub-region after correction both extend to the TEG region, so that the final pattern obtained after OPC does not have a thin gap, the problem of the thin gap on the mask after OPC in the prior art is avoided, the effect of the final pattern is ensured to be good, and thus the effect of the photoresist pattern obtained after exposure and development of a wafer according to the final pattern is ensured to be good.

[0041] It should be noted that the scribe lane region corresponds to a scribe lane position on a wafer to be subjected to lithography, the chip region corresponds to a chip position on the wafer, and the TEG region corresponds to a TEG pattern position on the wafer.

[0042] In actual application, a large number of patterns are present in the chip sub-region and the scribe lane sub-region, and all of them need to be subjected to OPC.

[0043] In order to further ensure that the other regions of the initial pattern except the TEG region are simply and efficiently optically proximity corrected, according to a specific embodiment of the present application, the method for optically proximity correcting the initial pattern except the TEG region comprises: generating a script for the optical proximity correction, the script having a function of identifying the boundary of the TEG region and not performing the optical proximity correction on the TEG region; and using the script to perform the optical proximity correction on the initial pattern to obtain the final pattern. The script operation further ensures that the TEG region is not corrected when the initial pattern is optically proximity corrected, thereby further ensuring that the obtained group pattern has no fine seams.

[0044] In another specific embodiment of the present application, the script is used to perform the optical proximity correction on the initial pattern to obtain the final pattern, which comprises: using the script to decompose the initial pattern into a plurality of first correction regions and a plurality of second correction regions, the first correction regions including the chip sub-regions, the second correction regions including the scribe lane sub-regions, and the first correction regions and the second correction regions having no overlapping parts; performing the optical proximity correction on the plurality of first correction regions and the plurality of second correction regions respectively; and matching and merging the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

[0045] In actual application, the method for optically proximity correcting the initial pattern is not limited to the above method, and any feasible optical proximity correction method in the prior art can be used to correct the initial pattern, as long as the TEG region of the initial pattern is not corrected.

[0046] In another specific embodiment of the present application, after the matching and merging of the corrected first correction regions and the corrected second correction regions, the method further comprises: detecting whether the overlapping length of the boundary of the merged first correction region and the corresponding boundary of the merged second correction region is greater than or equal to a predetermined length; and determining that the merging is successful when the overlapping length is greater than or equal to the predetermined length. The method further monitors the merging effect of the first correction regions and the second correction regions by detecting the overlapping length of the boundary of the merged first correction region and the corresponding boundary of the merged second correction region.

[0047] According to another specific embodiment of the present application, the initial pattern further comprises a guard ring region, and the guard ring region is located in the TEG region. Through the guard ring region, the chip sub-region and the scribe lane sub-region are protected.

[0048] In actual application, as shown in Figure 4 some of the plurality of guard ring regions are first guard ring regions 108, and the first guard ring regions 108 are located in the first sub-TEG region 106. The other guard ring regions are second guard ring regions 109, and the second guard ring regions 109 are located in the second sub-TEG region 107.

[0049] Specifically, in addition to the guard ring regions, the TEG region further comprises a plurality of test element group regions, and the TEG region has upper and lower boundaries.

[0050] In actual application, the first pattern file of the mask includes the final pattern of the mask, the first pattern file is a GDS or OAS format file, and the first pattern file includes all process parameters of the mask. According to the first pattern file in GDS or OAS format, a second pattern file in MEBES format is obtained after a developing process. The developing process can be positive developing or negative developing.

[0051] It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] The present application also provides a mask pattern correction device. It should be noted that the mask pattern correction device of the present application can be used to execute the mask pattern correction method provided by the present application. The mask pattern correction device provided by the present application is described below.

[0053] Figure 5 is a schematic diagram of the mask pattern correction device according to an embodiment of the present application. As shown in Figure 5 The device comprises an acquisition unit 10 and a correction unit 20, wherein the acquisition unit 10 is configured to acquire an initial pattern of a mask, and the correction unit 20 is configured to correct the initial pattern of the mask. Figure 4As shown, the initial pattern includes a scribe lane region 100 and a plurality of spaced-apart chip regions 102, the scribe lane region 100 is located between two adjacent chip regions 102, the chip region 102 includes a chip sub-region 104 and a first sub-TEG region 106, the scribe lane region 100 includes a scribe lane sub-region 105 and a second sub-TEG region 107, the first sub-TEG region 106 and the second sub-TEG region 107 are adjacent, and the first sub-TEG region 106 and the second sub-TEG region 107 constitute a TEG region 101; the correction unit 20 is configured to perform optical proximity correction on a region of the initial pattern other than the TEG region 101 to obtain a final pattern.

[0054] In the mask pattern correction device, the initial pattern of the mask is obtained by the obtaining unit, the initial pattern includes a scribe lane region and a plurality of spaced-apart chip regions, the scribe lane region is located between two adjacent chip regions, the chip region includes a chip sub-region and a first sub-TEG region, the scribe lane region includes a scribe lane sub-region and a second sub-TEG region, and the first sub-TEG region and the second sub-TEG region are adjacent, and the first sub-TEG region and the second sub-TEG region constitute a TEG region, that is, the TEG region is adjacent to the chip sub-region and the scribe lane sub-region, respectively; the correction unit performs optical proximity correction on a region of the initial pattern other than the TEG region to obtain a final pattern. Compared with the prior art, the chip region and the frame are respectively subjected to OPC, and then the OPC chip region and the frame are combined, which causes a problem of a fine gap at the connection between the scribe lane and the chip region after combination. In the above device, the TEG region between the chip sub-region and the scribe lane sub-region is not subjected to OPC during the OPC of the initial pattern, so that the polygon edges of the corrected chip sub-region and the polygon edges of the corrected scribe lane sub-region both extend to the TEG region, which ensures that the final pattern obtained after OPC does not have a fine gap, avoids the problem of a fine gap on the mask after OPC in the prior art, ensures that the final pattern has a good effect, and thus ensures that the photoresist pattern obtained after exposure and development of the wafer according to the final pattern has a good effect.

[0055] It should be noted that the scribe lane region corresponds to the scribe lane position on the wafer to be lithographed, the chip region corresponds to the chip position on the wafer, and the TEG region corresponds to the TEG pattern position on the wafer.

[0056] In actual application, a large number of patterns are present in the chip sub-region and the scribe lane sub-region, and all of them need to be subjected to OPC.

[0057] To further ensure that the other regions in the initial pattern except the TEG region are simply and efficiently optically proximity corrected, according to an embodiment of the present application, the correction unit comprises a generation module and a correction module, wherein the generation module is configured to generate a script for the optical proximity correction, and the script is configured to identify the boundary of the TEG region and not perform the optical proximity correction on the TEG region; and the correction module is configured to perform the optical proximity correction on the initial pattern by using the script to obtain the final pattern. Through the script operation, the device further ensures that the TEG region is not corrected when the initial pattern is optically proximity corrected, thereby further ensuring that the obtained group pattern has no fine seams.

[0058] In another embodiment of the present application, the correction module comprises a decomposition submodule, a correction submodule, and a matching submodule, wherein the decomposition submodule is configured to decompose the initial pattern into a plurality of first correction regions and a plurality of second correction regions by using the script, the first correction regions comprise the chip sub-regions, the second correction regions comprise the scribe lane sub-regions, and the first correction regions and the second correction regions have no overlapping parts; the correction submodule is configured to perform the optical proximity correction on the plurality of first correction regions and the plurality of second correction regions, respectively; and the matching submodule is configured to match and combine the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

[0059] In another embodiment of the present application, the device further comprises a detection unit and a determination unit, wherein the detection unit is configured to detect whether the overlapping length of the boundary of the combined first correction region and the corresponding boundary of the combined second correction region is greater than or equal to a predetermined length after the matching and combining of the corrected first correction regions and the corrected second correction regions; and the determination unit is configured to determine that the combination is successful if the overlapping length is greater than or equal to the predetermined length. Through the detection of the overlapping length of the boundary of the combined first correction region and the corresponding boundary of the combined second correction region, the device further monitors the combination effect of the first correction regions and the second correction regions.

[0060] According to another embodiment of the present application, the initial pattern further comprises a guard ring region, and the guard ring region is located in the TEG region. Through the guard ring region, the chip sub-regions and the scribe lane sub-regions are protected.

[0061] In actual application, as shown in Figure 4 Part of the plurality of the above-mentioned guard ring regions is a first guard ring region 108, which is located in the first sub-TEG region 106. The other of the above-mentioned guard ring regions is a second guard ring region 109, which is located in the second sub-TEG region 107.

[0062] Specifically, in addition to the above-mentioned guard ring regions, the TEG region further includes a plurality of test element group regions, and the TEG region has upper and lower boundaries.

[0063] In actual application, the first pattern file of the mask includes the final pattern of the mask. The first pattern file is a file in GDS or OAS format. The first pattern file includes all process parameters of the mask. According to the first pattern file in GDS or OAS format, a second pattern file in MEBES format is obtained after a developing process. The developing process can be positive developing or negative developing.

[0064] The mask pattern correction device includes a processor and a memory. The above-mentioned obtaining unit and the above-mentioned correction unit are stored in the memory as program units. The corresponding functions are realized by the processor executing the above-mentioned program units stored in the memory.

[0065] The processor includes a core. The core calls the corresponding program units from the memory. The core can be set to one or more. By adjusting the core parameters, the problem of the fine slit on the mask after OPC in the prior art is solved.

[0066] The memory can include a non-permanent memory in a computer readable medium, a random access memory (RAM) and / or a non-volatile memory such as a read-only memory (ROM) or a flash memory (flash RAM). The memory includes at least one memory chip region.

[0067] The embodiment of the present application provides a computer readable storage medium, which stores a program. The program is executed by a processor to realize the above-mentioned mask pattern correction method.

[0068] The embodiment of the present application provides a processor. The processor is used to run a program. When the program is run, the above-mentioned mask pattern correction method is executed.

[0069] The embodiment of the present application provides a device. The device includes a processor, a memory and a program stored in the memory and run on the processor. When the processor executes the program, at least the following steps are realized:

[0070] In step S101, an initial pattern of a mask is acquired, the initial pattern comprising a scribe lane region and a plurality of spaced-apart chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent, and the first sub-TEG region and the second sub-TEG region constituting a TEG region.

[0071] In step S102, an optical proximity correction is performed on a region of the initial pattern other than the TEG region, to obtain a final pattern.

[0072] The device herein can be a server, a PC, a PAD, a mobile phone, etc.

[0073] The application further provides a computer program product adapted to execute a program comprising at least the following method steps when executed on a data processing device:

[0074] In step S101, an initial pattern of a mask is acquired, the initial pattern comprising a scribe lane region and a plurality of spaced-apart chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent, and the first sub-TEG region and the second sub-TEG region constituting a TEG region.

[0075] In step S102, an optical proximity correction is performed on a region of the initial pattern other than the TEG region, to obtain a final pattern.

[0076] According to another typical embodiment of the application, a method for manufacturing a semiconductor device is further provided, comprising: providing a wafer to be processed, a structure layer on a surface of the wafer to be processed being a photoresist layer; placing a mask on the photoresist layer to obtain an exposure-to-be-performed assembly, a pattern of the mask being obtained by using any one of the above-mentioned correction methods; exposing the exposure-to-be-performed assembly; and developing the wafer after exposure.

[0077] The method for manufacturing the semiconductor device comprises the following steps: providing a wafer to be processed, wherein a structure layer on a surface of the wafer to be processed is a photoresist layer; placing a mask on the photoresist layer to obtain an exposure component, wherein a pattern of the mask is obtained by using any one of the above-mentioned correction methods; exposing the exposure component; and developing the wafer after exposure. The pattern of the mask is obtained by using any one of the above-mentioned correction methods, and the wafer to be processed is exposed and developed by using the mask. In the process of performing OPC on the initial pattern of the mask, the TEG region is not subjected to OPC, so that the pattern obtained after OPC does not have a fine gap, the problem that the mask after OPC has a fine gap in the prior art is avoided, the effect of the pattern of the mask after correction is ensured to be good, and thus the effect of the photoresist pattern of the wafer after exposure and development is ensured to be good, and the photoresist pattern is prevented from having a fine gap pattern.

[0078] In the above embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0079] In several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other manners. Among them, the above-described device embodiments are only schematic, for example, the division of the above-mentioned units can be a logical function division, and in actual implementation, there can be another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, which can be electrical or other forms.

[0080] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on multiple units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0081] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0082] The integrated units described above, if realized in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the above-mentioned method of each embodiment of the present application. The aforementioned storage medium includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0083] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:

[0084] 1) In the above-mentioned mask pattern correction method of the present application, first, an initial pattern of a mask is obtained, the initial pattern includes a scribe lane region and a plurality of spaced chip regions, the scribe lane region is located between two adjacent chip regions, the chip region includes a chip sub-region and a first sub-TEG region, the scribe lane region includes a scribe lane sub-region and a second sub-TEG region, and the first sub-TEG region and the second sub-TEG region are adjacent, the first sub-TEG region and the second sub-TEG region constitute a TEG region, that is, the TEG region is adjacent to the chip sub-region and the scribe lane sub-region respectively; then, the regions of the initial pattern except the TEG region are subjected to optical proximity correction to obtain a final pattern. Compared with the prior art of performing OPC on the chip region and the frame respectively, and then merging the OPC chip region and the frame, the problem of a fine gap at the connection between the scribe lane and the chip region after merging is solved. In the above-mentioned method of the present application, the TEG region between the chip sub-region and the scribe lane sub-region is not subjected to OPC in the process of OPC on the initial pattern, so that the polygon edges added to the modified chip sub-region and the polygon edges added to the modified scribe lane sub-region will extend to the TEG region. This ensures that the final pattern obtained after OPC will not have a fine gap, avoids the problem of a fine gap on the mask after OPC in the prior art, ensures that the effect of the final pattern formed is good, and thus ensures that the effect of the photoresist pattern obtained after exposure and development of the wafer according to the final pattern is good.

[0085] 2) The mask pattern correction device of the present application, the initial pattern of the mask is obtained by the obtaining unit, the initial pattern includes the scribe lane area and the plurality of spaced chip areas, the scribe lane area is located between the two adjacent chip areas, the chip area includes the chip sub-area and the first sub-TEG area, the scribe lane area includes the scribe lane sub-area and the second sub-TEG area, and the first sub-TEG area and the second sub-TEG area are adjacent, the first sub-TEG area and the second sub-TEG area constitute the TEG area, that is, the TEG area is adjacent to the chip sub-area and the scribe lane sub-area respectively; the area of the initial pattern except the TEG area is optically proximity corrected by the correction unit to obtain the final pattern. Compared with the prior art, the chip area and the frame are respectively subjected to OPC, and then the OPC chip area and the frame are merged, which causes the problem of fine seam at the connection of the scribe lane and the chip area after merging. In the process of OPC of the initial pattern, the TEG area between the chip sub-area and the scribe lane sub-area is not subjected to OPC, so that the polygon edges of the corrected chip sub-area and the polygon edges of the corrected scribe lane sub-area are all extended to the TEG area, which ensures that the final pattern obtained after OPC does not have fine seam, avoids the problem of fine seam on the mask after OPC in the prior art, ensures that the effect of the final pattern formed is good, and thus ensures that the photoresist pattern obtained after exposure and development of the wafer according to the final pattern is good.

[0086] 3) The semiconductor device manufacturing method of the present application, first, a wafer to be processed is provided, and the structure layer on the surface of the wafer to be processed is a photoresist layer; then, a mask is placed on the photoresist layer to obtain an exposure-to-be component, wherein the pattern of the mask is obtained by any of the above correction methods; finally, the exposure-to-be component is exposed, and the wafer after exposure is developed. The above method uses any of the above correction methods to obtain the pattern of the mask, and uses the mask to expose and develop the wafer to be processed. Since the correction method does not perform OPC on the TEG area in the process of OPC on the initial pattern of the mask, the pattern obtained after OPC does not have fine seam, avoiding the problem of fine seam on the mask after OPC in the prior art, ensuring that the effect of the pattern of the mask after correction is good, and thus ensuring that the effect of the photoresist pattern of the wafer after exposure and development is good, avoiding the problem of fine seam in the photoresist pattern.

[0087] The above descriptions are only the preferred embodiments of the present application, and are not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of modifying a mask pattern, the method comprising: providing a mask pattern; providing a mask layout; and modifying the mask pattern based on the mask layout. The method comprises: obtaining an initial pattern of a mask, the initial pattern comprising a scribe lane region and a plurality of spaced chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent, the first sub-TEG region and the second sub-TEG region constituting a TEG region; optically proximity correcting regions of the initial pattern other than the TEG region to obtain a final pattern.

2. The method of claim 1, wherein, The optically proximity correcting regions of the initial pattern other than the TEG region comprises: generating a script for the optically proximity correction, the script having a function of identifying boundaries of the TEG region and not performing the optically proximity correction on the TEG region; performing the optically proximity correction on the initial pattern using the script to obtain the final pattern.

3. The method of claim 2, wherein, The performing the optically proximity correction on the initial pattern using the script to obtain the final pattern comprises: decomposing the initial pattern into a plurality of first correction regions and a plurality of second correction regions using the script, the first correction region comprising the chip sub-region, the second correction region comprising the scribe lane sub-region, the first correction region and the second correction region having no overlapping part; respectively performing the optically proximity correction on the plurality of first correction regions and the plurality of second correction regions; matching and merging the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

4. The method of claim 3, wherein, After matching and merging the corrected first correction regions and the corrected second correction regions, the method further comprises: detecting whether an overlapping length of a boundary of the merged first correction region and a corresponding boundary of the merged second correction region is greater than or equal to a predetermined length; in a case where the overlapping length is greater than or equal to the predetermined length, determining that the merging is successful.

5. The method according to any one of claims 1 to 4, characterized in that, The initial pattern further comprises a plurality of spaced guard ring regions, a part of the plurality of guard ring regions being located in the first sub-TEG region, and the other guard ring regions being located in the second sub-TEG region.

6. The method of claim 5, wherein, The method comprises:

7. A device for correcting a mask pattern, characterized in that, an obtaining unit, configured to obtain an initial pattern of a mask, the initial pattern comprising a scribe lane region and a plurality of spaced chip regions, the scribe lane region being located between two adjacent chip regions, the chip region comprising a chip sub-region and a first sub-TEG region, the scribe lane region comprising a scribe lane sub-region and a second sub-TEG region, the first sub-TEG region and the second sub-TEG region being adjacent, the first sub-TEG region and the second sub-TEG region constituting a TEG region; a correcting unit, configured to optically proximity correct regions of the initial pattern other than the TEG region to obtain a final pattern. ​ 8. The apparatus of claim 7, wherein, The correction unit comprises: a generation module configured to generate a script for the optical proximity correction, the script having a function of identifying boundaries of the TEG region and not performing the optical proximity correction on the TEG region; a correction module configured to perform the optical proximity correction on the initial pattern by using the script to obtain the final pattern.

9. The apparatus of claim 8, wherein, The correction module comprises: a decomposition submodule configured to decompose the initial pattern into a plurality of first correction regions and a plurality of second correction regions by using the script, the first correction regions including the chip sub-regions, the second correction regions including the scribe lane sub-regions, and the first correction regions having no overlapping part with the second correction regions; a correction submodule configured to perform the optical proximity correction on the plurality of first correction regions and the plurality of second correction regions respectively; a matching submodule configured to match and combine the corrected first correction regions and the corrected second correction regions to obtain the final pattern.

10. The apparatus of claim 9, wherein, The device further comprises: a detection unit configured to detect whether an overlapping length of a boundary of a combined first correction region and a corresponding boundary of a combined second correction region is greater than or equal to a predetermined length after matching and combining the corrected first correction regions and the corrected second correction regions; a determination unit configured to determine that the combining is successful in a case where the overlapping length is greater than or equal to the predetermined length.

11. The apparatus of any one of claims 7 to 10, wherein, The initial pattern further comprises a guard ring region, and the guard ring region is located in the TEG region.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a stored program, wherein the program performs the method of any one of claims 1 to 6.

13. A processor, comprising: The processor is configured to run a program, wherein the program performs the method of any one of claims 1 to 6 when running.

14. An electronic device, comprising: comprise: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs comprise a program for performing the method of any one of claims 1 to 6.

15. A method of fabricating a semiconductor device, comprising: comprise: providing a wafer to be processed, and a structure layer on a surface of the wafer to be processed is a photoresist layer; placing a mask on the photoresist layer to obtain an exposure-to-be component, and a pattern of the mask is obtained by using the correction method of any one of claims 1 to 6; exposing the exposure-to-be component; developing the wafer after exposure.

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