Gate driving circuit and display panel

Abstract

The present invention discloses a gate driving circuit and a display panel. The gate driving circuit includes: a first control module, a first output module, a second control module, and a second output module. The first output module includes a first control end and a second control end. The first control module is configured to control the potentials of the first control end and the second control end to control the first output module to output a first scan signal. The second output module includes a third control end and a fourth control end. The second control module is respectively connected to the first control end, the second control end, the third control end, and the fourth control end. The second control module controls the potentials of the third control end and the fourth control end based on the potentials of the first control end and the second control end, and further controls the second output module to output a second scan signal. The pulse width of the second scan signal is greater than the pulse width of the first scan signal. The present invention can simplify the structure of the gate driving circuit and achieve a narrow border design.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular, to a gate driving circuit and a display panel. Background Art

[0002] With the continuous development of display technology, the application scope of display panels is becoming more and more extensive, and people's requirements for display panels are also getting higher and higher. A display panel includes a pixel circuit and a gate driving circuit that provides a gate driving signal for the pixel circuit. Among them, the pixel circuit plays a very important role in driving the light-emitting device to emit light stably. With the increase in the functions of the pixel circuit and the increase in the required scan signals, the types and quantities of scan signals that the gate driving circuit needs to provide increase, making the structure of the gate driving circuit more and more complex, and further making the frame width of the display panel larger, which is not conducive to the narrow frame design. Summary of the Invention

[0003] The present invention provides a gate driving circuit and a display panel to simplify the structure of the gate driving circuit, which is conducive to realizing the narrow frame design of the display panel.

[0004] To achieve the above technical purpose, the embodiments of the present invention provide the following technical solutions:

[0005] A gate driving circuit includes:

[0006] A first control module and a first output module. The first output module includes a first control end and a second control end. The first control module is respectively connected to the first control end and the second control end. The first control module is used to control the potentials of the first control end and the second control end. The first output module is used to output a first scan signal according to the potentials of the first control end and the second control end;

[0007] A second control module and a second output module. The second control module is respectively connected to the first control end and the second control end. The second output module includes a third control end and a fourth control end. The third control end and the fourth control end of the second output module are respectively connected to the second control module. The second control module controls the potentials of the third control end and the fourth control end based on the potentials of the first control end and the second control end. The second output module is used to output a second scan signal according to the potentials of the third control end and the fourth control end;

[0008] Wherein, the pulse width of the second scan signal is greater than the pulse width of the first scan signal.

[0009] Optionally, the first control module includes:

[0010] A first input unit, electrically connected to the first control terminal; the first input unit is configured to respond to a first clock signal and transmit an input signal to the first control terminal;

[0011] A potential control unit, electrically connected to the second control terminal; the potential control unit is configured to respond to the first clock signal and transmit a first potential signal to the second control terminal;

[0012] A first node mutual control unit, electrically connected to the first control terminal and the second control terminal respectively; the first node mutual control unit is configured to respond to the potential of the first control terminal and transmit the first clock signal to the second control terminal;

[0013] A second node mutual control unit, electrically connected to the first control terminal and the second control terminal respectively; the second node mutual control unit is configured to respond to a second clock signal and the potential of the second control terminal and transmit a second potential signal to the first control terminal.

[0014] Optionally, the first input unit includes: a first transistor; the gate of the first transistor is connected to the first clock signal, the first pole of the first transistor is connected to the input signal, and the second pole of the first transistor is electrically connected to the first control terminal;

[0015] And / or, the potential control unit includes: a second transistor; the gate of the second transistor is connected to the first clock signal, the first pole of the second transistor is connected to the first potential signal, and the second pole of the second transistor is electrically connected to the second control terminal;

[0016] And / or, the first node mutual control unit includes: a third transistor; the gate of the third transistor is connected to the first control terminal, the first pole of the third transistor is connected to the first clock signal, and the second pole of the third transistor is electrically connected to the second control terminal;

[0017] And / or, the second node mutual control unit includes: a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the second control terminal, the first pole of the fourth transistor is connected to the second potential signal, and the second pole of the fourth transistor is electrically connected to the first pole of the fifth transistor; the gate of the fifth transistor is connected to the second clock signal, and the second pole of the fifth transistor is electrically connected to the first control terminal.

[0018] Optionally, the second control module includes:

[0019] A second input unit, electrically connected to the second control terminal and the fourth control terminal respectively; the second input unit is configured to respond to the second clock signal and transmit the potential of the second control terminal to the fourth control terminal;

[0020] A coupling unit, electrically connected to the first control terminal and the fourth control terminal respectively; the coupling unit is configured to respond to a first clock signal, a second potential signal, the potential of the first control terminal, and the potential of the fourth control terminal, and perform coupling control on the potential of the fourth control terminal;

[0021] A third node mutual control unit, electrically connected to the third control terminal and the fourth control terminal respectively; the third node mutual control unit is configured to respond to the potential of the third control terminal and transmit the second potential signal to the fourth control terminal.

[0022] Optionally, the coupling unit includes: a coupling sub-unit, a first switch sub-unit, and a second switch sub-unit;

[0023] The control terminal of the first switch sub-unit is electrically connected to the first control terminal, the input terminal of the first switch sub-unit receives the second potential signal, and the output terminal of the first switch sub-unit is electrically connected to the first end of the coupling sub-unit;

[0024] The control terminal of the second switch sub-unit is electrically connected to the fourth control terminal, the input terminal of the second switch sub-unit receives the first clock signal, and the output terminal of the second switch sub-unit is electrically connected to the first end of the coupling sub-unit;

[0025] The second end of the coupling sub-unit is electrically connected to the fourth control terminal.

[0026] Optionally, the coupling sub-unit includes: a first capacitor; the first end of the first capacitor serves as the first end of the coupling sub-unit, and the second end of the first capacitor serves as the second end of the coupling sub-unit;

[0027] The first switch sub-unit includes: a sixth transistor; the gate of the sixth transistor serves as the control terminal of the first switch sub-unit, the first pole of the sixth transistor serves as the input terminal of the first switch sub-unit, and the second pole of the sixth transistor serves as the output terminal of the first switch sub-unit;

[0028] The second switch sub-unit includes: a seventh transistor; the gate of the seventh transistor serves as the control terminal of the second switch sub-unit, the first pole of the seventh transistor serves as the input terminal of the second switch sub-unit, and the second pole of the seventh transistor serves as the output terminal of the second switch sub-unit.

[0029] Optionally, the second input unit includes: an eighth transistor; the gate of the eighth transistor receives the second clock signal, the first pole of the eighth transistor is electrically connected to the second control terminal, and the second pole of the eighth transistor is electrically connected to the fourth control terminal;

[0030] And / or, the third node mutual control unit includes: a ninth transistor; a gate of the ninth transistor is electrically connected to the third control terminal, a first pole of the ninth transistor accesses the second potential signal, and a second pole of the ninth transistor is electrically connected to the fourth control terminal.

[0031] Optionally, the first output module includes:

[0032] A first output unit, a control terminal of the first output unit serves as the first control terminal, an input terminal of the first output unit accesses a second clock signal, and an output terminal of the first output unit serves as an output terminal of the first output module;

[0033] A second output unit, a control terminal of the second output unit serves as the second control terminal, an input terminal of the second output unit accesses a second potential signal, and an output terminal of the second output unit is electrically connected to the output terminal of the first output unit;

[0034] Preferably, the first output unit includes: a tenth transistor and a second capacitor; a gate of the tenth transistor serves as the first control terminal and is electrically connected to a first end of the second capacitor; a first pole of the tenth transistor serves as an input terminal of the first output unit; a second pole of the tenth transistor serves as an output terminal of the first output unit and is electrically connected to a second end of the second capacitor;

[0035] The second output unit includes: an eleventh transistor and a third capacitor; a gate of the eleventh transistor serves as the second control terminal and is electrically connected to a first end of the third capacitor; a first pole of the eleventh transistor serves as an input terminal of the second output unit and is electrically connected to a second end of the third capacitor; a second pole of the eleventh transistor serves as an output terminal of the second output unit;

[0036] Preferably, the first output unit further includes: a twelfth transistor; a gate of the twelfth transistor accesses a first potential signal, a first pole of the twelfth transistor serves as the first control terminal, and a second pole of the twelfth transistor is electrically connected to the gate of the tenth transistor.

[0037] Optionally, the second output module includes:

[0038] A third output unit, a control terminal of the third output unit serves as the third control terminal, an input terminal of the third output unit accesses a second potential signal, and an output terminal of the third output unit serves as an output terminal of the second output module;

[0039] The fourth output unit, the control end of the fourth output unit serves as the fourth control end, the input end of the fourth output unit is connected to a first potential signal, and the output end of the fourth output unit is electrically connected to the output end of the third output unit;

[0040] Preferably, the third output unit includes: a thirteenth transistor and a fourth capacitor; the gate of the thirteenth transistor serves as the third control end and is electrically connected to the first end of the fourth capacitor; the first pole of the thirteenth transistor serves as the input end of the third output unit and is electrically connected to the second end of the fourth capacitor; the second pole of the thirteenth transistor serves as the output end of the third output unit;

[0041] The fourth output unit includes: a fourteenth transistor; the gate of the fourteenth transistor serves as the fourth control end, the first pole of the fourteenth transistor serves as the input end of the fourth output unit, and the second pole of the fourteenth transistor serves as the output end of the fourth output unit.

[0042] Correspondingly, an embodiment of the present invention further provides a display panel, including: the gate driving circuit provided in any embodiment of the present invention.

[0043] The gate driving circuit provided by the embodiment of the present invention provides a new driving architecture. Through the settings of the first control module, the first output module, the second control module, and the second output module, a gate driving circuit can output two types of scanning signals with different pulse widths to meet the driving requirements of the pixel circuit. Specifically, the first control module is used to control the first output module and is also used in common with the second control module to control the second output module. Through the reuse of the first control module in the control process of the two output modules, the structure of the gate driving circuit can be simplified, which is beneficial to reducing the border of the display panel. Moreover, the first output module outputs based on the potentials of the first control end and the second control end, and the second control module controls the potentials of the third control end and the fourth control end based on the potentials of the first control end and the second control end, and then controls the output of the second output module. The two output modules are directly or indirectly controlled by the same control signal, and the synchronization of the first scanning signal and the second scanning signal can be automatically achieved without additional adjustment of the control signals of the first control module and the second control module due to considerations of synchronization. Therefore, compared with the prior art, the embodiment of the present invention can simplify the structure of the gate driving circuit and is beneficial to realizing the narrow border design of the display panel.

[0044] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0046] Figure 1 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0047] Figure 2 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0048] Figure 3 is a schematic structural diagram of a second control module provided by an embodiment of the present invention;

[0049] Figure 4 is a schematic structural diagram of yet another gate driving circuit provided by an embodiment of the present invention;

[0050] Figure 5 is a schematic diagram of the driving timing of a gate driving circuit provided by an embodiment of the present invention;

[0051] Figure 6 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0052] Figure 7 is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention;

[0053] Figure 8 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0054] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0056] As described in the background art, with the increase in the functions of pixel circuits and the increase in the required scan signals, the structure of the gate driving circuit becomes more and more complex. Taking the pixel circuit with a 7T1C structure in the prior art as an example, in order to drive the light-emitting device to emit light through this pixel circuit, the gate driving signals that need to be provided to this pixel circuit include: a scan signal with a smaller pulse width (acting on the data writing stage or the initialization stage) and a scan signal with a larger pulse width (acting on the light-emitting stage). In the prior art, the driving circuits for providing the above two types of scan signals are usually separately arranged, and each needs to be provided with a complete control module. The overall gate driving circuit structure formed is complex, occupies a relatively large border width, and is not conducive to the design of narrow borders of the display panel. Moreover, since the two types of driving circuits are not related to each other and are respectively controlled by different clock signals and input signals, it is difficult to ensure the synchronization of the two types of gate driving signals.

[0057] To solve the above problems, an embodiment of the present invention provides a new gate driving circuit. Figure 1 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention. Refer to Figure 1 This gate driving circuit includes: a first control module 10, a first output module 20, a second control module 30, and a second output module 40.

[0058] Among them, the first output module 10 includes a first control terminal N1 and a second control terminal N2. The first control module 10 is respectively connected to the first control terminal N1 and the second control terminal N2. The first control module 10 is used to control the potentials of the first control terminal N1 and the second control terminal N2. The first output module 20 is used to output a first scan signal Vout1 according to the potentials of the first control terminal N1 and the second control terminal N2. The second control module 30 is respectively connected to the first control terminal N1 and the second control terminal N2. The second output module 40 includes a third control terminal N3 and a fourth control terminal N4. The third control terminal N3 and the fourth control terminal N4 of the second output module 40 are respectively connected to the second control module 30. The first control module 10 and the second control module 30 jointly control the potentials of the third control terminal N3 and the fourth control terminal N4; specifically, the first control module 10 controls the potentials of the first control terminal N1 and the second control terminal N2, and the second control module 30 controls the potentials of the third control terminal N3 and the fourth control terminal N4 based on the potentials of the first control terminal N1 and the second control terminal N2. The second output module 40 is used to output a second scan signal Vout2 according to the potentials of the third control terminal N3 and the fourth control terminal N4. Among them, the pulse width of the second scan signal Vout2 is greater than the pulse width of the first scan signal Vout1. Exemplarily, the first scan signal Vout1 can be used as a scan signal for the data writing stage or the initialization stage of the pixel circuit, and the second scan signal Vout2 can be used as a scan signal for the light emitting stage of the pixel circuit (also called the EM signal, that is, the light emission control signal).

[0059] The gate driving circuit provided by the embodiment of the present invention provides a new driving architecture. Through the settings of the first control module 10, the first output module 20, the second control module 30, and the second output module 40, a gate driving circuit can output two types of scanning signals with different pulse widths to meet the driving requirements of the pixel circuit. Specifically, the first control module 10 is used for controlling the first output module 20 and, together with the second control module 30, is also used for controlling the second output module 40. By the reuse of the first control module 10 in the control process of the two output modules (or by the reuse of the potentials of the two nodes, i.e., the first control terminal N1 and the second control terminal N2), the structure of the gate driving circuit can be simplified, which is beneficial to reducing the border of the display panel. Moreover, the first output module 20 outputs based on the potentials of the first control terminal N1 and the second control terminal N2. The second control module 30 controls the potentials of the third control terminal N3 and the fourth control terminal N4 based on the potentials of the first control terminal N1 and the second control terminal N2, and then controls the output of the second output module 40. The two output modules are directly or indirectly controlled by the same control signal, and the synchronization of the first scanning signal Vout1 and the second scanning signal Vout2 can be automatically achieved without additional adjustment of the control signals of the first control module 10 and the second control module 30 for synchronization considerations. Therefore, compared with the prior art, the embodiment of the present invention can simplify the structure of the gate driving circuit and is beneficial to realizing the narrow border design of the display panel.

[0060] The specific structures that each functional module in the gate driving circuit may have will be described below. Figure 2 It is a schematic structural diagram of another gate driving circuit provided by the embodiment of the present invention. Refer to Figure 2 In one implementation manner, optionally, the first control module 10 includes: a first input unit 11, a potential control unit 12, a first node mutual control unit 13, and a second node mutual control unit 14.

[0061] The first input unit 11 is electrically connected to the first control terminal N1 and accesses the input signal SIN and the first clock signal SCK1. The potential control unit 12 is electrically connected to the second control terminal N2 and accesses the first clock signal SCK1 and the first potential signal VGL. The first node mutual control unit 13 is electrically connected to the first control terminal N1 and the second control terminal N2 respectively and accesses the first clock signal SCK1. The second node mutual control unit 14 is electrically connected to the first control terminal N1 and the second control terminal N2 respectively and accesses the second clock signal SCK2 and the second potential signal VGH. Exemplarily, the first potential signal VGL may be a low potential signal, and the second potential signal VGH may be a high potential signal.

[0062] The first input unit 11 is used to control the potential of the first control terminal N1. Specifically, it is used to conduct in response to the first clock signal SCK1 and transmit the input signal SIN to the first control terminal N1. The potential control unit 12 is used to control the potential of the second control terminal N2. Specifically, it is used to conduct in response to the first clock signal SCK1 and transmit the first potential signal VGL to the second control terminal N2. Both the first node mutual control unit 13 and the second node mutual control unit 14 are used for mutual control of the node potentials of the first control terminal N1 and the second control terminal N2, reducing the possibility of an intermediate potential between the high and low potentials of the potential of the first control terminal N1 and the potential of the second control terminal N2, ensuring that the potentials of the two control terminals are clear, enabling the first output module 20 to accurately identify the potentials of the two control terminals, thereby ensuring the accuracy of the output state of the first output module 20 and improving the accuracy and stability of the first scan signal Vout1. Specifically, the first node mutual control unit 13 is used to conduct in response to the potential of the first control terminal N1 and transmit the first clock signal SCK1 to the second control terminal N2. The second node mutual control unit 14 is used to conduct in response to the second clock signal SCK2 and the potential of the second control terminal N2 and transmit the second potential signal VGH to the first control terminal N1.

[0063] Continue to refer to Figure 2 , based on the above embodiments, optionally, the first output module 20 includes: a first output unit 21 and a second output unit 22.

[0064] The control terminal of the first output unit 21 serves as the first control terminal N1. The input terminal of the first output unit 21 is connected to the second clock signal SCK2, and the output terminal of the first output unit 21 serves as the output terminal of the first output module 20. The control terminal of the second output unit 22 serves as the second control terminal N2. The input terminal of the second output unit 22 is connected to the second potential signal VGH, and the output terminal of the second output unit 22 is electrically connected to the output terminal of the first output unit 21, that is, the output terminals of the second output unit 22 and the first output unit 21 jointly serve as the output terminal of the first output module 20.

[0065] Among them, the first output unit 21 is used to control whether to conduct between its input terminal and output terminal according to the potential of the first control terminal N1, thereby controlling whether the second clock signal SCK2 is output as the first scan signal Vout1. The second output unit 22 is used to control whether to conduct between its input terminal and output terminal according to the potential of the second control terminal N2, thereby controlling whether the second potential signal VGH is output as the first scan signal Vout1.

[0066] Continue to refer to Figure 2 , based on the above embodiments, optionally, the second control module 30 includes: a second input unit 31, a coupling unit 32, and a third node mutual control unit 33.

[0067] The second input unit 31 is electrically connected to the second control terminal N2 and the fourth control terminal N4 respectively, and is connected to the second clock signal SCK2. The coupling unit 32 is electrically connected to the first control terminal N1 and the fourth control terminal N4 respectively, and is connected to the first clock signal SCK1 and the second potential signal VGH. The third node mutual control unit 33 is electrically connected to the third control terminal N3 and the fourth control terminal N4 respectively, and is connected to the second potential signal VGH.

[0068] The second input unit 31 is used to conduct in response to the second clock signal SCK2, and transfer the potential of the second control terminal N2 to the fourth control terminal N4. The coupling unit 32 is used to perform coupling control on the potential of the fourth control terminal N4 in response to the first clock signal SCK1, the second potential signal VGH, the potential of the first control terminal N1, and the potential of the fourth control terminal N4. The third node mutual control unit 33 is used to conduct in response to the potential of the third control terminal N3, and transfer the second potential signal VGH to the fourth control terminal N4.

[0069] Continue to refer to Figure 2 , based on the above embodiments, optionally, the second output module 40 includes: a third output unit 41 and a fourth output unit 42.

[0070] The control terminal of the third output unit 41 serves as the third control terminal N3, the input terminal of the third output unit 41 is connected to the second potential signal VGH, and the output terminal of the third output unit 41 serves as the output terminal of the second output module 40. The control terminal of the fourth output unit 42 serves as the fourth control terminal N4, the input terminal of the fourth output unit 42 is connected to the first potential signal VGL, and the output terminal of the fourth output unit 42 is electrically connected to the output terminal of the third output unit 41, that is, the output terminals of the fourth output unit 42 and the third output unit 41 jointly serve as the output terminal of the second output module 40.

[0071] Among them, the third output unit 41 is used to control whether to conduct between its input terminal and output terminal according to the potential of the third control terminal N3, so as to control whether the second potential signal VGH is output as the second scan signal Vout2. The fourth output unit 42 is used to control whether to conduct between its input terminal and output terminal according to the potential of the fourth control terminal N4, so as to control whether the first potential signal VGL is output as the second scan signal Vout2.

[0072] In the gate driving circuit in the prior art, the driving circuit for outputting the first type of scanning signal requires the control of two clock signals and one input signal, and the driving circuit for outputting the second type of scanning signal requires the control of another two clock signals and one input signal. Since the signal lines in the display panel are crisscrossed and affect each other, signal delay is caused. Both driving circuits need to separately set clock signal lines and input signal lines, which will result in a large number of signal lines and serious signal delay. The gate driving circuit provided by the embodiment of the present invention can effectively solve the above problems. Specifically, the second control module 30 borrows the output signal of the first output module 10 and shares the clock signals (including the first clock signal SCK1 and the second clock signal SCK2) accessed by the first control module 10. In the embodiment of the present invention, there is no need to separately provide an input signal and a clock signal to the second control module 30. Compared with the prior art, the effects of reducing the number of signal lines, reducing signal delay, and improving signal synchronization can be achieved.

[0073] Figure 3 It is a schematic structural diagram of a second control module provided by an embodiment of the present invention. Refer to Figure 3 , based on the above embodiments, optionally, in the second control module 30, the coupling unit 32 includes: a coupling subunit 323, a first switch subunit 321, and a second switch subunit 322. The control end of the first switch subunit 321 is electrically connected to the first control end N1. The input end of the first switch subunit 321 accesses the second potential signal VGH. The output end of the first switch subunit 321 is electrically connected to the first end (node N5) of the coupling subunit 323. The control end of the second switch subunit 322 is electrically connected to the fourth control end N4. The input end of the second switch subunit 322 accesses the first clock signal SCK1. The output end of the second switch subunit 322 is electrically connected to the first end (node N5) of the coupling subunit 323. The second end of the coupling subunit 323 is electrically connected to the fourth control end N4.

[0074] Among them, the coupling subunit 232 is used to perform coupling control on the potential of the fourth control end N4 according to the potential of node N5. For example, when voltages are written to both the fourth control end N4 and node N5, the coupling subunit 232 is charged or discharged so that there is a fixed potential difference (the potential difference can be 0 or not 0) between the two ends of the coupling subunit 232; when the potential of the fourth control end N4 is vacant, the coupling subunit 323 couples the change amount of the potential of node N5 to the fourth control end N4. The first switch subunit 321 is used to conduct in response to the potential of the first control end N1 and transmit the second potential signal VGH to node N5. The second switch unit 322 is used to conduct in response to the potential of the fourth control end N4 and transmit the first clock signal SCK1 to node N5.

[0075] In summary, in the embodiment of the present invention, by providing that the coupling unit 32 includes a coupling subunit 323, a first switch subunit 321, and a second switch subunit 322, the coupling control of the potential of the fourth control terminal N4 is realized.

[0076] The above embodiments have exemplarily described the constituent units and their functions of the gate driving circuit. Next, the specific structures that each functional unit may have will be described.

[0077] Figure 4 It is a schematic structural diagram of another gate driving circuit provided by the embodiment of the present invention. Refer to Figure 4 , in one embodiment, optionally, the first input unit 11 includes: a first transistor M1; the gate of the first transistor M1 is connected to the first clock signal SCK1, the first pole of the first transistor M1 is connected to the input signal SIN, and the second pole of the first transistor M1 is electrically connected to the first control terminal N1. In the first input unit 11, the first clock signal SCK1 can control the on and off of the first transistor M1 to control whether the input signal SIN is written into the first control terminal N1.

[0078] The potential control unit 12 includes: a second transistor M2; the gate of the second transistor M2 is connected to the first clock signal SCK1, the first pole of the second transistor M2 is connected to the first potential signal VGL, and the second pole of the second transistor M2 is electrically connected to the second control terminal N2. In the potential control unit 12, the first clock signal SCK1 can control the on and off of the second transistor M2 to control whether the first potential signal VGL is written into the second control terminal N2.

[0079] The first node mutual control unit 13 includes: a third transistor M3; the gate of the third transistor M3 is connected to the first control terminal N1, the first pole of the third transistor M3 is connected to the first clock signal SCK1, and the second pole of the third transistor M3 is electrically connected to the second control terminal N2. In the first node mutual control unit 13, the potential of the first control terminal N1 can control the on and off of the third transistor M3 to control whether the first clock signal SCK1 is transmitted to the second control terminal N2.

[0080] The second node mutual control unit 14 includes: a fourth transistor M4 and a fifth transistor M5; the gate of the fourth transistor M4 is electrically connected to the second control terminal N2, the first pole of the fourth transistor M4 accesses the second potential signal VGH, and the second pole of the fourth transistor M4 is electrically connected to the first pole of the fifth transistor M5; the gate of the fifth transistor M5 accesses the second clock signal SCK2, and the second pole of the fifth transistor M5 is electrically connected to the first control terminal N1. In the second node mutual control unit 14, the potential of the second control terminal N2 controls the on and off of the fourth transistor M4, and the second clock signal SCK2 controls the on and off of the fifth transistor M5; when both the fourth transistor M4 and the fifth transistor M5 are turned on, the second potential signal VGH can be transmitted to the first control terminal N1.

[0081] Continue to refer to Figure 4 , in an implementation manner, optionally, the first output unit 21 includes: a tenth transistor M10 and a second capacitor C2. The gate of the tenth transistor M10 serves as the first control terminal N1 and is electrically connected to the first end of the second capacitor C2; the first pole of the tenth transistor M10 accesses the second clock signal SCK2; the second pole of the tenth transistor M10 is electrically connected to the second end of the second capacitor C2 and serves as the output terminal of the first output unit 21. Among them, the potential of the first control terminal N1 controls whether the tenth transistor M10 is turned on, so as to control whether the second clock signal SCK2 is output as the first scan signal Vout1; the second capacitor C2 is used to stabilize the gate potential of the tenth transistor M10 and perform coupling control on the potential of the second pole of the tenth transistor M10.

[0082] Furthermore, the first output unit 21 may further include: a twelfth transistor M12; the gate of the twelfth transistor M12 accesses the first potential signal VGL, the first pole of the twelfth transistor M12 serves as the first control terminal N1, and the second pole (node N6) of the twelfth transistor M12 is electrically connected to the gate of the tenth transistor M10. In this embodiment, the first pole and the second pole of the twelfth transistor M12 are respectively connected to the first control terminal N1 and the gate of the tenth transistor M10, which can reduce the large cross-voltage existing between the node N6 and the first control terminal N1 when the potential of the first control terminal N1 jumps, and increase the circuit reliability.

[0083] The second output unit 22 includes: an eleventh transistor M11 and a third capacitor C3. The gate of the eleventh transistor M11 serves as the second control terminal N2 and is electrically connected to the first end of the third capacitor C3; the first pole of the eleventh transistor M11 is connected to the second potential signal VGH and is electrically connected to the second end of the third capacitor C3; the second pole of the eleventh transistor M11 serves as the output terminal of the second output unit 22. Among them, the potential of the second control terminal N2 controls whether the eleventh transistor M11 is turned on, so as to control whether the second potential signal VHG is output as the first scan signal Vout1; the third capacitor C3 is used to stabilize the gate potential of the eleventh transistor M11.

[0084] In summary, the embodiment of the present invention provides a specific structure of the first control module 10 and the first output module 20, which can realize the shift output of the input signal SIN, and has a simple circuit structure, is easy to implement, and has good stability of the output signal.

[0085] Continue to refer to Figure 4 , in an implementation manner, optionally, the second input unit 31 includes: an eighth transistor M8; the gate of the eighth transistor M8 is connected to the second clock signal SCK2, the first pole of the eighth transistor M8 is electrically connected to the second control terminal N2, and the second pole of the eighth transistor M8 is electrically connected to the fourth control terminal N4. In the second input unit 31, the second clock signal SCK2 can control the on and off of the eighth transistor M8 to control whether the potential of the second control terminal N2 is written into the fourth control terminal N4.

[0086] The third node mutual control unit 33 includes: a ninth transistor M9; the gate of the ninth transistor M9 is electrically connected to the third control terminal N3, the first pole of the ninth transistor M9 is connected to the second potential signal VGH, and the second pole of the ninth transistor M9 is electrically connected to the fourth control terminal N4. In the third node mutual control unit 33, the potential of the third control terminal N3 can control the on and off of the ninth transistor M9 to control whether the potential of the third control terminal N3 is written into the fourth control terminal N4.

[0087] The coupling sub-unit 323 includes: a first capacitor C1; the first end of the first capacitor C1 serves as the first end of the coupling sub-unit 323, and the second end of the first capacitor C1 serves as the second end of the coupling sub-unit 323. In the embodiment of the present invention, the storage of the potential of the fourth control terminal N4 can be realized through the first capacitor C1, and the voltage coupling effect on the fourth control terminal N4 through the node N5 can be achieved.

[0088] The first switching sub-unit 321 includes: a sixth transistor M6; the gate of the sixth transistor M6 serves as the control terminal of the first switching sub-unit 321, the first pole of the sixth transistor M6 serves as the input terminal of the first switching sub-unit 321, and the second pole of the sixth transistor M6 serves as the output terminal of the first switching sub-unit 321. The potential of the first control terminal N1 can control whether the sixth transistor M6 is turned on, so as to control whether the second potential signal VGH is transmitted to the node N5, realize the control of the potential of the node N5, so as to realize the charging and discharging of the first capacitor C1, and utilize the coupling effect of the first capacitor C1 to couple and control the potential of the fourth control terminal N4 by controlling the potential of the node N5.

[0089] The second switching sub-unit 322 includes: a seventh transistor M7; the gate of the seventh transistor M7 serves as the control terminal of the second switching sub-unit 322, the first pole of the seventh transistor M7 serves as the input terminal of the second switching sub-unit 322, and the second pole of the seventh transistor M7 serves as the output terminal of the second switching sub-unit 322. Similar to the operation process of the sixth transistor M6, in the embodiment of the present invention, the conduction and cutoff of the seventh transistor M7 are controlled by the potential of the fourth control terminal N4, so as to control the potential of the node N5. Similarly, the charging and discharging of the first capacitor C1 can be realized, and the coupling effect of the first capacitor C1 is utilized to couple and control the potential of the fourth control terminal N4 by controlling the potential of the node N5.

[0090] Continue to refer to Figure 4 , in an embodiment, optionally, the third output unit 41 includes: a thirteenth transistor M13 and a fourth capacitor C4. The gate of the thirteenth transistor M13 serves as the third control terminal N3 and is electrically connected to the first end of the fourth capacitor C4; the first pole of the thirteenth transistor M13 is connected to the second potential signal VGH and is electrically connected to the second end of the fourth capacitor C4; the second pole of the thirteenth transistor M13 serves as the output terminal of the third output unit 41; wherein, the third control terminal N3 is actually directly electrically connected to the first control terminal N1, and its potential is the same as the potential of the first control terminal N1. The potential of the third control terminal N3 controls whether the thirteenth transistor M13 is turned on, so as to control whether the second potential signal VHG is output as the second scan signal Vout2; the fourth capacitor C4 is used to stabilize the gate potential of the thirteenth transistor M13.

[0091] The fourth output unit 42 includes: a fourteenth transistor M14. The gate of the fourteenth transistor M14 serves as the fourth control terminal N4, the first pole of the fourteenth transistor M14 is connected to the first potential signal VGL, and the second pole of the fourteenth transistor M14 serves as the output terminal of the fourth output unit 42. Wherein, the potential of the fourth control terminal N4 controls whether the fourteenth transistor M14 is turned on, so as to control whether the first potential signal VHL is output as the second scan signal Vout2.

[0092] In summary, the embodiments of the present invention provide the specific structures of the second control module 30 and the second output module 40, achieving the effect of outputting the second scan signal Vout2 based on the potentials of the first control terminal N1 and the second control terminal N2, and the stability of the output second scan signal Vout2 is relatively good.

[0093] The working process of the gate driving circuit will be described below in combination with specific timings. Figure 5 FIG. is a schematic diagram of the driving timing of a gate driving circuit provided by an embodiment of the present invention. Taking the case where each transistor in the gate driving circuit is a P-type transistor, the first potential signal VGL is a low potential, and the second potential signal VGH is a high potential as an example. The first clock signal SCK1 and the second clock signal SCK2 alternately output high and low potentials. Among them, the high potential of the first clock signal SCK1 and the second clock signal SCK2 can be the same high potential as the second potential signal VGH, and the low potential of the first clock signal SCK1 and the second clock signal SCK2 can be the same low potential as the first potential signal VGL. Combining Figure 4 and Figure 5 , the driving process of the gate driving circuit includes:

[0094] First stage T11: The input signal SIN and the first clock signal SCK1 are at low potential, and the second clock signal SCK2 is at high potential. The first transistor M1 is turned on, transmitting the low potential of the input signal SIN to the first control terminal N1; the twelfth transistor M12 is turned on, transmitting the low potential of the first control terminal N1 to the node N6, controlling the tenth transistor M10 to be turned on, and transmitting the high potential of the second clock signal SCK2 to the output terminal of the first output module 20. The third transistor M3 is turned on, transmitting the low potential of the first clock signal SCK1 to the second control terminal N2, and, the second transistor M2 is turned on, transmitting the first potential signal VGL to the second control terminal N2. The low potential of the second control terminal N2 controls the eleventh transistor M11 to be turned on, transmitting the second potential signal VGH to the output terminal of the first output module 20. Since the second potential signal VGH is at high potential and the second clock signal SCK2 is at high potential at this stage, the first scan signal Vout1 is at high potential at this stage. At the same time, the low potential of the first control terminal N1 controls the sixth transistor M6 and the ninth transistor M9 to be turned on; the second potential signal VGH is transmitted to the node N5 through the sixth transistor M6; and, the second potential signal VGH is transmitted to the fourth control terminal N4 through the ninth transistor M9, controlling the fourteenth transistor M14 to be turned off. The third control terminal N3 is at the same low potential as the first control terminal N1, controlling the thirteenth transistor M13 to be turned on, transmitting the second potential signal VGH to the output terminal of the second output module 20, so the second scan signal Vout2 is at high potential. Therefore, at this stage, the potentials of each key node in the gate driving circuit and the two scan signals are as follows: VN1 = VN2 = VN3 = VN6 = VGL - Vth, VN4 = VN5 = VGH, Vout1 = Vout2 = VGH, where each transistor in the gate driving circuit is a transistor with the same characteristics, and Vth is the threshold voltage of any transistor.

[0095] Second stage T12: The input signal SIN and the first clock signal SCK1 are at high potential, and the second clock signal SCK2 is at low potential. The potential of the first control terminal N1 maintains the low potential of the previous stage; the third transistor M3 is turned on, transmitting the high potential of the first clock signal SCK1 to the second control terminal N2, controlling the eleventh transistor M11 to turn off; the twelfth transistor M12 is turned on, the node N6 is at low potential, controlling the tenth transistor M10 to turn on, and outputting the low potential of the second clock signal SCK2 as the first scan signal Vout1. At the same time, the first scan signal Vout1 jumps from high potential to low potential, and under the coupling action of the second capacitor C2, the node N6 jumps to a lower potential. Similar to the previous stage, the low potential of the first control terminal N1 still controls the sixth transistor M6, the ninth transistor M9, and the thirteenth transistor M13 to be all turned on, and the second potential signal VGH is transmitted to the output terminal of the second output module 40 through the thirteenth transistor M13. At the same time, the low potential of the second clock signal SCK2 controls the eighth transistor M8 to turn on, transmitting the high potential of the second control terminal N2 to the fourth control terminal N4; at this time, the fourth control terminal N4 is at high potential, controlling the fourteenth transistor M14 to turn off. Therefore, in this stage, the potentials of the key nodes in the gate driving circuit and the two scan signals are as follows: VN1 = VN3 = VGL - vth, VN2 = VN4 = VN5 = VGH, VN6 = VLOW, Vout1 = VGL, Vout2 = VGH, where VLOW represents a potential lower than VGL - vth.

[0096] Third stage T13: The input signal SIN and the second clock signal SCK2 are both at high potential, and the first clock signal SCK1 is at low potential. The first transistor M1 is turned on, transmitting the high potential of the input signal SIN to the first control terminal N1; the twelfth transistor M12 is turned on, transmitting the high potential of the first control terminal N1 to the node N6, controlling the tenth transistor M10 to turn off. The second transistor M2 is turned on, transmitting the low potential of the first potential signal VGL to the second control terminal N2, controlling the eleventh transistor M11 to turn on, and outputting the second potential signal VGH as the first scan signal Vout1. At the same time, the high potential of the first control terminal N1 controls the sixth transistor M6 and the ninth transistor M9 to turn off, and the third control terminal N3 has the same high potential as the first control terminal N1; also, the second clock signal SCK2 controls the eighth transistor M8 to turn off, and the fourth control terminal N4 and the node N5 both maintain the high potential of the previous stage. At this time, both the fourteenth transistor M14 and the thirteenth transistor M13 are turned off, and the second scan signal Vout2 maintains the high potential of the previous stage. Therefore, in this stage, the potentials of the key nodes in the gate driving circuit and the two scan signals are as follows: VN2 = VGL - Vth, VN1 = VN3 = VN4 = VN5 = VN6 = VGH, Vout1 = Vout2 = VGH.

[0097] Fourth stage T14: The input signal SIN and the first clock signal SCK1 are at high potential, and the second clock signal SCK2 is at low potential. The potential of the second control terminal N2 maintains the low potential of the previous stage. The low potential of the second control terminal N2 controls the fourth transistor M4 to conduct, and the low potential of the second clock signal SCK2 controls the fifth transistor M5 to conduct. The second potential signal VGH is transmitted to the first control terminal N1 through the fourth transistor M4 and the fifth transistor M5. The low potential of the second control terminal N2 controls the eleventh transistor M11 to conduct, and the second potential signal VGH is output as the first scan signal Vout1. The high potential of the first control terminal N1 controls the sixth transistor M6 and the ninth transistor M9 to turn off. The third control terminal N3 has the same high potential as the first control terminal N1, controlling the thirteenth transistor M13 to turn off. The low potential of the second clock signal SCK2 controls the eighth transistor M8 to conduct, transmitting the low potential of the second control terminal N2 to the fourth control terminal N4, controlling the seventh transistor M7 to conduct, and transmitting the high potential of the first clock signal SCK1 to the node N5. Since the second scan signal Vout2 was at high potential in the previous stage, the second pole of the fourteenth transistor M14 is equivalent to its source. Therefore, in this stage, when the potential of the second scan signal Vout2 drops to the gate-source voltage difference of the fourteenth transistor M14 equal to its threshold voltage, that is, VN4 - Vout2 = Vth, the fourteenth transistor M14 turns off. Therefore, in this stage, the potentials of the key nodes in the gate driving circuit and the two scan signals are as follows: VN2 = VN4 = VGL - Vth, VN1 = VN3 = VN5 = VN6 = VGH, Vout1 = VGH, Vout2 = VGL - 2Vth.

[0098] Fifth stage T15: The input signal SIN and the second clock signal SCK2 are both at high potential, and the first clock signal SCK1 is at low potential. The operation processes of the first control module 10 and the first output module 20 are the same as those in the third stage T3 and will not be elaborated here. Meanwhile, the high potential at the first control terminal N1 controls the sixth transistor M6 and the ninth transistor M9 to turn off. The third control terminal N3 is at the same high potential as the first control terminal N1, controlling the thirteenth transistor M13 to turn off. The second clock signal SCK2 controls the eighth transistor M8 to turn off. The potential at the second control terminal N2 does not affect the potential at the fourth control terminal N4. The fourth control terminal N4 maintains the low potential of the previous stage when entering the fifth stage T15, controlling the seventh transistor M7 to conduct, and transmitting the low potential of the first clock signal to the node N5. That is to say, the potential at the node N5 jumps from the high potential of the previous stage to the low potential of this stage. Through the coupling effect of the first capacitor C1, the fourth control terminal N4 is coupled to a lower potential, making the fourteenth transistor M14 more fully open than in the previous stage, and outputting the first potential signal VGL as the second scan signal Vout2. Therefore, in this stage, the potentials of the key nodes in the gate driving circuit and the two scan signals are as follows: VN2 = VGL - vth, VN4 = VLOW, VN5 = VGL, VN1 = VN3 = VN6 = VGH, Vout1 = VGH, Vout2 = VGL.

[0099] Sixth stage T16: The input signal SIN and the first clock signal SCK1 are at high potential, and the second clock signal SCK2 is at low potential. The operation processes of the first control module 10 and the first output module 20 are the same as those in the fourth stage T4 and will not be elaborated here. The high potential at the first control terminal N1 controls the sixth transistor M6 and the ninth transistor M9 to turn off. The third control terminal N3 is at the same high potential as the first control terminal N1, controlling the thirteenth transistor M13 to turn off. The low potential of the second clock signal SCK2 controls the eighth transistor M8 to conduct, transmitting the low potential of the second control terminal N2 to the fourth control terminal N4, controlling the seventh transistor M7 and the fourteenth transistor M14 to conduct, and transmitting the high potential of the first clock signal SCK1 to the node N5, charging the first capacitor C1 again. The first potential signal VGL is output as the second scan signal Vout2 through the fourteenth transistor M14. Therefore, in this stage, the potentials of the key nodes in the gate driving circuit and the two scan signals are as follows: VN1 = VN3 = VN5 = VN6 = VGH, VN2 = VN4 = VGL - vth, Vout1 = VGH, Vout2 = VGL.

[0100] The subsequent stages repeat the fifth stage T15 and the sixth stage T16 until the input signal SIN jumps to low potential again.

[0101] In summary, in the gate driving circuit, the first control module 10 and the first output module 20 cooperate to achieve the shifted output of the input signal SIN; the first control module 10, the second control module 30 and the second output module 40 cooperate to make the low voltage phase of the first scan signal Vout1 fall within the phase where the second output signal Vout2 outputs a high potential during the first stage T11 to the fourth stage T14. After the fourth stage T14, the first scan signal Vout1 continuously outputs a high potential, and the second output signal Vout2 continuously outputs a low potential, meeting the driving requirements of the LTPO pixel circuit in the screen body. Moreover, in each stage after the fourth stage T14, the seventh transistor M7 in the coupling module repeatedly charges the first pole of the first capacitor C1 with a high potential and provides a low potential, causing the first capacitor C1 to continuously couple, ensuring that the potential of the fourth control terminal N4 is relatively low, and further ensuring that the second output signal Vout2 can continuously output a low potential.

[0102] Therefore, the gate driving circuit adopts a 14T4C architecture and requires three control signals, namely the input signal SIN, the first clock signal SCK1, and the second clock signal SCK2. By means of sharing voltage nodes within the circuit, it can achieve the simultaneous output of high and low potentials with different pulse widths, meeting the driving requirements of the pixel circuit. Compared with the existing combination structures such as 20T3C and the six control signals required in the industry, the layout space and signals required by the embodiments of the present invention are less, which can ensure the reliability of the two scan signals output, and is conducive to achieving the requirements of a narrow border and low power consumption of the screen body.

[0103] To further explain the action mode of the scan signal output by the gate driving circuit provided by the embodiments of the present invention, the following will be described in conjunction with the driving process of the pixel circuit. Figure 6 It is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. Figure 6 A pixel circuit with a 7T1C architecture is given. The pixel circuit includes: a driving transistor DTFT, a first initialization module 110, a second initialization module 120, a data writing module 130, a light emission control module 140, and a storage module 150.

[0104] Among them, the first initialization module 110 includes: a transistor M22; the gate of the transistor M22 is connected to a first gate control signal Scan1, the first pole is connected to an initialization voltage signal Vref, and the second pole is electrically connected to the gate of the driving transistor DTFT. The second initialization module 120 includes: a transistor M23; the gate of the transistor M23 is connected to the first gate control signal Scan1, the first pole is connected to the initialization voltage signal Vref, and the second pole is electrically connected to the anode of the light-emitting device OLED. The data writing module 130 includes: a transistor M24 and a transistor M25; the gate of the transistor M24 is connected to a second gate control signal Scan2, the first pole is connected to a data signal Vdata, and the second pole is electrically connected to the first pole of the driving transistor DTFT; the gate of the transistor M25 is connected to the second gate control signal Scan2, the first pole is electrically connected to the second pole of the driving transistor DTFT, and the second pole is electrically connected to the gate of the driving transistor DTFT. The light-emitting control module 140 includes: a transistor M26 and a transistor M27; the gate of the transistor M26 is connected to a light-emitting control signal EM, the first pole is connected to a first power supply signal VDD, and the second pole is electrically connected to the first pole of the driving transistor DTFT; the gate of the transistor M27 is connected to the light-emitting control signal EM, the first pole is electrically connected to the second pole of the driving transistor DTFT, and the second pole is electrically connected to the anode of the light-emitting device OLED. The cathode of the light-emitting device OLED is connected to a second power supply signal VSS. The storage module 150 includes: a capacitor C5; the first end of the capacitor C5 is connected to the first power supply signal VDD, and the second end is electrically connected to the gate of the driving transistor DTFT.

[0105] Figure 7 It is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention. Combining Figure 6 and Figure 7 , taking each transistor in the pixel circuit as a P-type transistor and the gate being connected to a low potential to conduct as an example, the driving process of the pixel circuit includes:

[0106] Initialization stage T21: The first gate control signal Scan1 is at a low potential, and the second gate control signal Scan2 and the light-emitting control signal EM are at a high potential. Both the transistor M22 and the transistor M23 are turned on, and the initialization voltage signal Vref is transmitted to the gate of the driving transistor DTFT through the transistor M22 to initialize the gate of the driving transistor DTFT; and, the initialization voltage signal Vref is transmitted to the anode of the light-emitting device OLED through the transistor M23 to initialize the anode of the light-emitting device OLED.

[0107] Data writing stage T22: The second gate control signal Scan2 is at a low potential, and the first gate control signal Scan1 and the emission control signal EM are both at a high potential. Transistors M24 and M25 are both turned on. The data signal Vdata is transmitted through transistors M24, the driving transistor DTFT, and transistor M25 to the gate of the driving transistor DTFT.

[0108] Emission stage T23: The emission control signal EM is at a low potential, and the first gate control signal Scan1 and the second gate control signal Scan2 are both at a high potential. Transistors M26 and M27 are both turned on. The first power supply signal VDD is applied to the first pole of the driving transistor DTFT through transistor M26, so that the driving transistor DTFT generates a driving current according to the first power supply signal VDD and the gate potential written in the previous stage. The driving current flows into the light-emitting device OLED through transistor M27 to drive the light-emitting device OLED to emit light.

[0109] Exemplarily, multiple pixel circuits are arranged in an array in the display area of the display panel, and a cascaded gate driving circuit corresponding to each row of pixel circuits can be arranged in the non-display area of the display panel. Then, the first scan signal output by the nth-stage gate driving circuit can be used as the first gate control signal of the nth row of pixel circuits and as the second gate control signal of the (n - 1)th row of pixel circuits; and the second scan signal output by the nth-stage gate driving circuit can be used as the emission control signal of the nth row of pixel circuits. Or, the first scan signal of the (n - 1)th stage can be used as the first gate control signal of the nth row of pixel circuits, the first scan signal of the nth stage can be used as the second gate control signal of the nth row of pixel circuits, and the second scan signal of the nth stage can be used as the emission control signal of the nth row of pixel circuits.

[0110] It should be noted that for each transistor involved in the above embodiments, its first pole can be called the source or the drain. Correspondingly, its second pole can be called the drain or the source. Since the structure of the transistor in the display panel is symmetric, the source and drain of each transistor are not distinguished.

[0111] It should also be noted that in the above embodiments, it is exemplarily shown that each transistor in the gate driving circuit is a P-type transistor, which is not a limitation of the present invention. In other embodiments, some transistors or all transistors can also be set as N-type transistors according to needs, and the high and low potentials of their control signals are correspondingly changed.

[0112] The embodiment of the present invention also provides a display panel, including cascaded multi-stage gate driving circuits as provided in any embodiment of the present invention, and having corresponding beneficial effects. Figure 8 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 8, Exemplarily, the display panel can be a display panel of types such as an organic light-emitting diode display panel or a micro light-emitting diode display panel. The gate driving circuit can adopt a single-ended driving structure as shown in Figure 8 , or a double-ended driving structure, which is not limited herein. The display panel may further include a plurality of pixel circuits (not shown in the figure). The gate driving circuit 100 is used to provide the required gate driving signals to each pixel circuit; the pixel circuits can be arranged in an array in the display area 81 of the display panel, and the gate driving circuit 100 can be cascade-connected in the non-display area 82 of the display panel, and one row of pixel circuits can correspond to one stage of the gate driving circuit 100. Figure 8 , Exemplarily, in the direction from bottom to top are the first stage to the last stage of the gate driving circuit 100. The cascade connection of each stage of the gate driving circuit 100 means that the first scan signal Vout1 output by the previous stage of the gate driving circuit is used as the input signal of the next stage of the gate driving circuit, so as to realize the shift output of the first scan signal Vout1 and the second scan signal Vout2 of each stage.

[0113] Continuing to refer to Figure 8 , On the basis of the above embodiments, optionally, the display panel further includes: a first potential signal line 71, a second potential signal line 72, an input signal line 73, a first clock signal line 74, a second clock signal line 75, a scan signal line 50, and a light emission control signal line 60. The first potential signal line 21 is used to provide a first potential signal, the second potential signal line 22 is used to provide a second potential signal, the scan signal line 50 is used to transmit the first scan signal Vout1 to the pixel circuit, and the light emission control signal line 60 is used to transmit the second scan signal Vout2 (light emission control signal) to the pixel circuit.

[0114] Each stage of the gate driving circuit 100 is electrically connected to the first potential signal line 71 and the second potential signal line 72. The first-stage gate driving circuit 100 is electrically connected to the input signal line 73; the first scan signal Vout1 output by each stage of the gate driving circuit 100 is used as the input signal of the next stage of the gate driving circuit 100. Each stage of the gate driving circuit 100 is alternately connected to the first clock signal line 74 and the second clock signal line 75. Specifically, the signal transmitted by the first clock signal line 74 is used as the first clock signal of the (2n - 1)-th stage of the gate driving circuit 100, and the signal transmitted by the second clock signal line 75 is used as the second clock signal of the (2n - 1)-th stage of the gate driving circuit 100; and, the signal transmitted by the first clock signal line 74 is used as the second clock signal of the 2n-th stage of the gate driving circuit 100, and the signal transmitted by the second clock signal line 75 is used as the first clock signal of the 2n-th stage of the gate driving circuit 100; where n is a positive integer. One stage of the gate driving circuit 100 is correspondingly connected to one scan signal line 50 and correspondingly connected to one light emission control signal line 60.

[0115] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A gate driving circuit, characterized in that, Comprising: A first control module and a first output module. The first output module includes a first control end and a second control end. The first control module is respectively connected to the first control end and the second control end. The first control module is used to control the potentials of the first control end and the second control end. The first output module is used to output a first scan signal according to the potentials of the first control end and the second control end; A second control module and a second output module. The second control module is respectively connected to the first control end and the second control end. The second output module includes a third control end and a fourth control end. The third control end and the fourth control end of the second output module are respectively connected to the second control module. The second control module controls the potentials of the third control end and the fourth control end based on the potentials of the first control end and the second control end. The second output module is used to output a second scan signal according to the potentials of the third control end and the fourth control end; The second control module includes: a coupling unit, which is respectively electrically connected to the first control end and the fourth control end; the coupling unit is used to respond to a first clock signal, a second potential signal, the potential of the first control end, and the potential of the fourth control end, and perform coupling control on the potential of the fourth control end; The coupling unit includes: a coupling sub-unit, a first switch sub-unit, and a second switch sub-unit; The control end of the first switch sub-unit is electrically connected to the first control end. The input end of the first switch sub-unit accesses the second potential signal. The output end of the first switch sub-unit is electrically connected to the first end of the coupling sub-unit; The control end of the second switch sub-unit is electrically connected to the fourth control end. The input end of the second switch sub-unit accesses the first clock signal. The output end of the second switch sub-unit is electrically connected to the first end of the coupling sub-unit; The second end of the coupling sub-unit is electrically connected to the fourth control end; Wherein, the pulse width of the second scan signal is greater than the pulse width of the first scan signal.

2. The gate driving circuit according to claim 1, wherein The first control module includes: A first input unit, which is electrically connected to the first control end; the first input unit is used to respond to the first clock signal and transmit an input signal to the first control end; A potential control unit, which is electrically connected to the second control end; the potential control unit is used to respond to the first clock signal and transmit a first potential signal to the second control end; A first node mutual control unit, which is respectively electrically connected to the first control end and the second control end; the first node mutual control unit is used to respond to the potential of the first control end and transmit the first clock signal to the second control end; A second node mutual control unit, which is respectively electrically connected to the first control end and the second control end; the second node mutual control unit is used to respond to a second clock signal and the potential of the second control end and transmit a second potential signal to the first control end.

3. The gate driving circuit according to claim 2, wherein The first input unit includes: a first transistor; a gate of the first transistor is connected to the first clock signal, a first pole of the first transistor is connected to the input signal, and a second pole of the first transistor is electrically connected to the first control end; And / or, the potential control unit includes: a second transistor; a gate of the second transistor is connected to the first clock signal, a first pole of the second transistor is connected to the first potential signal, and a second pole of the second transistor is electrically connected to the second control end; And / or, the first node mutual control unit includes: a third transistor; a gate of the third transistor is electrically connected to the first control end, a first pole of the third transistor is connected to the first clock signal, and a second pole of the third transistor is electrically connected to the second control end; And / or, the second node mutual control unit includes: a fourth transistor and a fifth transistor; a gate of the fourth transistor is electrically connected to the second control end, a first pole of the fourth transistor is connected to the second potential signal, and a second pole of the fourth transistor is electrically connected to a first pole of the fifth transistor; a gate of the fifth transistor is connected to the second clock signal, and a second pole of the fifth transistor is electrically connected to the first control end.

4. The gate driving circuit according to claim 1, wherein The second control module includes: A second input unit, which is electrically connected to the second control end and the fourth control end respectively; the second input unit is configured to respond to the second clock signal and transmit the potential of the second control end to the fourth control end; A third node mutual control unit, which is electrically connected to the third control end and the fourth control end respectively; the third node mutual control unit is configured to respond to the potential of the third control end and transmit the second potential signal to the fourth control end.

5. The gate driving circuit according to claim 1, wherein The coupling sub-unit includes: a first capacitor; a first end of the first capacitor serves as a first end of the coupling sub-unit, and a second end of the first capacitor serves as a second end of the coupling sub-unit; The first switch sub-unit includes: a sixth transistor; a gate of the sixth transistor serves as a control end of the first switch sub-unit, a first pole of the sixth transistor serves as an input end of the first switch sub-unit, and a second pole of the sixth transistor serves as an output end of the first switch sub-unit; The second switch sub-unit includes: a seventh transistor; a gate of the seventh transistor serves as a control end of the second switch sub-unit, a first pole of the seventh transistor serves as an input end of the second switch sub-unit, and a second pole of the seventh transistor serves as an output end of the second switch sub-unit.

6. The gate driving circuit according to claim 4, wherein The second input unit includes: an eighth transistor; a gate of the eighth transistor is connected to the second clock signal, a first pole of the eighth transistor is electrically connected to the second control end, and a second pole of the eighth transistor is electrically connected to the fourth control end; And / or, the third node mutual control unit includes: a ninth transistor; a gate of the ninth transistor is electrically connected to the third control end, a first pole of the ninth transistor is connected to the second potential signal, and a second pole of the ninth transistor is electrically connected to the fourth control end.

7. The gate driving circuit according to claim 1, wherein The first output module includes: A first output unit, the control terminal of the first output unit serving as the first control terminal, the input terminal of the first output unit being connected to a second clock signal, and the output terminal of the first output unit serving as the output terminal of the first output module; A second output unit, the control terminal of the second output unit serving as the second control terminal, the input terminal of the second output unit being connected to a second potential signal, and the output terminal of the second output unit being electrically connected to the output terminal of the first output unit.

8. The gate driving circuit according to claim 7, wherein The first output unit includes: a tenth transistor and a second capacitor; the gate of the tenth transistor serves as the first control terminal and is electrically connected to the first terminal of the second capacitor; the first pole of the tenth transistor serves as the input terminal of the first output unit; the second pole of the tenth transistor serves as the output terminal of the first output unit and is electrically connected to the second terminal of the second capacitor; The second output unit includes: an eleventh transistor and a third capacitor; the gate of the eleventh transistor serves as the second control terminal and is electrically connected to the first terminal of the third capacitor; the first pole of the eleventh transistor serves as the input terminal of the second output unit and is electrically connected to the second terminal of the third capacitor; the second pole of the eleventh transistor serves as the output terminal of the second output unit.

9. The gate driving circuit according to claim 8, wherein The first output unit further includes: a twelfth transistor; the gate of the twelfth transistor is connected to a first potential signal, the first pole of the twelfth transistor serves as the first control terminal, and the second pole of the twelfth transistor is electrically connected to the gate of the tenth transistor.

10. The gate driving circuit according to claim 1, characterized in that, The second output module includes: A third output unit, the control terminal of the third output unit serving as the third control terminal, the input terminal of the third output unit being connected to a second potential signal, and the output terminal of the third output unit serving as the output terminal of the second output module; A fourth output unit, the control terminal of the fourth output unit serving as the fourth control terminal, the input terminal of the fourth output unit being connected to a first potential signal, and the output terminal of the fourth output unit being electrically connected to the output terminal of the third output unit.

11. The gate driving circuit according to claim 10, characterized in that, The third output unit includes: a thirteenth transistor and a fourth capacitor; the gate of the thirteenth transistor serves as the third control terminal and is electrically connected to the first terminal of the fourth capacitor; the first pole of the thirteenth transistor serves as the input terminal of the third output unit and is electrically connected to the second terminal of the fourth capacitor; the second pole of the thirteenth transistor serves as the output terminal of the third output unit; The fourth output unit includes: a fourteenth transistor; the gate of the fourteenth transistor serves as the fourth control terminal, the first pole of the fourteenth transistor serves as the input terminal of the fourth output unit, and the second pole of the fourteenth transistor serves as the output terminal of the fourth output unit.

12. A display panel, characterized in that, It includes: The gate driving circuit according to any one of claims 1-11.

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