A kind of injection error test method, device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose an error injection test method and device, electronic equipment and medium. The method comprises: obtaining a test bit corresponding to a to-be-tested storage unit, and writing target data into the to-be-tested storage unit according to the test bit, wherein the test bit is determined based on a position of an interrupt domain corresponding to the to-be-tested storage unit in an interrupt register; reading the target data stored by the to-be-tested storage unit according to the test bit, and determining an error injection data source according to the target data; performing a read operation on the to-be-tested storage unit again according to the test bit, and replacing the read result with the error injection data source to perform error injection on the storage unit. In this embodiment, the target data at the test bit in the to-be-tested unit is read, the error injection data source is generated based on the target data, the test bit is read again, and the read result is replaced with the error injection source data, so as to trigger an ECC check error, complete error injection, and improve error injection efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and more particularly to an error injection testing method, apparatus, electronic device, and storage medium. Background Technology

[0002] RAM (Random Access Memory) is susceptible to certain soft failures or device malfunctions, which are errors caused by physical layer factors.

[0003] In existing technologies, verification is mainly carried out through EDA (Electronic Design Automation) simulation, which mainly involves two methods: one is to directly modify specific data in RAM to achieve the testing purpose. This testing method requires knowledge of the precise arrangement of data in RAM, which is difficult to control; the other is to perform error injection testing by manipulating data on the RAM interface. This method is relatively easy to control but lacks a systematic and universal testing method.

[0004] Therefore, how to provide a simpler method for RAM error verification has become an urgent problem to be solved. Summary of the Invention

[0005] This invention provides an error injection testing method, apparatus, electronic device, and storage medium to solve the technical problem of high difficulty in verifying RAM in the prior art.

[0006] According to one aspect of the present invention, an error testing method is provided, comprising:

[0007] Obtain the test bit corresponding to the memory cell to be tested, and write target data to the memory cell to be tested according to the test bit, wherein the test bit is determined based on the position of the interrupt field corresponding to the memory cell to be tested in the interrupt register;

[0008] Read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data;

[0009] Based on the test bit, a read operation is performed again on the storage unit to be tested, and the storage unit is injected with errors by replacing the read result with the error-injection data source.

[0010] According to another aspect of the present invention, an error testing apparatus is provided, comprising:

[0011] The data writing module is used to obtain the test bit corresponding to the storage unit to be tested, and write target data to the storage unit to be tested according to the test bit. The test bit is determined based on the position of the interrupt field corresponding to the storage unit to be tested in the interrupt register.

[0012] The data source determination module is used to read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data.

[0013] The error injection module is used to perform a read operation on the storage unit to be tested again according to the test bit, and to inject errors into the storage unit by replacing the read result with the error injection data source.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform an error-checking method according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement an error-injection testing method according to any embodiment of the present invention.

[0019] The technical solution of this invention provides a convenient and accurate way to generate 2-bit data errors in a storage unit by reading the target data at the test bit in the unit to be tested, generating an error injection data source based on the target data, reading the test bit again, and replacing the reading result with the error injection source data.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for injecting error data according to Embodiment 1 of the present invention;

[0023] Figure 2 This is a flowchart of a data injection method applicable to Embodiment 2 of the present invention;

[0024] Figure 3 This is a flowchart of a data annotation method applicable to Embodiment 3 of the present invention.

[0025] Figure 4 This is a schematic diagram of the structure of an error-injection data device according to Embodiment 4 of the present invention;

[0026] Figure 5 This is a schematic diagram of the structure of an electronic device that implements a data injection method according to Embodiment 5 of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products or devices.

[0029] Example 1

[0030] Figure 1The flowchart below provides an injection error testing method according to Embodiment 1 of the present invention. This embodiment is applicable to the situation of verifying RAM injection errors. The method can be executed by an injection error testing device, which can be implemented in hardware and / or software, and can be integrated into an electronic device. Figure 1 As shown, the method includes:

[0031] S110. Obtain the test bit corresponding to the memory unit to be tested, and write target data to the memory unit to be tested according to the test bit. The test bit is determined based on the address of the interrupt field corresponding to the memory unit to be tested in the interrupt register.

[0032] The storage unit to be tested can be a storage unit inside RAM, used to store program and data components; the memory capacity of the storage unit inside RAM can be represented by bits, for example, the memory capacity can be 1 bit, and 1 bit is also the minimum memory capacity corresponding to the storage unit. This embodiment does not impose a specific limit on the size of the memory capacity, and it can be flexibly set according to the actual situation.

[0033] An interrupt register can be a special register used to store interrupt request information from an interrupt source; an interrupt field can be the address where the interrupt request information is located.

[0034] The test bit can be the bit position of the interrupt field in the interrupt register.

[0035] Different types of RAM can exist within the same interrupt register, and test interfaces for different types of RAM can be predefined. Different test interfaces for different types of RAM can be defined using macros, and different test bits can be passed to the macro methods to implement error injection tests for different test bits.

[0036] It should be noted that there are no specific restrictions on the specific implementation of macro methods. For example, the code A_ram_1rw_ecc_err_gen(1) can represent that the test bit of RAM is 1 bit. Correspondingly, when the code is A_ram_1rw_ecc_err_gen(2), it can represent that the test bit of RAM is 2 bits; when the code is A_ram_1rw_ecc_err_gen(3), it can represent that the test bit of RAM is 3 bits; and so on. When the code is A_ram_1rw_ecc_err_gen(4), it can represent that the test bit of RAM is 4 bits.

[0037] In this embodiment, writing target data to the storage unit under test according to the test bit can be done by writing target data to the storage unit under test according to the position corresponding to the 4 bits when the test bit is 4 bits.

[0038] In this embodiment, target data can be written to the memory cell under test using the force method based on the test bit. This target data can be pre-set data. Then, the bit corresponding to the test bit is released after one clock cycle. Here, force is a simulation instruction.

[0039] S120. Read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data.

[0040] The error data source can be the data that triggers a 2-bit ECC (Error Checking and Correcting) interrupt in RAM.

[0041] In this embodiment, the target data stored in the test storage unit can be read using the force method, and two bits in the target data can be inverted to determine the error injection data source. The specific inversion operation is performed according to a predefined inversion rule. For example, if the target data read is 01101100, then inverting the lower 2 bits yields 01101111. Accordingly, the error injection data source is 01101111.

[0042] S130. Perform a read operation on the storage unit to be tested again based on the test bit, and inject errors into the storage unit by replacing the read result with the error-injecting data source.

[0043] In this embodiment, the read operation on the storage unit to be tested is performed again using the force method according to the test bit. When waiting for the data reading result to be returned, the reading result is replaced with the error-injected data source. At this time, this read operation will generate an ECC check error, thereby triggering an interrupt report, proving that the error injection was successful.

[0044] This embodiment reads the target data at the test bit in the unit under test, generates an error injection data source based on the target data, reads the test bit again, and replaces the reading result with the error injection source data, thereby triggering ECC verification error and completing the error injection. This provides a convenient and accurate way to generate 2-bit data errors in the storage unit.

[0045] Example 2

[0046] Figure 2 This is a flowchart of an error injection testing method provided in Embodiment 2 of the present invention. Before the step "obtaining the test bit corresponding to the memory unit to be tested" in the above embodiments, this embodiment further includes: obtaining register configuration parameters. Terms identical to those in the above embodiments are not repeated here. Figure 2 As shown, the method includes:

[0047] S210. Obtain register configuration parameters through the module test case of the module where the storage unit to be tested is located. The module test case is a test case built in the verification environment through electronic design simulation application.

[0048] The register configuration parameters may include the module name, the configuration interrupt register name, and the number of random tests. These register configuration parameters can be pre-configured as needed; this embodiment does not impose specific restrictions on this.

[0049] In this embodiment, since the chip used for storage contains several modules, and each module contains several memory units to be tested, the register parameters corresponding to different modules may be different. Therefore, it is necessary to set register configuration parameters for the module where the memory unit to be tested is located. Different modules can share a common testing process, requiring only changes to the relevant register parameters. Therefore, all relevant parameters are interfaces reserved in the main test case, facilitating their transfer to the main test case for use and further simplifying parameter configuration during module usage. The main test case is primarily implemented using macro methods. Error-injection testing of corresponding bits can be performed by passing different test bits to the main test case.

[0050] S220. Based on the register configuration parameters, determine the location of the interrupt field corresponding to the memory unit to be tested in the interrupt register.

[0051] In this embodiment, the bit position of the interrupt field corresponding to the memory unit to be tested in the interrupt register can be determined according to the register configuration parameters.

[0052] Specifically, the target interrupt register is determined based on the interrupt register name, and the bit position of the interrupt field corresponding to the RAM to be tested that exists in the target interrupt register is obtained.

[0053] S230. Obtain the test bit corresponding to the memory unit to be tested, and write target data to the memory unit to be tested according to the test bit. The test bit is determined based on the position of the interrupt field corresponding to the memory unit to be tested in the interrupt register.

[0054] For example, obtaining the test bit corresponding to the memory cell to be tested may include: obtaining the location of the interrupt field corresponding to the memory cell to be tested in the interrupt register, and determining at least one test bit based on the location of the interrupt field.

[0055] S240. Read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data.

[0056] S250. Perform a read operation on the storage unit to be tested again based on the test bit, and inject errors into the storage unit by replacing the read result with the error-injected data source.

[0057] This embodiment improves the efficiency of parameter configuration by setting register configuration parameters in the module test case. Based on the register configuration parameters, the location of the interrupt field corresponding to the memory unit to be tested in the interrupt register is determined, which enables the use of general code to inject errors into different units to be tested, thereby improving the efficiency of error injection.

[0058] Example 3

[0059] Figure 3 This is a flowchart of an error-injection testing method provided in Embodiment 3 of the present invention. This embodiment adds a step of passing the test bits to the macro method before the step "obtaining the test bits corresponding to the memory unit to be tested" in the above embodiments. Terms identical to those in the above embodiments are not repeated here. Figure 3 As shown, the method includes:

[0060] S310. If there are at least two types of memory units to be tested in the interrupt register, then the test bits are passed to the macro methods corresponding to the memory units to be tested respectively, and when passing the test bits to the macro methods corresponding to a certain type of memory unit to be tested, the test bits corresponding to other types of memory units to be tested are masked.

[0061] In this embodiment, for a 2-bit ECC interrupt of the memory cell under test, different types of memory cells under test can exist in the same interrupt register, such as 1rw, 1r1w, and 2r2w types. Different types of memory cells under test will be tested separately, and corresponding interfaces will be provided for each type. For example, taking 1rw type RAM and 1r1w type RAM as examples, the test interfaces can be defined as task A_ram_1rw_intr_case::gen_intr_info() and task A_ram_1r1w_intr_case::gen_intr_info(), respectively. The test programs contained in different test interfaces can be implemented using macro methods.

[0062] When performing an error injection test on a certain type of memory cell, the test bits corresponding to other types of memory cells need to be masked. In this embodiment, the following codes are used as examples: A_ram_1rw_ecc_err_gen(1), A_ram_1rw_ecc_err_gen(2), A_ram_1rw_ecc_err_gen(3), A_ram_1rw_ecc_err_gen(4), and A_ram_1r1w_ecc_err_gen(0). In these codes, the test bits corresponding to the interrupt register are bits 1-4, which belong to the 1rw type of memory cell. The test interface used is task A_ram_1rw_intr_case::gen_intr_info().

[0063] However, for the test memory cell corresponding to the 0th bit which belongs to the 1r1w type, the test interface used is task A_ram_1r1w_intr_case::gen_intr_info(), and the two types of test memory cells are tested separately.

[0064] For example, passing test bits to the macro method corresponding to the memory cell under test may include: for any type of memory cell under test, if the number of test bits is greater than 1, then according to the position of the interrupt field in the interrupt register, the test bits are passed one by one to the macro method corresponding to the current type of memory cell under test.

[0065] In this embodiment, the test memory unit of type 1rw can be used as an example. If bits 1 to 4 in the interrupt register correspond to RAM of type 1rw, then the macro of 1rw is used for error injection test. That is, 4 bits are passed to A_ram_1rw_ecc_err_gen(4), 3 bits are passed to A_ram_1rw_ecc_err_gen(3), 2 bits are passed to A_ram_1rw_ecc_err_gen(2), and 1 bit is passed to A_ram_1rw_ecc_err_gen(1).

[0066] It should be noted that for specific bits in the interrupt register, parameters can be passed to the corresponding type of macro in the above manner for error injection testing. This invention does not limit the passing order.

[0067] For example, reading the target data stored in the storage unit under test according to the test bit, and determining the error injection data source according to the target data may include: for each input test bit, reading the target data in the storage unit under test according to the read address of the current test bit through a macro method, performing a setting operation on the target bit in the target data, and generating an error injection data source.

[0068] In this embodiment, the RAM path and error-checking path can be predefined using the following code:

[0069]

[0070] For macros of type 1rw, the code block executing the error injection test calls macros 'RAM_PATH_4', 'RAM_PATH_3', 'RAM_PATH_2', and 'RAM_PATH_1' to sort all RAM paths according to the corresponding bits in the interrupt register, facilitating unified processing of error injection tests for the corresponding bits. `define RAM_PATH_*` defines the top-level RAM path. `define RAM_ECC_PATH_*` defines the path at the layer above the RAM encoding / decoding and data module. By pre-defining these two paths, maximum reuse of macro methods for error injection can be achieved. That is, the same error injection code can be reused for different bits; only the corresponding path needs to be obtained based on the different bits and the above path definitions.

[0071] For example, the generation of an error-injection data source by reading the target data in the storage unit under test according to the read address of the current test bit using a macro method and performing a setting operation on the target bit in the target data may include: reading the target data in the storage unit under test according to the read address corresponding to the current test bit using a macro method; determining the target bit based on the current test bit and the macro definition; performing an inversion operation on the target bit in the target data using a macro method to generate an error-injection data source, wherein the macro definition includes the definition of the storage unit encoding / decoding and the path of the upper layer of the data module.

[0072] In this embodiment, according to the definition of RAM_ECC_PATH_* above, RAM_ECC_PATH_* is defined for different bits, and the corresponding RAM_ECC_PATH_* is selected according to the bit value of the input macro. The RAM_ECC_PATH_* determines which 2 bits of the target data to invert.

[0073] In RAM_PATH_*, * represents the bit position of the interrupt field in the interrupt register corresponding to RAM.

[0074] Specifically, the target data stored in the test storage unit can be read using the `force` method, and two specific bits in the target data can be inverted to determine the error injection data source. The inversion operation is performed according to a predefined inversion rule. For example, if the target data is 01101100, inverting the first two bits yields 01101111. Correspondingly, the error injection data source is 01101111. The inversion rule can be a macro method that performs an inversion operation on the target bits in the target data to generate the error injection data source.

[0075] S320. Obtain the test bit corresponding to the storage unit to be tested.

[0076] For example, the incoming test bit is obtained through a macro method.

[0077] S330. For each input test bit, write the target data to the memory unit under test according to the write address of the corresponding test bit using a macro method.

[0078] Specifically, the write enable value of RAM_PATH_ram_idx is set to 1 using the force method to write the destination data to RAM. Here, ram_idx is the corresponding bit position in the interrupt register (e.g., bits 1-4 for type 1rw). The RAM enable value of RAM_PATH_ram_idx is set to 1 using the force method to enable RAM. The write address value of RAM_PATH_ram_idx is set to 0 using the force method to write to address 0. The write data value of RAM_PATH_ram_idx is set to 01101100 using the force method to write 01101100 to address 0 of RAM.

[0079] S340. Read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data.

[0080] Specifically, the write enable value of RAM_PATH_ram_idx is set to 0 using the force method to prevent data from being written to RAM. The RAM enable value of RAM_PATH_ram_idx is set to 1 using the force method to enable RAM. The read address value of RAM_PATH_ram_idx is set to 0 using the force method to achieve read address 0, thereby reading the previously written target data m_de_i.

[0081] The target data is this.m_de_i = `RAM_ECC_PATH_``ram_idx.d0_0.DDI[1:0]. By inverting the [1:0] bits in the target data, the error-injection data source m_de_i_n is obtained.

[0082] S350. Perform a read operation on the storage unit to be tested again based on the test bit, and inject errors into the storage unit by replacing the read result with the error-injected data source.

[0083] Specifically, the write enable of RAM_PATH_ram_idx is set to 0 using the force method to prevent data from being written to RAM. The RAM enable of RAM_PATH_ram_idx is set to 1 using the force method to enable RAM. The read address of RAM_PATH_ram_idx is set to 0 using the force method to achieve read address 0. When the data read result is returned, the force data read result is the data source replaced with m_de_i_n.

[0084] This invention utilizes a macro method to perform setting operations on target bits in target data, thereby improving the efficiency of generating error injection data sources and the reusability of error injection code.

[0085] Example 4

[0086] The figure is a schematic diagram of an error testing device provided in Embodiment 4 of the present invention. Figure 4 As shown, the device includes:

[0087] The data writing module 401 is used to obtain the test bit corresponding to the storage unit under test and write target data to the storage unit under test according to the test bit. The test bit is determined based on the position of the interrupt field corresponding to the storage unit under test in the interrupt register.

[0088] The data source determination module 402 is used to read the target data stored in the storage unit to be tested according to the test bit, and determine the error injection data source according to the target data.

[0089] Error injection module 403 is used to perform a read operation on the storage unit to be tested again based on the test bits, and to inject errors into the storage unit by replacing the read result with the error injection data source.

[0090] Optionally, the device may also include:

[0091] The parameter determination module is used to obtain register configuration parameters through the module test cases of the module where the memory cell under test is located before obtaining the test bits corresponding to the memory cell under test. The module test cases are test cases built in the verification environment through electronic design simulation applications.

[0092] The location determination module is used to determine the location of the interrupt field corresponding to the memory unit to be tested in the interrupt register based on the register configuration parameters.

[0093] Optionally, the data writing module 401 is specifically used for:

[0094] The test bit determination unit is used to obtain the location of the interrupt field corresponding to the memory unit to be tested in the interrupt register, and determine at least one test bit based on the location of the interrupt field.

[0095] Optionally, the device may also include:

[0096] The masking module is used to pass the test bits to the macro method corresponding to the memory cell under test respectively if there are at least two types of memory cells under test in the interrupt register before obtaining the test bits corresponding to the memory cell under test. When passing the test bits to the macro method corresponding to a certain type of memory cell under test, the test bits corresponding to other types of memory cells under test are masked.

[0097] The process of writing target data to the storage unit under test based on the test bits includes: for each input test bit, writing target data to the storage unit under test according to the write address of the corresponding test bit using a macro method.

[0098] Optionally, the shielding module is specifically used for:

[0099] For any type of memory cell under test, if the number of test bits is greater than 1, the test bits are passed one by one to the macro method corresponding to the current type of memory cell under test according to the position of the interrupt field in the interrupt register.

[0100] Optionally, the data source determination module 402 includes:

[0101] The error injection unit is used to read the target data in the storage unit under test according to the read address of the current test bit for each input test bit, perform setting operations on the target bit in the target data, and generate an error injection data source.

[0102] Optionally, the error annotation unit is specifically used for:

[0103] The macro method is used to read the target data in the storage unit under test according to the read address corresponding to the current test bit; the target bit is determined based on the current test bit and the macro definition, and the macro method is used to perform an inversion operation on the target bit in the target data to generate an error injection data source. The macro definition includes the definition of the encoding and decoding of the storage unit and the path of the upper layer of the data module.

[0104] The error testing device provided in this embodiment of the invention can execute an error testing method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method.

[0105] Example 5

[0106] Figure 5 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0107] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0108] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0109] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as an error injection testing method.

[0110] In some embodiments, an error-injection testing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the error-injection testing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform an error-injection testing method by any other suitable means (e.g., by means of firmware).

[0111] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0114] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0115] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0116] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0117] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0118] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method of error injection testing, characterized by, The method comprises the following steps: acquiring a test bit corresponding to a to-be-tested storage unit, and writing target data into the to-be-tested storage unit according to the test bit, wherein the test bit is determined based on a position of an interrupt domain corresponding to the to-be-tested storage unit in an interrupt register; reading target data stored in the to-be-tested storage unit according to the test bit, and determining a fault injection data source according to the target data; performing a read operation on the to-be-tested storage unit again according to the test bit, and replacing a read result with the fault injection data source to perform fault injection on the storage unit.

2. The method of claim 1, wherein, Before acquiring the test bit corresponding to the to-be-tested storage unit, the method further comprises the following steps: acquiring a register configuration parameter through a module test case of a module in which the to-be-tested storage unit is located, wherein the module test case is a test case constructed in a verification environment through electronic design simulation; determining the position of the interrupt domain corresponding to the to-be-tested storage unit in the interrupt register according to the register configuration parameter.

3. The method of claim 2, wherein, The step of acquiring the test bit corresponding to the to-be-tested storage unit comprises the following steps: acquiring the position of the interrupt domain corresponding to the to-be-tested storage unit in the interrupt register, and determining at least one test bit according to the position of the interrupt domain.

4. The method according to any one of claims 1-3, characterized in that, Before acquiring the test bit corresponding to the to-be-tested storage unit, the method further comprises the following steps: if there are at least two types of to-be-tested storage units in the interrupt register, delivering the test bit to a macro method corresponding to the to-be-tested storage unit of each type, and shielding the test bit corresponding to the to-be-tested storage unit of another type when delivering the test bit to the macro method corresponding to the to-be-tested storage unit of a certain type; the step of writing target data into the to-be-tested storage unit according to the test bit comprises the following steps: for each test bit, writing target data into the to-be-tested storage unit according to a write address of the corresponding test bit through the macro method.

5. The method of claim 4, wherein, the step of delivering the test bit to the macro method corresponding to the to-be-tested storage unit comprises the following steps: for any type of to-be-tested storage unit in the to-be-tested storage unit, if the number of test bits is greater than 1, the test bits are delivered to the macro method corresponding to the to-be-tested storage unit of the current type one by one according to the position of the interrupt domain in the interrupt register.

6. The method of claim 4, wherein, the step of reading target data stored in the to-be-tested storage unit according to the test bit, and determining a fault injection data source according to the target data comprises the following steps: for each test bit, reading the target data in the to-be-tested storage unit according to a read address of the current test bit through the macro method, performing a setting operation on a target bit in the target data, and generating a fault injection data source.

7. The method of claim 6, wherein, the step of reading the target data in the to-be-tested storage unit according to the read address of the current test bit through the macro method, and performing a setting operation on a target bit in the target data to generate a fault injection data source comprises the following steps: reading the target data in the to-be-tested storage unit according to the read address of the current test bit through the macro method; Determine the target bit based on the current test bit and a macro definition, perform a NOT operation on the target bit in the target data by using the macro method, and generate a bug injection data source, wherein the macro definition includes a definition of a path of a previous layer of a storage unit coding and data module.

8. An error injection test apparatus, characterized by, The method comprises the following steps: A data writing module is configured to obtain a test bit corresponding to a to-be-tested storage unit, and write target data into the to-be-tested storage unit according to the test bit, wherein the test bit is determined based on a position of an interrupt domain corresponding to the to-be-tested storage unit in an interrupt register; A data source determining module is configured to read target data stored by the to-be-tested storage unit according to the test bit, and determine a bug injection data source according to the target data; A bug injection module is configured to perform a read operation on the to-be-tested storage unit again according to the test bit, and replace a read result with the bug injection data source to perform bug injection on the storage unit.

9. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected with the at least one processor in communication; wherein The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the bug injection test method in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to execute the bug injection test method in any one of claims 1-7 when executed.

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