A packaging structure

Abstract

The present application relates to a packaging structure, comprising a thermally conductive pad, the material of which is a conductive material; an adhesive layer, located above the thermally conductive pad, the material of which comprises a thermally conductive and insulating adhesive material; a chip, located above the adhesive layer, comprising a control circuit and a power transistor, the power transistor having a lateral structure, wherein the input end or the output end of the chip is electrically connected to the thermally conductive pad; a plurality of pins, at least part of which are coupled to the control circuit and the other ends of the power transistor; and packaging material, surrounding the thermally conductive pad, the adhesive layer, the chip and the inner pin portion of the plurality of pins; the present application also discloses an electronic device comprising and utilizing the packaging structure as described above.

Description

Technical Field

[0001] The present application relates to the field of chip packaging design, and in particular to a packaging structure. Background Art

[0002] Power distribution chips, which include at least one power transistor that acts as a switch, are generally used to control the on / off switching of loads. They can be categorized as hot-swappable chips, high-side switch chips, and load switch chips. Power distribution chips are a common switching circuit used in manufacturing, enabling cost-saving and efficient high-current load control. They are widely used in electronic devices such as automotive control systems and industrial lighting.

[0003] Traditional power distribution chips consist of control circuits and power transistors. The control circuits provide control and protection for the power transistors. When the power transistors are turned on, the load current flows through their on-resistance, generating heat dissipation in the power transistors. Because power distribution chips generate significant heat dissipation, in actual production, a thermal pad is typically installed on the bottom of the chip package. This pad is soldered to the external PCB heatsink pad to conduct heat from the power distribution chip to the PCB, dissipating the heat.

[0004] With the development of power transistors and related technologies, various structures have emerged in the preparation of power distribution chips. For example, the power transistors in the power distribution chip can adopt a lateral LDMOS structure, a vertical VDMOS structure, or a trench MOS structure. Summary of the Invention

[0005] In response to the technical problems existing in the prior art, the present application proposes a packaging structure, including a thermally conductive pad, the material of the thermally conductive pad being a conductive material; an adhesive layer located above the thermally conductive pad, the material of the adhesive layer comprising a thermally conductive and insulating adhesive material; a chip located above the adhesive layer, comprising a control circuit and a power transistor, the power transistor having a lateral structure, wherein the input end or the output end of the chip is electrically connected to the thermally conductive pad; a plurality of pins, at least some of the plurality of pins being coupled to the control circuit and the other ends of the power transistor; and a packaging material surrounding the thermally conductive pad, the adhesive layer, the chip, and the inner pin portions of the plurality of pins.

[0006] Particularly, the chip is a power switch chip.

[0007] Particularly, the thermally conductive pad includes a base island and a connecting rib electrically connected to each other, and the input end or the output end of the chip is electrically connected to the base island or the connecting rib.

[0008] Particularly, the area of ​​the thermally conductive pad where electrical connection is performed is at least partially plated with silver.

[0009] Particularly, the material of the adhesive layer includes a material with an insulation strength greater than 5V / um and a thermal conductivity greater than 1W / (m·K).

[0010] In particular, it includes one or more steps located above the base island and electrically connected thereto, and the input end or the output end of the chip is electrically connected to the base island through the steps.

[0011] In particular, the region of the step where electrical connection is made is at least partially plated with silver.

[0012] Particularly, the plurality of pins include at least one first pin electrically connected to the thermal pad, and the input end or the output end of the chip is electrically connected to the thermal pad through the first pin.

[0013] Particularly, the first pins only include inner pins surrounded by the packaging material, and the other pins also include outer pins exposed from the packaging material.

[0014] Particularly, the thermal pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located above the first portion; and the second portion is electrically connected to an input terminal or an output terminal of the chip.

[0015] Particularly, the first portion of the thermally conductive pad is electrically connected to the output end of the chip.

[0016] Particularly, a conductive step is provided above the thermally conductive pad, and the chip is electrically connected to the second portion of the thermally conductive pad via the step.

[0017] In particular, the thermal pad includes a first part and a second part electrically isolated from each other, wherein the chip is located above the first part and the second part of the thermal pad; the second part of the thermal pad is electrically connected to the input end or the output end of the chip.

[0018] Particularly, the first portion of the thermally conductive pad is also electrically connected to the output terminal or the input terminal of the chip.

[0019] The present application also proposes an electronic device, comprising and utilizing the aforementioned packaging structure.

[0020] By adopting the solution of the present application, the number of pins of, for example, a power distribution chip can be reduced, the package volume can be reduced, and the packaging cost can be lowered. At the same time, the pins of a chip with a horizontal power transistor structure can be made compatible with the pins of a chip with a vertical power transistor structure. During the application process, there is no need to additionally design the interface of the chip on the printed circuit board, which greatly reduces the design and application costs of the circuit board and improves product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0022] Figure 1A This is a circuit diagram of a power distribution chip;

[0023] Figure 1B is a schematic side cross-sectional view of a power distribution chip fabricated using a lateral structure such as LDMOS;

[0024] Figure 1C is a schematic side cross-sectional view of a power distribution chip fabricated using a vertical structure such as VDMOS;

[0025] Figure 2A is a schematic front cross-sectional view of a packaging structure according to an embodiment of the present application;

[0026] Figure 2B is a schematic cross-sectional view of a package structure according to an embodiment of the present application from the right side;

[0027] Figure 2C is a top view of a packaging structure according to an embodiment of the present application;

[0028] Figure 3A is a right side cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application;

[0029] Figure 3B is a top view of a packaging structure according to another embodiment of the present application;

[0030] Figure 3C is a right side cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application;

[0031] Figure 3D is a top view of a packaging structure according to another embodiment of the present application;

[0032] Figure 4A is a schematic front cross-sectional view of a packaging structure according to an embodiment of the present application;

[0033] Figure 4B is a top view of a packaging structure according to an embodiment of the present application;

[0034] Figure 4C is a schematic front cross-sectional view of a packaging structure according to another embodiment of the present application;

[0035] Figure 4D is a top view of a packaging structure according to another embodiment of the present application; and

[0036] Figure 5 is a top view of a packaging structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0039] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0040] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carriers are electrons or holes, it can be divided into N-type transistors and P-type transistors. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor. The transistor can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductors, organic semiconductors, NMOS / PMOS processes, or CMOS processes.

[0041] The chip described below is a tube core excluding the packaging structure, and the packaging structure refers to the structure including the chip / tube core and external packaging materials.

[0042] Currently, in practical applications, different power distribution chips require external circuits with different structures to operate in conjunction with them due to their different structures. To improve the compatibility of different power distribution chips with external circuits (for example, external circuits suitable for traditional vertical power distribution chip packaging), the present application provides a package including a horizontal power distribution chip that is compatible with traditional vertical external circuits.

[0043] Figure 1A This is a circuit diagram of a power distribution chip.

[0044] like Figure 1A As shown, the power distribution chip may include at least a control circuit 101 and a power transistor 102. The control circuit 101 includes multiple transistors, which may mainly use CMOS process transistors to provide higher device density, supplemented by bipolar transistors and DMOS transistors to reduce the size of the control circuit 101.

[0045] DMOS devices have a similar structure to CMOS devices, with source, drain, and gate electrodes, but the drain breakdown voltage is higher. There are two main types of DMOS: vertical double-diffused MOSFET (VDMOSFET) and lateral double-diffused MOSFET (LDMOSFET).

[0046] Figure 1A The power transistor 102 shown has a high withstand voltage and high power, and can be manufactured using LDMOS / VDMOS or trench MOS processes. According to an embodiment of the present application, the power distribution chip can be a high-side switch chip.

[0047] like Figure 1A The power distribution chip shown receives an input signal Vin and an enable signal EN from an external circuit, and generates an output signal Vout to transmit to the external circuit. In normal operation, Vin is the power supply voltage VDD. The enable signal EN is used to start the control circuit 101.

[0048] Figure 1B This is a side cross-sectional diagram of a power distribution chip fabricated using a lateral structure such as LDMOS. Figure 1B As shown, the power transistor 102 may adopt a lateral structure such as LDMOS, and is formed together with the control circuit 101 on the upper surface of the chip. Figure 1B In the embodiment, the substrate of the power transistor can be a P-type semiconductor prepared by the BCD process. Figure 1B As shown, in a lateral LDMOS structure, the gate, source, and drain are all on the upper surface of the chip. When the current flows from the drain to the source, the current is concentrated on the upper surface of the chip.

[0049] Figure 1C This is a schematic side cross-sectional view of a power distribution chip fabricated using a vertical structure such as VDMOS. Figure 1C As shown, the gate and source of the VDMOS (located in the P-type well) are located on the same plane as the control circuit 101, that is, the upper surface of the chip, while the drain is located on the lower surface of the chip and is electrically connected through the N-type semiconductor substrate. Figure 1C As shown, when the current flows from the drain to the source, the current flows from the bottom surface of the chip to the top surface of the chip.

[0050] like Figure 1B and Figure 1C As shown, the power distribution chip includes a PN junction. To prevent the PN junction from erroneously conducting and affecting normal circuit operation, the substrate of a power distribution chip with a lateral structure, such as LDMOS, needs to be connected to the system's lowest potential, that is, ground. Since the substrate of a power distribution chip with a vertical structure, such as VDMOS, is an N-type semiconductor, it needs to be connected to the system's highest potential, that is, the input signal Vin.

[0051] In the packaging process for power distribution chips, a thermal pad is typically placed on the bottom surface of the chip, and the circuitry on the top surface is wire-bonded. In traditional packaging, the thermal pad not only dissipates heat but also provides power to the chip. To meet this requirement, conventional bonding agents are doped with metal to make them conductive.

[0052] For power distribution chips with lateral structures, such as LDMOS, the thermal pad can be used to provide a ground signal GND to the chip substrate. For power distribution chips with vertical structures, such as VDMOS, the thermal pad can be used to provide an input signal Vin to the power distribution chip. This results in different pinouts for power distribution chips with vertical structures, such as VDMOS, and lateral structures, such as LDMOS.

[0053] For external circuits or electronic devices currently compatible with power distribution chips including vertical structures such as VDMOS, due to the problem of mismatched pin layout, power distribution chips including lateral structures such as LDMOS are not compatible with external circuits using VDMOS power distribution chips.

[0054] Furthermore, wire bonding has certain limitations. For example, the number of wires that can be bonded to a single pin is limited. A wire diameter of, for example, around 30 μm introduces considerable resistance. Chip pins themselves also have resistance. When current flows through them, the presence of pin resistance affects the current flow, increasing chip heat generation. Therefore, existing packaging structures for lateral power distribution chips, such as LDMOS, where both the input terminal Vin and the output terminal Vout are wire-bonded to the package pins, are more susceptible to these limitations.

[0055] For example, a power distribution chip with two independent power transistors and control circuitry forming two paths requires three pins per path. For a lateral structure chip like LDMOS, this requires 3*2*2 = 12 pins, while a vertical structure chip like VDMOS requires 3*2 = 6 pins. Horizontal chips have far more pins than vertical ones, resulting in a larger package size, higher packaging costs, and a larger PCB footprint.

[0056] In order to solve the problems of large packaging volume and high cost caused by the pins of the above-mentioned power distribution chip, as well as the compatibility issues between power distribution chips with different structures and external circuits, the present application proposes a packaging structure that utilizes the characteristics of relatively large thermal pad area and relatively small resistance, adjusts the pin layout of chips including lateral structures such as LDMOS, reduces the number of pins of chips including power transistors with lateral structures, and makes it compatible with external circuits suitable for chips including power transistors with vertical structures.

[0057] Figure 2A FIG. 1 is a schematic front cross-sectional view of a packaging structure according to an embodiment of the present application. Figure 2A As shown, the package structure may include a thermal pad 201 and a chip. The thermal pad 201 provides heat dissipation for the chip and electrically connects the chip to an external circuit. The chip is secured to the thermal pad 201 via an adhesive layer 202. According to one embodiment of the present application, the thermal pad 201 is made of a conductive material.

[0058] According to one embodiment of the present application, the package structure disclosed herein can be applied to chips with lateral power transistor structures, including power distribution chips. The following description uses an embodiment in which the chip surrounded by the package structure is a power distribution chip as an example. According to other embodiments of the present application, the chip can also be other chips with lateral power transistor structures.

[0059] According to an embodiment of the present application, the chip may include a control circuit 204-21 and a power transistor 204-22. According to an embodiment of the present application, during the chip fabrication process, the control circuit 204-21 and the power transistor 204-22 may be fabricated on a common substrate 204-1. Figure 2A As shown. In some embodiments, substrate 204-1 may be a component of control circuit 204-21 and power transistor 204-22. According to one embodiment of the present application, power transistor 204-22 may include LDMOS or other lateral structures. According to one embodiment, substrate 204-1 may be connected to ground terminals on the top surface of the chip via conductive paths (not shown), and these ground terminals are wire-bonded to ground pins.

[0060] According to one embodiment of the present application, the packaging structure may further include an adhesive layer 202 located between the thermal pad 201 and the chip. The adhesive layer 202 is in contact with the thermal pad 201 and the chip and is tightly adhered to the chip, thereby helping the chip to transfer heat to the thermal pad 201. Figure 2A shown.

[0061] like Figure 2A As shown, the chip substrate 204-1 is secured to the thermal pad 201 via an adhesive layer 202. Adhesive layer 202 can be made of a thermally conductive and insulating material. According to one embodiment of the present application, since power transistor 204-22 utilizes a lateral LDMOS structure and has a P-type substrate, substrate 204-1 must be grounded, separate from the input signal Vin network on thermal pad 201. Therefore, adhesive layer 202 connecting substrate 204-1 and thermal pad 201 is made of an insulating material to electrically isolate substrate 204-1 from thermal pad 201.

[0062] According to one embodiment of the present application, the material of adhesive layer 202 can be a connector with good insulation and thermal conductivity, such as Henkel's LOCTITE ABLESTIK 84-3J-GR, which has a dielectric strength of 31 kV / mm and a thermal conductivity of 3 W / (m·K). According to an embodiment of the present application, the thickness of adhesive layer 202 using the above connector can be 20 μm, and the insulation voltage can be greater than or equal to 620 V.

[0063] According to other embodiments of the present application, the material of the adhesive layer 202 may have an insulation strength of at least greater than 5V / um and a thermal conductivity of at least greater than 1W / (m·K). According to embodiments of the present application, the material of the adhesive layer may have an insulation voltage greater than or equal to 50V.

[0064] According to an embodiment of the present application, the package structure may further include a plurality of pins, such as pin 203-1 and pin 203-2. Figure 2A The plurality of pins include inner pins and outer pins. The inner pins refer to the parts located inside the package structure for electrical connection with various terminals, and the outer pins refer to the parts outside the package structure for electrical connection or welding with external circuits.

[0065] According to one embodiment of the present application, the output end of the power transistor 204-22 can be located in the B area where the power transistor is located, and can be electrically connected to the inner pins of at least a portion of the pins 203-1 through the wire bonding 205-1 to transmit the output signal Vout to the external circuit.

[0066] According to one embodiment, the input terminal of the power transistor 204-22 can be located in region A within the power transistor region and electrically connected to the thermal pad 201 via a down-bond 205-3, for example, to receive an input signal Vin from an external circuit via the thermal pad 201. According to one embodiment of the present application, down-bonding is used as a wire bonding method to electrically connect the thermal pad 201 to the input terminal in region A while spanning the insulating adhesive layer 202. According to one embodiment of the present application, the adhesive layer does not cover the entire thermal pad 201, so the wire is bonded to the upper surface of the thermal pad 201 that is not covered by the adhesive layer 202.

[0067] According to other embodiments of the present application, at least a portion of the surface of the thermal pad 201 may be plated with silver to improve the reliability of the bonding process.

[0068] Of course, the arrangement of the input and output terminals in the power transistor region may also be arranged in other layouts and is not limited to the above description. According to one embodiment of the present application, the electrical connection method of the input and output terminals of the power transistor 204-22 may also be reversed, with the output terminal electrically connected to the thermal pad 201 via a downward bond, and the input terminal electrically connected to the inner pin of the pin 203-1 via a wire bond.

[0069] In addition, the electrical connection relationship between the pins 203 - 1 and 203 - 2 bonded to the chip can also be swapped.

[0070] like Figure 2A As shown, the packaging structure may further include packaging material 200, which covers the thermal pad 201 and the chip. According to one embodiment, packaging material 200 may have a rectangular shape, for example, but may also have other shapes as needed. According to embodiments of the present application, packaging material 200 may be made of plastic or other materials that meet production requirements.

[0071] Figure 2B FIG. 1 is a schematic cross-sectional view of a packaging structure according to an embodiment of the present application from the right side. Figure 2B As shown, the thermal pad may include a base island 201-3 and a plurality of connecting ribs 201-1 and 201-2 electrically connected to the base island. The input terminal of the power transistor 204-22 in the chip, located in region A (not shown), is electrically connected to the thermal pad 201-3 via wire bonding. According to other embodiments of the present application, the thermal pad may also include only the base island 201-3 without the connecting ribs electrically connected to the base island.

[0072] Figure 2C FIG. 1 is a top view of a packaging structure according to an embodiment of the present application. Figure 2C As shown, the plurality of pins may include, for example, pins 203-1 and pins 203-2 located on both sides of the plastic packaging material 200. Of course, the pins may also be arranged in other ways as needed.

[0073] According to one embodiment, the control terminal of the control circuit 204 - 21 receiving the control signal EN may be electrically connected to the inner pins of at least some of the pins 203 - 2 through the wire bonding 205 - 2 to receive the control signal EN from the external circuit.

[0074] According to an embodiment of the present application, the ground terminal in the chip may be coupled to an inner pin of a ground pin (not shown) that is part of 203 - 2 by wire bonding.

[0075] Figure 3A : is a right side cross-sectional schematic diagram of a package structure according to another embodiment of the present application. According to one embodiment of the present application, the package structure may further include steps 311-1 and 311-2 which are independent of the chip, located above the thermal pad 301 and electrically connected to the thermal pad 301, such as Figure 3A As shown. The purpose of providing steps 311-1 and 311-2 is to improve the electrical connection effect between the thermal pad 301 and the input terminal in area A (not shown). According to one embodiment of the present application, the input terminal of the power transistor in the chip can be electrically connected to the steps 311-1 and 311-2 on the thermal pad 301 through a wire bonding process. According to one embodiment of the present application, the step 311 can make the arc produced by the bonding process better, reduce the stress at the contact, avoid delamination at the contact, and improve reliability.

[0076] According to an embodiment of the present application, the height of the steps 311 - 1 and 311 - 2 may be the same as the height of the plurality of inner pins.

[0077] According to an embodiment of the present application, at least a portion of the surface of the steps 311 - 1 and 311 - 2 that contacts the input terminal of the chip may be silver-plated to improve the reliability of the bonding process on the step 311 .

[0078] Figure 3BFIG. 1 is a top view of a packaging structure according to another embodiment of the present application. Figure 3B As shown, since the chip needs to pass a large current, there can be multiple steps 311 - 1 and 311 - 2, all located above the thermal pad 301, for electrical connection with the input terminal in the chip A area to reduce chip loss.

[0079] Figure 3C It is a right side cross-sectional schematic diagram of a packaging structure according to another embodiment of the present application. Figure 3D is a top view of a packaging structure according to another embodiment of the present application.

[0080] According to another embodiment of the present application, the input terminal in the chip A region can be electrically connected to the connecting ribs 301-1 and 301-2 of the thermal pad 301 by wire bonding, such as Figure 3C and 3D The other terminals except the input terminals are electrically connected to the inner terminals of at least some of the pins 303 - 1 and 303 - 2 through wire bonding.

[0081] Figure 4A 1 is a schematic front cross-sectional view of a packaging structure according to an embodiment of the present application. Figure 4B FIG. 1 is a top view of a packaging structure according to an embodiment of the present application. Figure 4B As shown, the chip's A region is electrically connected to one or at least part of the inner pins of the pins 403-1 through wire bonding. The inner pins of the pins electrically connected to the A region are also electrically connected to the base island 401-3 of the thermal pad, as shown in FIG. Figure 4A shown.

[0082] According to an embodiment of the present application, the inner pins of the pins electrically connected to the A region must be electrically connected to the thermal pad, and the outer pins thereof are not electrically connected to an external circuit that receives other signals.

[0083] According to other embodiments of the present application, the pin electrically connected to region A may also be one or at least part of the pins 403 - 2 , depending on actual production needs.

[0084] Figure 4C 4 is a schematic front cross-sectional view of a packaging structure according to another embodiment of the present application. Figure 4D is a top view of a packaging structure according to another embodiment of the present application.

[0085] like Figure 4D As shown, the chip's A region is electrically connected to one or at least part of the inner pins of the pins 403-1 through wire bonding. The inner pins of the pins electrically connected to the A region are also electrically connected to the base island 401-3 of the thermal pad, as shown in FIG. Figure 4CAccording to the embodiment of the present application, the pins electrically connected to the A region are flush with the edge of the packaging material 400 of the packaging structure, and do not include external pins exposed outside the packaging material 400 and electrically connected to the external circuit, such as Figure 4C shown.

[0086] According to an embodiment of the present application, the pin electrically connected to region A may also be one or at least part of the pins 403 - 2 , which is determined according to actual production needs.

[0087] Figure 5 FIG. 1 is a top view of a packaging structure according to another embodiment of the present application. Figure 5 As shown, the thermal pad may include a first portion 501 - 1 and a second portion 501 - 2 , and the first portion 501 - 1 and the second portion 501 - 2 are electrically isolated from each other.

[0088] According to one embodiment of the present application, only the first portion 501-1 is in contact with the adhesive layer (not shown) to dissipate heat from the chip, and only the second portion 501-2 is electrically connected to the input terminal in the chip A region to form an electrical network for receiving an input signal Vin from an external circuit.

[0089] like Figure 5 As shown, the input terminal in the chip region A can be electrically connected to the second portion 501-2 by wire bonding, or by other processes. According to one embodiment of the present application, the portion of the thermal pad second portion 501-2 that contacts the input terminal in region A can be specially processed, such as forming a step at the portion of the thermal pad 501-2 that contacts the input terminal in region A and silver-plating at least a portion of the contact surface to reduce process complexity.

[0090] According to an embodiment of the present application, the area of ​​the first portion 501 - 1 of the thermal pad may be the same as the vertical projection area of ​​the chip, or may be larger or smaller than the area of ​​the chip, depending on actual production needs.

[0091] According to other embodiments of the present application, the first portion 501-1 of the thermal pad may also be electrically connected to the chip. According to embodiments of the present application, the electrical signal transmitted by the first portion 501-1 of the thermal pad may be the same as or different from the electrical signal transmitted by the second portion 501-2. For example, the electrical signals transmitted by the first portion 501-1 and the second portion 501-2 of the thermal pad may both be input signals Vin, or the first portion may transmit the output signal Vout while the second portion transmits the input signal Vin.

[0092] According to other embodiments of the present application, the electrical signals transmitted by the first part 501 - 1 and the second part 501 - 2 may also be interchangeable or other electrical signals.

[0093] According to another embodiment of the present application, an adhesive layer (not shown) can be located above the first portion 501-1 and the second portion 501-2 of the thermal pad, contacting the first portion 501-1 and the second portion 501-2, respectively. According to one embodiment, only the second portion 501-2 can be electrically connected to the input terminal of the chip, or the first portion 501-1 can be electrically connected to the output terminal, and the second portion 501-2 can be electrically connected to the input terminal. According to an embodiment of the present application, the output terminal or the input terminal electrically connected to the first portion 501-1 and the second portion 501-2 can be swapped, so that the first portion 501-1 transmits Vin and the second portion 501-2 transmits Vout.

[0094] The present application also provides an electronic device, comprising the packaging structure described in the above embodiment.

[0095] By adopting the solution of the present application, the number of pins of, for example, a power distribution chip can be reduced, the package volume can be reduced, and the packaging cost can be lowered. At the same time, the pins of a chip including a horizontal power transistor can be made compatible with the pins of a chip including a vertical power transistor. During the application process, there is no need to additionally design the interface of the chip on the printed circuit board, which greatly reduces the design and application costs of the circuit board and improves product competitiveness.

[0096] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A packaging structure, comprising: A thermally conductive pad, wherein the material of the thermally conductive pad is a conductive material; an adhesive layer, located above the thermally conductive pad, wherein the adhesive layer comprises a thermally conductive and insulating adhesive material; a chip, located above the adhesive layer, comprising a control circuit and a power transistor, wherein the power transistor has a lateral structure, wherein an input terminal or an output terminal of the chip is electrically connected to the thermal pad, and a substrate of the power transistor is grounded and electrically isolated from the thermal pad; a plurality of pins, at least a portion of the plurality of pins being coupled to the control circuit and other terminals of the power transistor; as well as, The packaging material surrounds the thermal pad, the adhesive layer, the chip and the inner pin portions of the plurality of pins.

2. The packaging structure according to claim 1, wherein: The chip is a power distribution chip.

3. The package structure according to claim 1, wherein: The thermal conductive pad includes a base island and a connecting rib electrically connected to each other, and the input end or the output end of the chip is electrically connected to the base island or the connecting rib.

4. The package structure according to claim 1, wherein: The area where the thermally conductive pad is electrically connected is at least partially plated with silver.

5. The package structure according to claim 1, wherein: The material of the adhesive layer includes a material with an insulation strength greater than 5V / um and a thermal conductivity greater than 1W / (m·K).

6. The package structure according to claim 3, further comprising: One or more steps are located above the base island and electrically connected thereto, and the input end or the output end of the chip is electrically connected to the base island through the steps.

7. The package structure according to claim 6, wherein: The region of the step where the electrical connection is made is at least partially plated with silver.

8. The package structure according to claim 1, wherein: The plurality of pins include at least one first pin electrically connected to the thermally conductive pad, and the input end or the output end of the chip is electrically connected to the thermally conductive pad through the first pin.

9. The package structure according to claim 8, wherein: The first pins only include inner pins surrounded by the packaging material, and the other pins also include outer pins exposed from the packaging material.

10. The package structure according to claim 1, wherein: The thermal pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located above the first portion; The second portion is electrically connected to an input terminal or an output terminal of the chip. The package structure according to claim 10 , wherein: The first portion of the thermal conductive pad is electrically connected to the output end or the input end of the chip.

12. The package structure according to claim 10, wherein: A conductive step is provided above the second portion of the thermally conductive pad, and the chip is electrically connected to the second portion of the thermally conductive pad via the step.

13. The package structure according to claim 1, wherein: The thermal pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located above the first portion and the second portion of the thermal pad; The second portion of the thermal conductive pad is electrically connected to the input end or the output end of the chip.

14. The package structure according to claim 13, wherein: The first portion of the thermal pad is also electrically connected to the output terminal or the input terminal of the chip.

15. An electronic device comprising the packaging structure according to any one of claims 1 to 14.

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