A power device chip and its fabrication method

Abstract

This invention provides a power device chip and its fabrication method. The power device chip includes a semiconductor layer and a back conductive metal layer. The semiconductor layer includes a front side and a back side disposed opposite to each other, and a back trench is provided on the back side of the semiconductor layer. The back conductive metal layer is located on the back side of the semiconductor layer and fills the back trench. This invention utilizes the back trench to allow the semiconductor material on the back side of the chip to intersect with the heat-dissipating metal, forming a heat dissipation structure, thereby reducing the thermal resistance in the current path. Furthermore, the introduction of the back trench also helps to shorten the current path, further reducing resistance. This allows for a thicker semiconductor layer, which not only reduces manufacturing difficulty and improves yield but also increases the short-circuit withstand capability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology and relates to a power device chip and its manufacturing method. Background Technology

[0002] Power devices include IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and power diodes. Almost all modern power devices conduct electricity vertically. To reduce resistance and thermal resistance in the current path, it is usually necessary to reduce the wafer thickness as much as possible. However, wafer thinning introduces problems such as wafer bending, high fragmentation rate, and deterioration of short-circuit parameters.

[0003] The currently popular TAIKO process, developed by Japan's Disco, is a wafer thinning process that only thins the middle portion of the wafer, leaving the edges as support rings. Integrated circuit devices are formed in the thinned middle portion, while the thicker support rings maintain the overall mechanical strength of the wafer, preventing warping and facilitating subsequent wafer handling, transfer, and processing. However, due to the presence of the support rings, wafer-level packaging cannot be completed in standard packaging lines. This means that the support rings typically need to be removed before subsequent wafer-level packaging processes, introducing additional processes and equipment, increasing production costs. Therefore, adopting the currently popular TAIKO process leads to problems such as wafer waste in the support ring area, increased difficulty in CP testing, and high process costs.

[0004] The reason for the bending of ultra-thin wafers is the excessive stress difference between the upper and lower surfaces; the reason for the high breakage rate is that the wafer is too thin; the high cost of the TAIKO process is due to the high price of the newly added equipment and the complexity of the process; at the same time, the reduction in chip thickness leads to a reduction in short-circuit withstand capability. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power device chip and its manufacturing method, which solves the problems of wafer bending, high fragmentation rate, deterioration of short-circuit parameters, increased cost, and complex process caused by wafer thinning in the manufacturing of existing power device chips.

[0006] To achieve the above and other related objectives, the present invention provides a power device chip, comprising:

[0007] A semiconductor layer includes a front side and a back side disposed opposite to each other, wherein the back side of the semiconductor layer is provided with a back trench;

[0008] A back-side conductive metal layer is located on the back side of the semiconductor layer and fills the back-side trench.

[0009] Optionally, the power device chip includes one of an insulated gate bipolar transistor chip, a metal-oxide-semiconductor field-effect transistor chip, and a diode chip.

[0010] Optionally, the semiconductor layer includes an N-type lightly doped host layer, an N-type heavily doped layer located on the back side of the N-type lightly doped host layer, and a P-type heavily doped layer located on the back side of the N-type heavily doped layer. The N-type heavily doped layer and the P-type heavily doped layer extend into the N-type lightly doped host layer according to the contour of the back trench, and the back metal conductive layer is in contact with the P-type doped layer.

[0011] Optionally, the power device chip further includes a gate structure located on the front side of the semiconductor layer, the gate structure including a gate dielectric layer and a gate conductive layer.

[0012] Optionally, the gate structure includes at least one of a planar gate structure and a trench gate structure.

[0013] Optionally, the position of the back trench corresponds to the position of the gate structure.

[0014] Optionally, the power device chip further includes:

[0015] A front-side conductive metal layer is located on the front side of the semiconductor layer;

[0016] An insulating layer is located between the gate structure and the front metal conductive layer to electrically isolate the gate conductive layer from the front metal conductive layer.

[0017] Optionally, the semiconductor layer has a P-type doped region and an N-type heavily doped region. The P-type doped region is distributed on both sides of the gate structure, and the N-type heavily doped region is located in the P-type doped region. The front metal conductive layer contacts the P-type doped region and the N-type heavily doped region.

[0018] Optionally, the semiconductor layer may be made of at least one of silicon carbide, III-V compound, silicon, germanium, or germanium-silicon.

[0019] This invention also provides a method for manufacturing a power device chip, comprising the following steps:

[0020] A semiconductor layer is provided, the semiconductor layer including a front side and a back side disposed opposite to each other;

[0021] The back side of the semiconductor layer is ground to thin the semiconductor layer, wherein the central region and the edge region of the semiconductor layer are ground simultaneously during the grinding process;

[0022] Form a back trench on the back side of the semiconductor layer;

[0023] A back metal conductive layer is formed on the back side of the semiconductor layer, and the back metal conductive layer fills the back trench.

[0024] Optionally, the power device chip includes one of an insulated gate bipolar transistor chip, a metal-oxide-semiconductor field-effect transistor chip, and a diode chip.

[0025] Optionally, the semiconductor layer includes an N-type lightly doped host layer, and the back trench opens from the back side of the N-type lightly doped host layer and extends toward the front side of the N-type lightly doped host layer; after forming the back trench, N-type ion implantation and P-type ion implantation are performed sequentially along the back side of the N-type lightly doped host layer and the inner wall of the back trench to form an N-type heavily doped layer and a P-type heavily doped layer, wherein the depth of the N-type ion implantation is greater than the depth of the P-type ion implantation, and then the back metal conductive layer in contact with the P-type doped layer is formed.

[0026] Optionally, laser annealing is performed after the N-type ion implantation and the P-type ion implantation to form the heavily doped N-type layer and the heavily doped P-type layer.

[0027] Optionally, the method further includes the step of forming a gate structure on the front side of the semiconductor layer, the gate structure including a gate dielectric layer and a gate conductive layer.

[0028] Optionally, the gate structure includes at least one of a planar gate structure and a trench gate structure.

[0029] Optionally, the position of the back trench corresponds to the position of the gate structure.

[0030] Optionally, the method further includes the steps of forming an insulating layer, a P-type doped region, an N-type heavily doped region, and a front-side metal conductive layer. The P-type doped region is located in the semiconductor layer and distributed on both sides of the gate structure. The N-type heavily doped region is located in the P-type doped region. The front-side metal conductive layer is located on the front side of the semiconductor layer and contacts the P-type doped region and the N-type heavily doped region. The insulating layer is located between the gate structure and the front-side metal conductive layer to electrically isolate the gate conductive layer from the front-side metal conductive layer.

[0031] Optionally, the method for forming the back trench includes wet etching, and the method for forming the back conductive metal layer includes vapor deposition.

[0032] Optionally, the method further includes a step of planarizing the back surface of the back metal conductive layer.

[0033] Optionally, the semiconductor layer may be made of at least one of silicon carbide, III-V compound, silicon, germanium, or germanium-silicon.

[0034] As described above, the power device chip and its fabrication method of the present invention have a back trench on the back side of the semiconductor layer, and a back conductive metal layer is filled into the back trench, so that the semiconductor material on the back side of the chip intersects with the metal with better heat dissipation to form a heat dissipation structure, thereby reducing the thermal resistance in the current path. In addition, the back trench can push the N-type heavily doped layer on the back side (as a field termination layer in IGBT devices) into the chip interior, shortening the current path and reducing resistance. The reduced thermal resistance and resistance mean that the thickness of the semiconductor layer does not need to be too thin. When thinning the semiconductor wafer used to fabricate the power device chip on the back side, conventional grinding processes can be used, avoiding the use of TAIKO thinning process, reducing process costs, and the thickness of the product with the same voltage specification is higher than that of the TAIKO thinned wafer. The maintained overall thickness of the semiconductor wafer makes the wafer less prone to bending and breakage; in addition, the back trench structure changes the back stress, further making the wafer less prone to bending; and the maintenance of the overall chip thickness is beneficial to increasing the short-circuit withstand capability of the device. Attached Figure Description

[0035] Figure 1 The diagram shown is a longitudinal cross-sectional view of the active region of the power device chip of the present invention.

[0036] Figure 2 The image shows a thickness comparison between the first power device chip and the second power device chip.

[0037] Figure 3 The diagram shown is a process flow chart of the method for manufacturing the power device chip of the present invention.

[0038] Component designation explanation

[0039] 1 Semiconductor layer

[0040] 101 N-type lightly doped host layer

[0041] 102 N-type heavily doped layer

[0042] 103 P-type doped layer

[0043] 104 P-type doped region

[0044] 105 N-type heavily doped region

[0045] 2 Gate Structure

[0046] 201 Gate Dielectric Layer

[0047] 202 Gate conductive layer

[0048] 3. Front-side conductive metal layer

[0049] 4 Insulation layer

[0050] 5. Backside conductive metal layer

[0051] 6. Back groove

[0052] 100 First Power Device Chip

[0053] 200 Second Power Device Chip

[0054] Steps S1 to S4 Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Example 1

[0058] This embodiment provides a power device chip; please refer to [link / reference]. Figure 1 The diagram shows a longitudinal cross-sectional view of the active region of the power device chip, including a semiconductor layer 1 and a back metal conductive layer 5. The semiconductor layer 1 includes a front side and a back side disposed opposite to each other, and a back trench 6 is provided on the back side of the semiconductor layer 1. The back metal conductive layer 5 is located on the back side of the semiconductor layer 1 and fills the back trench 6.

[0059] Specifically, the back metal conductive layer 5 is filled into the back trench 6, so that the semiconductor material on the back of the chip and the metal with better heat dissipation intersect to form a heat dissipation structure, thereby reducing the thermal resistance in the current path.

[0060] As an example, the power device chip can be one of the following: an insulated gate bipolar transistor (IGBT) chip, a metal-oxide-semiconductor field-effect transistor (MOSFET) chip, and a diode chip, or other types of semiconductor chips. The material of the semiconductor layer 1 includes at least one of silicon carbide, III-V compound (e.g., gallium nitride), silicon, germanium, germanium-silicon, or other suitable semiconductor materials.

[0061] In this embodiment, a trench-type FS field-terminated IGBT is used to illustrate the power device chip of the present invention, such as... Figure 1 As shown, the semiconductor layer 1 includes an N-type lightly doped host layer 101, an N-type heavily doped layer 102 located on the back side of the N-type lightly doped host layer 101, and a P-type heavily doped layer 103 located on the back side of the N-type heavily doped layer 102. The N-type heavily doped layer 102 and the P-type heavily doped layer 103 extend into the N-type lightly doped host layer 101 according to the contour of the back trench 6. The back metal conductive layer 5 is in contact with the P-type doped layer 103. The N-type heavily doped layer 102 serves as a field stop layer (FS layer). The back trench 6 pushes the FS layer into the chip interior, shortening the current path and reducing resistance.

[0062] As an example, the power device chip further includes a gate structure 2 located on the front side of the semiconductor layer 1, the gate structure 2 including a gate dielectric layer 201 and a gate conductive layer 202. The gate structure 2 may be at least one of a planar gate structure and a trench gate structure.

[0063] As an example, the position of the back trench 6 corresponds to the position of the gate structure 2. In particular, when the gate structure 2 adopts a trench gate structure, the corresponding position of the back trench 6 and the front trench helps to maintain the same or similar stress on the front and back sides of the wafer, thereby reducing or avoiding wafer warpage.

[0064] As an example, the power device chip further includes a front-side metal conductive layer 3 and an insulating layer 4. The front-side metal conductive layer 3 is located on the front side of the semiconductor layer 1. The insulating layer 4 is located between the gate structure 2 and the front-side metal conductive layer 3 to electrically isolate the gate conductive layer 202 and the front-side metal conductive layer 3.

[0065] As an example, the semiconductor layer 1 is further provided with a P-type doped region 104 and an N-type heavily doped region 105. The P-type doped region 104 is distributed on both sides of the gate structure 2, and the N-type heavily doped region 105 is located in the P-type doped region 104. The front metal conductive layer 3 contacts the P-type doped region 104 and the N-type heavily doped region 105.

[0066] It should be noted that the terms "light doping" and "heavy doping" are relative concepts. The specific doping concentration parameters of each doped layer can be adjusted as needed, as long as the doping concentration is light doping < heavy doping < heavy doping.

[0067] In addition, in other embodiments, the specific layer structure of the semiconductor layer 1 may be adjusted as needed depending on the type and performance requirements of the power device chip, and this should not excessively limit the scope of protection of the present invention.

[0068] For example, please refer to Figure 2 The image shows a thickness comparison between the first power device chip 100 and the second power device chip 200. The first power device chip 100 does not use a back trench, while the second power device chip 200 uses a power device chip with a back trench as described in this embodiment. The power device chip in this embodiment uses a back trench to reduce the thermal resistance in the current path and shorten the current path, thereby reducing the resistance. This allows for a thicker semiconductor layer, which not only helps to reduce the difficulty of the process and improve the yield, but also increases the short-circuit withstand capability of the device.

[0069] Example 2

[0070] This embodiment provides a method for fabricating a power device chip. Please refer to [link / reference]. Figure 3 The diagram shows the process flow of this method, which includes the following steps:

[0071] S1: A semiconductor layer is provided, the semiconductor layer including a front side and a back side disposed opposite to each other;

[0072] S2: The back side of the semiconductor layer is ground to thin the semiconductor layer, wherein the central region and the edge region of the semiconductor layer are ground simultaneously during the grinding process;

[0073] S3: Form a back trench on the back side of the semiconductor layer;

[0074] S4: A back metal conductive layer is formed on the back side of the semiconductor layer, and the back metal conductive layer fills the back trench.

[0075] As an example, the power device chip can be one of the following: an insulated gate bipolar transistor (IGBT) chip, a metal-oxide-semiconductor field-effect transistor (MOSFET) chip, and a diode chip, or other types of semiconductor chips. The material of the semiconductor layer includes at least one of silicon carbide, III-V compound (e.g., gallium nitride), silicon, germanium, germanium-silicon, or other suitable semiconductor materials.

[0076] In this embodiment, a trench-type FS field-terminated IGBT is used to illustrate the fabrication method of the power device chip of the present invention, such as... Figure 1As shown, the semiconductor layer 1 includes an N-type lightly doped host layer 101. The back trench 6 opens from the back side of the N-type lightly doped host layer 101 and extends towards the front side of the N-type lightly doped host layer 101. After forming the back trench 6, N-type ion implantation and P-type ion implantation are performed sequentially along the back side of the N-type lightly doped host layer 101 and the inner wall of the back trench 6 to form an N-type heavily doped layer 102 and a P-type heavily doped layer 103. The depth of the N-type ion implantation is greater than the depth of the P-type ion implantation. Then, the back metal conductive layer 5 is formed in contact with the P-type doped layer 103. The N-type heavily doped layer 102 serves as a field termination layer (FS layer). The back trench 6 pushes the FS layer into the chip interior, shortening the current path and reducing resistance.

[0077] As an example, laser annealing is performed after the N-type ion implantation and the P-type ion implantation to eliminate implantation damage and activate implanted impurities, thereby forming the N-type heavily doped layer 102 and the P-type heavily doped layer 103.

[0078] As an example, the method further includes the step of forming a gate structure 2 on the front side of the semiconductor layer 1, the gate structure 2 including a gate dielectric layer 201 and a gate conductive layer 202. The gate structure 2 may be at least one of a planar gate structure and a trench gate structure.

[0079] As an example, the position of the back trench 6 corresponds to the position of the gate structure 2. In particular, when the gate structure 2 adopts a trench gate structure, the corresponding position of the back trench 6 and the front trench helps to maintain the same or similar stress on the front and back sides of the wafer, thereby reducing or avoiding wafer warpage.

[0080] As an example, the method further includes the steps of forming an insulating layer 4, a P-type doped region 104, an N-type heavily doped region 105, and a front-side metal conductive layer 3. The P-type doped region 104 is located in the semiconductor layer 101 and distributed on both sides of the gate structure 2. The N-type heavily doped region 105 is located in the P-type doped region 104. The front-side metal conductive layer 3 is located on the front side of the semiconductor layer 1 and contacts the P-type doped region 104 and the N-type heavily doped region 105. The insulating layer 4 is located between the gate structure 2 and the front-side metal conductive layer 3 to electrically isolate the gate conductive layer 202 and the front-side metal conductive layer 3.

[0081] As an example, the method for forming the back trench 6 includes wet etching or other suitable patterning methods, and the method for forming the back conductive metal layer 3 includes vapor deposition or other suitable deposition methods.

[0082] As an example, the method also includes a step of planarizing the back side of the back metal conductive layer 3.

[0083] The power device chip fabrication method of this embodiment can use conventional grinding process when thinning the back side, which helps to reduce process cost. The overall thickness of the semiconductor wafer retained after thinning is relatively thick, and the back trench structure changes the back stress, which makes the wafer less prone to bending and breakage, and helps to increase the short-circuit withstand capability of the device.

[0084] In summary, the power device chip and its fabrication method of the present invention feature a back trench on the back side of the semiconductor layer, with a back conductive metal layer filling the back trench. This allows the semiconductor material on the back side of the chip to intersect with the heat-dissipating metal, forming a heat dissipation structure and reducing thermal resistance in the current path. Furthermore, the back trench can push the heavily doped N-type layer (used as a field-stop layer in IGBT devices) into the chip interior, shortening the current path and reducing resistance. The reduced thermal and electrical resistance means the semiconductor layer does not need to be excessively thin. The semiconductor wafer used to fabricate the power device chip can be thinned using conventional grinding processes, avoiding the use of the TAIKO thinning process, thus reducing process costs. Moreover, the thickness of the product with the same voltage specification is higher than that of the TAIKO-thinned wafer, and the maintained overall thickness of the semiconductor wafer makes it less prone to bending and breakage. Additionally, the back trench structure alters the back stress, further reducing wafer bending. Maintaining the overall chip thickness also helps increase the short-circuit withstand capability of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power device chip, characterized by, The power device chip comprises: a semiconductor layer comprising a front surface and a back surface arranged oppositely, wherein the back surface of the semiconductor layer is provided with a back surface trench; a back surface metal conductive layer located on the back surface of the semiconductor layer and filled into the back surface trench; wherein the power device chip further comprises a gate structure located on the front surface of the semiconductor layer, and the gate structure comprises a gate dielectric layer and a gate conductive layer; the gate structure comprises a trench gate structure; the position of the back surface trench corresponds to the position of the gate structure.

2. The power device chip of claim 1, wherein: The power device chip comprises one of an insulated gate bipolar transistor chip, a metal-oxide semiconductor field effect transistor chip and a diode chip.

3. The power device chip of claim 1, wherein: The semiconductor layer comprises an N-type lightly doped body layer, an N-type heavily doped layer located on the back surface of the N-type lightly doped body layer and a P-type heavily doped layer located on the back surface of the N-type heavily doped layer, wherein the N-type heavily doped layer and the P-type heavily doped layer extend into the N-type lightly doped body layer according to the profile of the back surface trench, and the back surface metal conductive layer is in contact with the P-type heavily doped layer.

4. The power device chip of claim 1, wherein, The power device chip further comprises: a front surface metal conductive layer located on the front surface of the semiconductor layer; an insulating layer located between the gate structure and the front surface metal conductive layer to electrically separate the gate conductive layer and the front surface metal conductive layer.

5. The power device chip of claim 4, wherein: The semiconductor layer is provided with a P-type doped region and an N-type heavily doped region, wherein the P-type doped region is distributed on both sides of the gate structure, the N-type heavily doped region is located in the P-type doped region, and the front surface metal conductive layer is in contact with the P-type doped region and the N-type heavily doped region.

6. The power device chip of claim 1, wherein: The material of the semiconductor layer comprises at least one of silicon carbide, a III-V compound, silicon, germanium and germanium silicon.

7. A method of fabricating a power device chip, characterized by, The method comprises the following steps: providing a semiconductor layer comprising a front surface and a back surface arranged oppositely; thinning the semiconductor layer by grinding the back surface of the semiconductor layer, wherein the center region and the edge region of the semiconductor layer are ground simultaneously during the grinding process; forming a back surface trench on the back surface of the semiconductor layer; forming a back surface metal conductive layer on the back surface of the semiconductor layer, wherein the back surface metal conductive layer is filled into the back surface trench; wherein the method further comprises the step of forming a gate structure on the front surface of the semiconductor layer, and the gate structure comprises a gate dielectric layer and a gate conductive layer; the gate structure comprises a trench gate structure; the position of the back surface trench corresponds to the position of the gate structure.

8. The method of claim 7, wherein: The power device chip comprises one of an insulated gate bipolar transistor chip, a metal-oxide semiconductor field effect transistor chip and a diode chip.

9. The method of claim 7, wherein: The semiconductor layer comprises an N-type lightly doped body layer, the back surface trench is opened from the back surface of the N-type lightly doped body layer and extends to the front surface of the N-type lightly doped body layer; after the back surface trench is formed, N-type ion implantation and P-type ion implantation are sequentially performed along the back surface of the N-type lightly doped body layer and the inner wall of the back surface trench to form an N-type heavily doped layer and a P-type heavily doped layer, wherein the depth of the N-type ion implantation is greater than the depth of the P-type ion implantation, and then the back surface metal conductive layer in contact with the P-type heavily doped layer is formed.

10. The method of claim 9, wherein: After the N-type ion implantation and the P-type ion implantation, laser annealing is performed to form the N-type heavily doped layer and the P-type heavily doped layer.

11. The method of claim 7, wherein: The method further comprises forming an insulating layer, a P-type doped region, an N-type heavily doped region and a front metal conductive layer, the P-type doped region is located in the semiconductor layer and distributed on both sides of the gate structure, the N-type heavily doped region is located in the P-type doped region, the front metal conductive layer is located on the front surface of the semiconductor layer and contacts the P-type doped region and the N-type heavily doped region, and the insulating layer is located between the gate structure and the front metal conductive layer to electrically isolate the gate conductive layer and the front metal conductive layer.

12. The method of claim 7, wherein: The method for forming the back trench comprises wet etching, and the method for forming the back conductive metal layer comprises evaporation.

13. The method of claim 7, wherein: The method further comprises a step of performing back planarization treatment on the back metal conductive layer.

14. The method of claim 7, wherein: The material of the semiconductor layer comprises at least one of silicon carbide, a III-V compound, silicon, germanium, and germanium silicon.

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