A continuous-time linear equalizer with a compact layout and highly immune to common-mode noise

Abstract

A continuous-time linear equalizer (CTLE) includes: a common-source amplifier configured to receive an input signal and output an output signal according to a bias current; a current source controlled by a first bias voltage and configured to output the bias current; an active load controlled by a second bias voltage and serving as a load of the common-source amplifier; a common-mode sensing circuit configured to sense a common-mode voltage of the output signal; a current source controller configured to output the first bias voltage according to the common-mode voltage and a reference voltage, wherein the reference voltage is derived from a supply voltage of the active load and a first reference current; and an active load controller configured to output the second bias voltage according to the supply voltage of the active load and a second reference current.

Description

Technical Field

[0001] The present invention relates to a continuous time linear equalizer, and in particular to a continuous time linear equalizer with compact layout and high immunity to common mode noise. Background Art

[0002] A continuous time linear equalizer (CTLE) receives an input signal and outputs an output signal according to a frequency-dependent gain factor. In one embodiment, the gain factor is larger when the frequency of the input signal is higher. Figure 1 As shown, a conventional CTLE 100 includes: a bias voltage generator 110 including a diode-connected NMOS transistor 111 for receiving a reference current I REF , and establish a bias voltage V B A current source 140, comprising two NMOS transistors 141, 142, which are respectively used according to the bias voltage V B Output two bias currents I bias+ ,I bias- A common source amplifier 120, comprising two NMOS transistors 121, 122, which are respectively used according to the two bias currents I bias+ ,I bias- Receive an input signal and output an output signal, wherein the input signal includes two input voltages V I+ 、V I- , the output signal contains two output voltages V O+ 、V O- a load circuit 130 comprising two inductors 131 and 132 and two resistors 133 and 134 and used as a load for the common-source amplifier 120; and a source attenuation circuit 150 comprising a resistor 151 and a capacitor 152 connected in parallel and used to attenuate the common-source amplifier 120. Figure 1 In, V DD represents a power supply node. The gain of CTLE 100 is determined by the impedance of load circuit 130 and the impedance of source attenuator circuit 150. A higher impedance of load circuit 130 results in a higher gain; a lower impedance of source attenuator circuit 150 also results in a higher gain. A higher frequency input signal sees a higher impedance of load circuit 130 and a lower impedance of source attenuator circuit 150, resulting in a higher gain. CTLE 100 is well known in the art and will not be described in detail here.

[0003] CTLE 100 has two common problems. First, inductors 131 and 132 can effectively amplify the impedance of load circuit 130 at high frequencies, thereby increasing the high-frequency gain of common-source amplifier 120. However, inductors are relatively expensive components; in one embodiment, CTLE 100 is an integrated circuit fabricated on a silicon substrate, and inductors 131 and 132 typically occupy a large layout area. Second, in the presence of common-mode noise, the common-mode voltage of the two input voltages V I+ and V I- may drop. Due to the finite output impedance of current source 140, the two bias currents I bias+ and I bias- will also drop, which will cause the gain of CTLE 100 to drop.

[0004] There is a need in the art for a CTLE that can save layout area and is highly insensitive to common-mode noise. SUMMARY OF THE INVENTION

[0005] One object of the present disclosure is to provide a continuous-time linear equalizer that has the advantages of a compact layout and high immunity to common-mode noise.

[0006] One embodiment of the continuous-time linear equalizer of the present disclosure includes: a common-source amplifier for receiving an input signal according to a bias current and outputting an output signal; a current source controlled by a first bias voltage and for outputting the bias current; an active load controlled by a second bias voltage and serving as a load of the common-source amplifier; a common-mode sensing circuit for sensing a common-mode voltage of the output signal; a current source controller for outputting the first bias voltage according to the common-mode voltage and a reference voltage, wherein the reference voltage is derived from a supply voltage of the active load and a first reference current; and an active load controller for outputting the second bias voltage according to the supply voltage of the active load and a second reference current.

[0007] The features, implementation, and technical effects of the present invention will be described in detail in the preferred embodiments with reference to the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram showing a known continuous-time linear equalizer;

[0009] Figure 2 A schematic diagram showing a continuous-time linear equalizer according to an embodiment of the present disclosure; and

[0010] Figure 3 Showing Figure 2 The simulation result of the gain of the continuous-time linear equalizer.

[0011] Symbol Explanation

[0012] 100: Continuous-Time Linear Equalizer

[0013] 110: Bias Voltage Generator

[0014] 111: Diode-Connected NMOS Transistor

[0015] I REF : Reference Current

[0016] V B : Bias Voltage

[0017] 120: Common-Source Amplifier

[0018] 121, 122: NMOS Transistors

[0019] V I+ 、V I- : Input Voltage

[0020] V O+ 、V O- : Output Voltage

[0021] 130: Load Circuit

[0022] : Inductors

[0023] 133, 134: Resistors

[0024] V DD : Power Supply Node

[0025] 140: Current Source

[0026] 141, 142: NMOS Transistors

[0027] I bias+ 、I bias- : Bias Current

[0028] 150: Source Degeneration Circuit

[0029] 151: Resistor

[0030] 152: Capacitor

[0031] 200: Continuous-Time Linear Equalizer

[0032] 201: Source Node

[0033] 202: Source Node

[0034] 210: Current Source Controller

[0035] 211: Operational Amplifier

[0036] 212: Capacitor

[0037] R ref1 : Reference resistor

[0038] V DD : Supply voltage

[0039] V CMR : Reference voltage

[0040] I ref1 : First reference current

[0041] V B1 : First bias voltage

[0042] 220: Common-source amplifier

[0043] 221: NMOS transistor

[0044] 222: NMOS transistor

[0045] V 1+ : First input voltage

[0046] V 1- : Second input voltage

[0047] 230: Active load

[0048] 231: First active inductor

[0049] 232: Second active inductor

[0050] 233: Gate resistor

[0051] 234: Gate resistor

[0052] 235: Gate-to-drain capacitance

[0053] 236: Gate-to-drain capacitance

[0054] M1: NMOS transistor

[0055] M2: NMOS transistor

[0056] 240: Current source

[0057] 241: NMOS transistor

[0058] 241: NMOS transistor

[0059] 250: Source degeneration circuit

[0060] 251: Resistor

[0061] 252: Capacitor

[0062] I B+ : First bias current

[0063] I B- : Second bias current

[0064] 260: Common-mode sensing circuit

[0065] 261: Resistor

[0066] 262: Resistor

[0067] V CM : Common-mode voltage

[0068] V 2+ : First output voltage

[0069] V 2- : Second output voltage

[0070] 270: Active load controller

[0071] 275: Capacitor

[0072] M0: NMOS transistor

[0073] R ref2 : Resistor

[0074] I ref2 : Second reference current

[0075] V B2 : Second bias voltage Detailed implementation manners

[0076] This disclosure relates to a continuous-time linear equalizer (CTLE). Although this specification discloses that multiple embodiments of this disclosure can be regarded as preferred examples for implementing the present invention, the present invention can be implemented in various ways, not limited to the specific examples described hereinafter, nor to the specific ways of the technical features used to implement those specific examples. In other cases, known details are not shown or described to avoid obscuring the viewpoints presented in this disclosure.

[0077]

[0078] ​Those skilled in the art can understand the microelectronics-related terms and basic concepts used in this disclosure, such as "voltage", "signal", "common mode", "gain", "bias", "power flow", "impedance", "direct current (DC)", "operational amplifier", "inductor", "capacitor", "resistor", "common-source amplifier", "load", "source degeneration", "parallel connection", "circuit node", "ground", "power supply", "MOS (metal-oxide semiconductor)", "CMOS (complementary metal-oxide semiconductor) process", "NMOS (n-channel metal-oxide semiconductor) transistor", and "PMOS (p-channel metal-oxide semiconductor) transistor". Such terms and basic concepts are used in microelectronics articles and are obvious to those skilled in the art, so their details are omitted here.

[0079] Those skilled in the art can understand the units mentioned in this specification without explanation, such as nH (nano-Henry), pF (pico-Farad), fF (femto-Farad), and μm (micron).

[0080] Those skilled in the art can understand circuit diagrams containing electronic components such as capacitors, resistors, NMOS transistors, PMOS transistors, etc., and do not require redundant explanations to indicate how a certain component in the figure is connected to another component. Those skilled in the art can also recognize a ground symbol, a capacitor symbol, an inductor symbol, a resistor symbol, an operational amplifier symbol, the symbols of PMOS transistors and NMOS transistors, and can recognize the "source terminal", "gate terminal", and "drain terminal" of MOS transistors. Regarding MOS transistors, for the sake of simplicity, in the following description, the "source terminal" will be abbreviated as "source", the "gate terminal" will be abbreviated as "gate", and the "drain terminal" will be abbreviated as "drain".

[0081] A MOS transistor, PMOS transistor, or NMOS transistor has a threshold voltage. When the gate-to-source voltage of a MOS transistor is greater than its threshold voltage (in absolute value), the MOS transistor is turned on. When a MOS transistor is turned on, the absolute value of the difference between the gate-to-source voltage and the threshold voltage is called the "over-drive voltage". When a MOS transistor is turned on and its over-drive voltage is less than its drain-to-source voltage (in absolute value), the MOS transistor is in a "saturation region". A MOS transistor is only an effective gain element when it is in the "saturation region".

[0082] A circuit is an assembly of a transistor, a resistor, an inductor, a capacitor, and / or other electronic devices interconnected in a specific manner to perform a specific function.

[0083] In the present disclosure, when the meaning of a "circuit node" can be clearly understood from the context, the "circuit node" is often abbreviated as "node".

[0084] A signal is a voltage with variable levels that carries specific information and can vary with time. At a certain instant, the level of the signal represents the state of the signal at that instant. In the present disclosure, "signal" and "voltage signal" refer to the same thing, and thus the two terms are interchangeable.

[0085] In the present disclosure, a differential signal architecture is widely used. When implementing a differential signal architecture, a signal includes two voltages represented by the suffixes "+" and "-" in subscript form, and the value of the signal represents the difference between the two voltages. For example, a signal V1(V2) in a differential signal embodiment includes two voltages V 1+ (V 2+ ) and V 1- (V 2- ), and the value of the signal V1(V2) represents the difference between the two voltages V 1+ (V 2+ ) and V 1- (V 2- ). The voltage V 1+ (V 2+ ) is called the first-end signal of the signal V1(V2), and the voltage V 1- (V 2- ) is called the second-end signal of the signal V1(V2). The first-end signal is also called the positive-end signal, and the second-end signal is also called the negative-end signal. In a differential signal embodiment, the average value of the first-end signal and the second-end signal of a signal is called the "common-mode" voltage of the signal.

[0086] Figure 2 A schematic diagram showing a CTLE 200 according to an embodiment of the present disclosure. CTLE 200 includes: a common-source amplifier 220 for receiving a first signal V1 (in a differential signal embodiment, the first signal V1 includes two input voltages, including a first input voltage V B and outputting a second signal V2 (in a differential signal embodiment, the second signal V2 includes two output voltages, including a first output voltage V 1+ and a second input voltage V 1- ) according to a bias current I 1+ and a second input voltage V 1- ) and outputting a second signal V2 (in a differential signal embodiment, the second signal V2 includes two output voltages, including a first output voltage V2+ with a second output voltage V 2- ), wherein the bias current I B comprises two bias currents, including a first bias current I B+ and a second bias current I B- ; a current source 240 for generating the two bias currents I B1 under the control of a first bias voltage V B+ 、I B- ; a source degeneration circuit 250 for degenerating the common-source amplifier 220; an active load 230 receiving a supply voltage V DD and controlled by a second bias voltage V B2 and used as a load of the common-source amplifier 220; a common-mode sensing circuit 260 for sensing a common-mode voltage V CM of the second signal V2; a current source controller 210 for outputting the first bias voltage V CM based on the difference between the common-mode voltage V CMR and a reference voltage V B1 , wherein the reference voltage V CMR is derived from the supply voltage V DD and a first reference current I ref1 ; and an active load controller 270 for outputting the second bias voltage V DD based on the supply voltage V ref2 and a second reference current I B2 .

[0087] The common-source amplifier 220 includes two NMOS transistors 221, 222 which are respectively used to receive V B+ , I B- , receive V 1+ , V 1- and output V 2- , V 2+ according to the bias currents I B1 . The current source 240 includes two NMOS transistors 241, 242 and is used to respectively output the two bias currents I B+ , I B-。The source attenuation circuit 250 includes a resistor 251 and a capacitor 252 connected in parallel, which are coupled between two source nodes 201 and 202. The source node 201 is coupled to the source of the NMOS transistor 221 and the drain of the NMOS transistor 241, and the source node 202 is coupled to the source of the NMOS transistor 222 and the drain of the NMOS transistor 242. The active load 230 includes a first active inductor 231 and a second active inductor 232; the first active inductor 231 includes an NMOS transistor M1, a gate resistor 233 and a gate-to-source capacitor 235; the second active inductor 232 includes an NMOS transistor M2, a gate resistor 234 and a gate-to-source capacitor 236. The resistor 233 (234) is called a gate resistor because it is coupled to the gate of the NMOS transistor M1 (M2); the capacitor 235 (236) is called a gate-to-source capacitor because it is coupled from the gate of the NMOS transistor M1 (M2) to the source of the NMOS transistor M1 (M2). Since "an NMOS transistor together with a gate resistor and a gate-to-source capacitor can implement an active inductor" is prior art, it will not be described in detail herein.

[0088] The second bias voltage V B2 biases the active inductors 231 and 232 via the gate resistors 233 and 234 respectively. To enable the active inductors 231 and 232 to effectively act as an inductive load, the NMOS transistors M1 and M2 need to be continuously in the saturation region. To keep the two NMOS transistors M1 and M2 continuously in the saturation region, the second bias voltage V B2 should be appropriately controlled to ensure that a drain-to-source voltage is greater than an overdrive voltage. The above control can be achieved by the active load controller 270. The active load controller 270 includes an NMOS transistor M^0, a resistor R ref2 and a capacitor 275. The resistor R ref2 is disposed between the drain and the gate of the NMOS transistor M^0, and the source of the NMOS transistor M^0 is coupled to the supply voltage V DD . The second bias voltage V B2 is tapped from the drain of the NMOS transistor M^0 and maintained by the capacitor 275. In the above manner, the second bias voltage V B2 is a step up higher than the supply voltage, and the amount of the step up is determined by the second reference current I ref2 and the resistor R ref2 . The second reference current I ref2 flows through the resistor R ref2 to the drain of the NMOS transistor M^0, and a drain-to-source voltage V ds0It can be expressed as follows:

[0089] V ds0 = V th0 + V od0 - I ref2 R ref2 (1)

[0090] In formula (1), V th0 and V od0 respectively represent a threshold voltage and an overdrive voltage of the NMOS transistor M0.

[0091] In one embodiment, I ref2 R ref2 ≤ V th0 , and it can be clearly known from formula (1) that V ds0 ≥ V od0 , and the NMOS transistor M0 can continuously be in the saturation region.

[0092] The second bias voltage V B2 can be expressed as follows:

[0093] V N2 = V DD + V ds0 = V DD + V th0 + V od0 - I ref2 R ref2 (2)

[0094] The common-mode sensing circuit 260 includes two identical resistors 261 and 262, which are arranged between V 2- and V 2+ . Therefore, the common-mode voltage V CM will be equal to the average of V 2- and V 2+ . In a zero-input scenario, V 1+ and V 1- are both equal to a common-mode direct current (DC) voltage, V 2+ and V 2- are both equal to the common-mode voltage V CM . The drain-to-source voltage V ds1 of the NMOS transistor M1 and the drain-to-source voltage V ds2 of the NMOS transistor M2 are both equal to V DD - V CM , that is:

[0095] V ds1 = V ds2 = V DD - V CM (3)

[0096] By using the current source controller 210, the common-mode voltage V CM is adjusted in a closed-loop manner to approximate the reference voltage V CMR . The current source controller 210 includes an operational amplifier 211, a reference resistor R ref1 and a capacitor 212. The first reference current I ref1 flows from the supply voltage V DD through the reference resistor R ref1 to establish the reference voltage V CMR , and the reference voltage V CMR is lower than the supply voltage V DD by a voltage amount of I ref1 R ref1 , that is:

[0097] V CMR = V DD - I ref1 R ref1 (4)

[0098] The operational amplifier 211 amplifies the difference between the common-mode voltage V CM and the reference voltage V CMR to generate the first bias voltage V B1 , which is maintained by the capacitor 212. When the common-mode voltage V CM rises (falls), the operational amplifier 211 raises (lowers) the first bias voltage V B1 , and causes the two bias currents I B+ , I B- to increase (decrease), thereby reducing (raising) the two voltages V 2- , V 2+ , and thus reducing (raising) the common-mode voltage V CM . Therefore, the common-mode voltage V CM can be adjusted in a negative feedback manner to approximate the reference voltage V CMR . According to Equation (4) and the understanding that the common-mode voltage V CM [[ID=6�]]approximates the reference voltage V CMR , in a steady state of the aforementioned zero-input scenario, the drain-to-source voltage V ds1 of the NMOS transistor M1 and the drain-to-source voltage V ds2 of the NMOS transistor M2 are both equal to I ref1 R ref1 , that is:

[0099]

[0100] The overdrive voltage V of the NMOS transistor M1od1 It can be expressed as follows:

[0101] V od1 = V B2 - V CM - V th1 (6)

[0102] In Equation (6), V th1 represents a threshold voltage of the NMOS transistor M1. According to Equations (2) and (6), the following equation can be obtained:

[0103] V od1 = V DD + V th0 + V od0 - I ref2 R ref2 - V CM - V th1 (7)

[0104] In an embodiment, the NMOS transistors M0, M1, and M2 all have the same channel length and substantially the same threshold voltage. Therefore, Equation (7) can be simplified as follows:

[0105] V od1 = V DD + V od0 - I ref2 R ref2 - V cM (8)

[0106] According to Equations (5) and (8), the following equation can be obtained:

[0107] V od1 = V od0 + I ref1 R ref1 - I ref2 R ref2 (9)

[0108] The condition for the NMOS transistor M1 to be in the saturation region is V ds1 ≥ V od1 . According to Equations (5) and (9), the above condition can be summarized as follows:

[0109] I ref2 R ref2 ≥ V od0 (10)

[0110] Similarly, Equation (10) is also the condition for the NMOS transistor M2 to be in the saturation region.

[0111] In summary, the second reference current I ref2 and the resistor R ref2are appropriately selected to satisfy the following formula:

[0112] V th0 ≥I ref2 R ref2 ≥V od0 (11)

[0113] As described above, these NMOS transistors M0, M1, and M2 can all be in the saturation region.

[0114] CTLE 200 is functionally similar to CTLE 100, that is, a higher-frequency input signal will have a higher gain because, for this input signal, the impedance of the active load 230 is higher and the impedance of the source degeneration circuit 250 is lower. However, CTLE 200 has advantages over CTLE 100. First, by using the active inductors 231, 232, the layout area can be significantly reduced. Second, the two bias currents I B+ 、I B- are controlled in a closed-loop manner. When an input common-mode voltage drops (rises) and causes the two bias currents I B+ 、I B- to drop (rise), the common-mode voltage V CM will rise (drop), and thus cause the current source controller 210 to increase (decrease) the first bias voltage V B1 , to offset / resist this change. This makes the gain of CTLE 200 insensitive to the input common-mode voltage. In addition, the active load 230 is controlled by the active load controller 270 to remain effective under process, voltage, and temperature variations.

[0115] The source degeneration circuit 250 is used to attenuate the low-frequency gain of CTLE 200, thereby relatively increasing the high-frequency gain. Since the active load 230 can also increase the high-frequency gain, if the active load 230 is sufficient to provide enough high-frequency boost, the source degeneration circuit 250 is not necessary. In one embodiment, the source degeneration circuit 250 is replaced by a short circuit; in this case, there is no source degeneration effect.

[0116] The operational amplifier is prior art and will not be described in detail here. The circuit designer can use any suitable existing operational amplifier circuit according to his judgment to implement the operational amplifier 211.

[0117] In some implementation examples that are not used to limit the present invention: CTLE 200 is fabricated on a silicon substrate using a 12-nanometer CMOS process technology; V DD is 0.9V; I ref1is 100 μA; the W / L (representing width / length) of NMOS transistors 221 and 222 is 5 μm / 16 μm; the resistance value of resistor 251 is 2 K Ohm; the capacitance value of capacitor 252 is 50 fF; the W / L of NMOS transistors 241 and 242 is 11 μm / 16 μm; the resistance values of resistors 261 and 262 are 30 K Ohm; the W / L of NMOS transistors M1 and M2 is 500 μm / 16 μm; the resistance values of resistors 233 and 234 are 6 K Ohm; the capacitance values of capacitors 235 and 256 are 5 fF; the W / L of NMOS transistor M0 is 500 μm / 16 μm; the resistance of resistor R ref2 is 2 K Ohm; the capacitance value of capacitor 275 is 30 pF; the resistance of resistor R ref1 is 3 K Ohm; and the capacitance value of capacitor 212 is 10 pF. An analog result of the gain of CTLE 200 is as shown in Figure 3 : at frequencies (freq(Hz)) of 40 MHz and 20 GHz, the gains (V(dB)) are -4.97 dB and 16.1 dB respectively, and an equalization function is clearly achieved.

[0118] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by what is defined in the claims of this specification.

Claims

1. A continuous-time linear equalizer, comprising: A common-source amplifier for receiving an input signal and outputting an output signal according to a bias current; A current source controlled by a first bias voltage and for outputting the bias current; An active load controlled by a second bias voltage and serving as a load of the common-source amplifier; A common-mode sensing circuit for sensing a common-mode voltage of the output signal; A current source controller for outputting the first bias voltage according to the common-mode voltage and a reference voltage, wherein the reference voltage is derived from a supply voltage of the active load and a first reference current; and An active load controller for outputting the second bias voltage according to the supply voltage of the active load and a second reference current.

2. The continuous-time linear equalizer according to claim 1, wherein the continuous-time linear equalizer uses a differential signal architecture, the input signal includes a first input voltage and a second input voltage, and the output signal includes a first output voltage and a second output voltage.

3. The continuous-time linear equalizer according to claim 2, wherein the bias current includes a first bias current and a second bias current.

4. The continuous-time linear equalizer according to claim 3, wherein the common-source amplifier includes two n-channel metal-oxide-semiconductor transistors, and the two n-channel metal-oxide-semiconductor transistors are respectively for receiving the first input voltage and the second input voltage and outputting the second output voltage and the first output voltage according to the first bias current and the second bias current.

5. The continuous-time linear equalizer according to claim 4, wherein the current source includes two other n-channel metal-oxide-semiconductor transistors, and the two other n-channel metal-oxide-semiconductor transistors are for outputting the first bias current and the second bias current according to the first bias voltage.

6. The continuous-time linear equalizer according to claim 2, wherein the common-mode sensing circuit includes two resistors connected in series, the two resistors are disposed between the first output voltage and the second output voltage, and the common-mode voltage is connected to a connection point of the two resistors.

7. The continuous-time linear equalizer according to claim 2, further comprising a source degeneration circuit for degenerating the common-source amplifier to reduce a low-frequency gain of the common-source amplifier.

8. The continuous-time linear equalizer according to claim 1, wherein the current source controller includes a resistor, an operational amplifier and a capacitor; the first reference current flows through the resistor from the supply voltage of the active load to establish the reference voltage; the operational amplifier is for amplifying a difference between the common-mode voltage and the reference voltage to generate the first bias voltage; and the capacitor is for holding the first bias voltage.

9. The continuous-time linear equalizer as claimed in claim 1, wherein the active load controller includes an n-channel metal oxide semiconductor transistor, a resistor, and a capacitor; the n-channel metal oxide semiconductor transistor is used to increase the supply voltage of the active load to generate the second bias voltage; The resistor is for allowing the second reference current to flow into the n-channel metal-oxide-semiconductor transistor and for controlling an amount by which the supply voltage is increased; and the capacitor is for holding the second bias voltage.

10. The continuous-time linear equalizer as claimed in claim 1, wherein the active load includes an active inductor; the active inductor includes an n-channel metal oxide semiconductor transistor, a gate resistor, and a gate-to-source capacitor; a source of the n-channel metal oxide semiconductor transistor is coupled to the common-source amplifier, a drain of the n-channel metal oxide semiconductor transistor is coupled to the supply voltage, and a gate of the n-channel metal oxide semiconductor transistor is coupled to the second bias voltage via the gate resistor; and the gate-to-source capacitor is disposed between the gate and the source of the n-channel metal oxide semiconductor transistor.

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