Synchronous data processing method and device

Abstract

The present application discloses a synchronous data processing method and apparatus, comprising: first acquiring a first synchronous training signal and a second synchronous training signal having the same phase frequency, and sampling them respectively through a first ADC and a second ADC to obtain a first training sampling signal and a second training sampling signal, respectively; then performing multiple delay operations on at least one of the first training sampling signal and the second training sampling signal, and calculating the delay difference between the first training sampling signal and the second training sampling signal after the multiple delay operations; and finally, correcting at least one of the first ADC and the second ADC based on the minimum value of the delay differences to achieve synchronous sampling, thereby resolving the technical problem of data lag relationship between different channels, ensuring that the data collected simultaneously from different channels is synchronous data, and being able to more clearly, comprehensively, and accurately reflect the waveform details of the measured object.

Description

Technical Field

[0001] The present application relates to the field of data acquisition technology, and in particular to a synchronous data processing method and device. Background Art

[0002] Electronic measurement refers to various electrical and non-electrical measurements of the object being measured using electronic technology. With the rapid advancement of technology, a key development direction for the electronic measurement industry is to be able to more clearly, comprehensively, and accurately reflect the waveform details of the object being measured.

[0003] With the development of multi-measurement integration technology in the current electronic measurement industry, the synchronous acquisition of multi-channel data will directly affect the accurate reflection of the waveform details of the measured object. Therefore, it is particularly important to be able to accurately and synchronously acquire different types of measured signals under multiple channels. Currently, when acquiring different types of measured signals under multiple channels, existing technologies often directly acquire multi-channel data simultaneously. However, the data collected from different channels often lags behind, resulting in the data collected from different channels being out of sync, which in turn affects the accurate reflection of the waveform details of the measured object.

[0004] Therefore, due to the lack of existing technical means, a synchronous data processing method is urgently needed to reduce the lag relationship between data under different channels and ensure that the data under different channels collected simultaneously are synchronized data. Summary of the Invention

[0005] The present application provides a synchronous data processing method and device to ensure that data collected simultaneously from different channels are synchronized data.

[0006] In one aspect, a synchronous data processing method is provided, the method comprising:

[0007] Acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency;

[0008] Sampling the first synchronous training signal through the first ADC to obtain a first training sampling signal;

[0009] Sampling the second synchronous training signal through the second ADC to obtain a second training sampling signal;

[0010] performing multiple delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculating delay differences between the first training sample signal and the second training sample signal after the multiple delay operations;

[0011] At least one of the first ADC and the second ADC is calibrated according to a minimum value of the delay differences, so that the first ADC and the second ADC can sample synchronously.

[0012] In another aspect, a synchronous data processing device is provided, the device comprising:

[0013] A synchronous training signal acquisition module, configured to acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency;

[0014] A first training sampling signal acquisition module is used to sample the first synchronous training signal through the first ADC to obtain a first training sampling signal;

[0015] A second training sampling signal acquisition module is used to sample the second synchronous training signal through the second ADC to obtain a second training sampling signal;

[0016] a delay difference acquisition module, configured to perform multiple delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculate the delay difference between the first training sample signal and the second training sample signal after the multiple delay operations;

[0017] The correction module is configured to correct at least one of the first ADC and the second ADC according to a minimum value of the delay differences, so that the first ADC and the second ADC perform sampling synchronously.

[0018] In a possible implementation, the delay difference acquisition module includes:

[0019] a first delayed signal acquiring unit, configured to delay the first training sample signal for a first specified time to obtain a first delayed signal;

[0020] a second delayed signal acquiring unit, configured to perform a plurality of delay operations on the second training sample signal according to a second specified time to obtain respective second delayed signals, until the second training sample signal is delayed to a set end time;

[0021] a delay difference acquiring unit, configured to calculate differences between the first delayed signal and each of the second delayed signals, and determine the differences between the first delayed signal and each of the second delayed signals as delay differences between the first training sample signal and the second training sample signal after multiple delay operations.

[0022] In a possible implementation, the second training sample signal is delayed multiple times, with the second designated time being the first delay and subsequent delays being performed by gradually increasing the preset time based on the second designated time, to obtain the first and subsequent second delayed signals.

[0023] In one possible implementation, the second specified time has a value range of 0 to the first specified time; the added preset time has a value range of 0 to the first specified time; and the specified end time has a value range of 1 to 3 times the first specified time.

[0024] In a possible implementation manner, the delay difference acquiring unit is further configured to:

[0025] For each second delayed signal, split the first delayed signal into a target number of first signed data, and split the second delayed signal into a target number of second signed data; the first signed data and the second signed data correspond one to one;

[0026] Normalizing each of the first signed data and each of the second signed data;

[0027] performing a difference operation on each normalized first signed data and the corresponding normalized second signed data, and obtaining an absolute value of each difference;

[0028] The absolute values ​​of the respective differences are summed to obtain a sum of the absolute values, and the sums of the respective absolute values ​​are respectively determined as the differences between the first delayed signal and the respective second delayed signals.

[0029] In one possible embodiment, the device is further used for:

[0030] Sequentially acquiring a difference between the first training sample signal and the second training sample signal under each delay operation;

[0031] The corresponding difference values ​​under each delay operation are compared in sequence to obtain a minimum difference value, and the minimum difference value is determined as the minimum value among the delay differences.

[0032] In a possible implementation, the correction module includes:

[0033] a minimum value delay times acquisition unit, configured to acquire a delay time corresponding to the number of delay operations of the second training sample signal corresponding to the minimum value;

[0034] The calibration unit is configured to calibrate at least one of the first ADC and the second ADC based on a delay time corresponding to the number of delay operations and the first specified time.

[0035] In a possible implementation, the correction unit is further configured to:

[0036] When the delay time corresponding to the number of delay operations is greater than the first specified time, calibrating the second ADC based on a difference between the delay time corresponding to the number of delay operations and the first specified time;

[0037] When the delay time corresponding to the number of delay operations is less than the first specified time, the first ADC is calibrated based on a difference between the first specified time and the delay time corresponding to the number of delay operations.

[0038] In one possible embodiment, the device is further used for:

[0039] Acquiring a target waveform data signal: Based on the target waveform data signal, acquiring two synchronous training signals with the same phase frequency, and determining the two synchronous training signals with the same phase frequency as a first synchronous training signal and a second synchronous training signal, respectively.

[0040] The technical solution provided by this application may have the following beneficial effects:

[0041] Before synchronous data sampling is performed through the first ADC and the second ADC, a first synchronous training signal and a second synchronous training signal with the same phase frequency are first obtained, and the first synchronous training signal is sampled by the first ADC to obtain a first training sampling signal, and the second synchronous training signal is sampled by the second ADC to obtain a second training sampling signal; then, multiple delay operations are performed on at least one of the first training sampling signal and the second training sampling signal, and the delay difference between the first training sampling signal and the second training sampling signal after the multiple delay operations is respectively calculated. At this time, at least one of the first training sampling signal and the second training sampling signal in the multiple delay operations is A time delay occurs on one of the signals, that is, a time delay is performed on at least one of the first training sampling signal and the second training sampling signal, and the signal is compared with the other signal. A minimum value among the compared delay differences indicates that after the delay operation corresponding to the minimum value is performed, the first training sampling signal is closest to the second training sampling signal. Therefore, after correcting at least one of the first ADC and the second ADC based on the minimum value of the delay difference, the first ADC and the second ADC can be sampled synchronously, thereby reducing the lag relationship between data in different channels and obtaining the best state of data synchronization in different channels, thereby ensuring that the data in different channels collected simultaneously are synchronized data. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 The figure is a schematic structural diagram of a synchronous data processing system according to an exemplary embodiment.

[0044] Figure 2 The figure is a flowchart of a synchronous data processing method according to an exemplary embodiment.

[0045] Figure 3 The figure is a flowchart of a synchronous data processing method according to an exemplary embodiment.

[0046] Figure 4 The figure is a flowchart showing a delay operation according to an exemplary embodiment.

[0047] Figure 5 The figure is a schematic diagram of a process for determining a delay difference according to an exemplary embodiment.

[0048] Figure 6 The figure is a schematic diagram of a process for determining a minimum value according to an exemplary embodiment.

[0049] Figure 7 The figure is a structural block diagram of a synchronous data processing device according to an exemplary embodiment. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solution of this application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0051] It should be understood that the "indication" mentioned in the embodiments of this application can be a direct indication, an indirect indication, or an indication of an association. For example, "A indicates B" can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, and B can be obtained through C; it can also mean that there is an association between A and B.

[0052] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between the two, or an association relationship between the two, or a relationship between indication and being indicated, configuration and being configured, etc.

[0053] Figure 1 FIG1 is a structural diagram of a synchronous data processing system according to an exemplary embodiment. The synchronous data processing system includes a control chip, a signal acquisition chip 1 and a signal acquisition chip 2.

[0054] Optionally, the control core can be an FPGA. FPGA (Field Programmable Gate Array) is a product further developed based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). The FPGA can generate a fixed square wave waveform signal to provide signal acquisition chip 1 and signal acquisition chip 2 with a synchronous training signal with the same frequency for synchronous training.

[0055] Optionally, the signal acquisition chip 1 and the signal acquisition chip 2 can be the first ADC and the second ADC respectively. The first ADC and the second ADC are analog-to-digital converters that can convert analog signals generated in the real world (such as temperature, pressure, sound, fingerprints or images, etc.) into digital forms that are easier to process, and are used for data acquisition of square wave waveform signals generated by the FPGA and external sampling signals.

[0056] Optionally, the first ADC and the second ADC may not collect data synchronously, and there may be a certain lag between the two data paths, resulting in the collected data being out of sync. Since the FPGA generates a fixed square wave waveform signal, it can ensure that the training data collected by the first ADC and the second ADC are exactly the same. Therefore, there will only be a lag between the two data paths collected by the first ADC and the second ADC. After the synchronous training process, the first ADC and the second ADC are guaranteed to achieve synchronous sampling, and the first ADC and the second ADC can then collect the external sampling signal to achieve synchronous sampling of the external sampling signal.

[0057] Optionally, in order to achieve high-speed and high-precision data acquisition, the first ADC and the second ADC can adopt a high-speed analog-to-digital conversion chip with a sampling rate of up to 3G and a resolution of 12 bits. The first ADC and the second ADC are used to realize the acquisition of two channels of data, meeting the needs of multi-channel data acquisition.

[0058] Optionally, if the first ADC and the second ADC acquire the same square wave signal generated by the FPGA, and if the signals acquired by the first ADC and the second ADC are synchronized, the ideal result of the difference operation between the two data channels will be 0. However, if there is a lag between the two signals, the difference operation result will not be 0. In practice, it is difficult to achieve a difference of 0, so the minimum value of the difference operation results is found, and this state is considered to be the state of optimal synchronization between the two signals.

[0059] Figure 2 FIG. 1 is a flow chart showing a method for synchronous data processing according to an exemplary embodiment. Figure 2 As shown, the synchronous data processing method may include the following steps:

[0060] Step S201: Acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency.

[0061] In one possible implementation, to ensure that the two signals collected by the first ADC and the second ADC are synchronized data, the first ADC and the second ADC need to be trained and calibrated using training signals. During training, it is necessary to ensure that the training signals collected by the first ADC and the second ADC are identical (i.e., have the same phase and frequency) synchronized training signals to accurately determine the lag relationship between the two signals collected by the first ADC and the second ADC. Therefore, a fixed square wave waveform signal can be generated by an FPGA, and two identical synchronized training signals, i.e., a first synchronized training signal and a second synchronized training signal, can be obtained based on the square wave waveform signal.

[0062] Step S202: Sample the first synchronous training signal through the first ADC to obtain a first training sampling signal.

[0063] In a possible implementation, after acquiring the first synchronous training signal and the second synchronous training signal with the same phase frequency, the first synchronous training signal is sampled by the first ADC according to the target sampling condition, and the sampling result is the first training sampling signal.

[0064] Optionally, since the first synchronous training signal and the second synchronous training signal are substantially the same square wave signal, the target sampling condition may be to perform instantaneous sampling at each rising edge of the first synchronous training signal and the second synchronous training signal.

[0065] Step S203: Sample the second synchronous training signal through the second ADC to obtain a second training sampling signal.

[0066] In a possible implementation, the second synchronous training signal is sampled by the second ADC according to the target sampling condition, and the sampling result is the second training sampling signal.

[0067] Step S204 , performing multiple delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculating delay differences between the first training sample signal and the second training sample signal after the multiple delay operations.

[0068] In one possible implementation, after a first ADC acquires a first training sample signal and a second ADC acquires a second training sample signal, synchronization training is performed on the first ADC and the second ADC based on the two training sample signals. During the synchronization training, multiple delay operations are performed on the first training sample signal and the second training sample signal. After the multiple delay operations, delayed signals of the first training sample signal and the second training sample signal are obtained (i.e., a first training sample delayed signal and a second training sample delayed signal formed by delaying the first training sample signal and the second training sample signal, respectively). For each delay operation, a delay difference between the first training sample signal and the second training sample signal after the delay operation (i.e., the difference between the first training sample delayed signal and the second training sample delayed signal) is calculated. A larger delay difference indicates a greater lag between the first and second ADC signals, and the more out of sync the two signals are. Conversely, a smaller delay difference indicates a smaller lag between the first and second ADC signals, and the closer the two signals are to synchronization.

[0069] Step S205 : Calibrate at least one of the first ADC and the second ADC according to the minimum value of the delay differences, so that the first ADC and the second ADC perform sampling synchronously.

[0070] In one possible implementation, after obtaining the delay differences, a minimum value is determined from the delay differences. When the delay difference is the minimum, it indicates that the synchronization state of the signals from the first ADC and the second ADC is optimal, with the hysteresis relationship minimized and the signals closest to synchronization. Therefore, after obtaining the minimum delay difference, the first ADC and the second ADC can be calibrated based on the parameters of the delay operation when the delay difference is the minimum, completing synchronization training and ensuring synchronous sampling between the first ADC and the second ADC.

[0071] In another possible implementation, after the first ADC acquires the first training sample signal and the second ADC acquires the second training sample signal, multiple delay operations may be performed on one of the first and second training sample signals. Calibration of the first and second ADCs may then be performed based on the minimum delay difference obtained after the delay operations. For example, after multiple delay operations are performed on the first training sample signal, multiple first delayed signals may be obtained, each corresponding to a different time delay. Each first delayed signal may then be compared with the second training sample signal to determine the delay difference between the first and second training sample signals. Calibration of the first ADC may then be performed based on the minimum delay difference.

[0072] Furthermore, when the delay difference obtained by comparing the first delayed signal with the second training sampled signal increases as the time delay corresponding to the first delayed signal increases, the first ADC is not calibrated at this time, and instead multiple delay operations are performed on the second training sampled signal to obtain each second delayed signal. Each second delayed signal is then compared with the first training sampled signal to determine the delay difference between each second delayed signal and the first training sampled signal, and the second ADC is calibrated based on the minimum delay difference.

[0073] In summary, before synchronous data sampling is performed through the first ADC and the second ADC, a first synchronous training signal and a second synchronous training signal with the same phase frequency are first obtained, and the first synchronous training signal is sampled by the first ADC to obtain a first training sampling signal, and the second synchronous training signal is sampled by the second ADC to obtain a second training sampling signal; then, multiple delay operations are performed on at least one of the first training sampling signal and the second training sampling signal, and the delay difference between the first training sampling signal and the second training sampling signal after the multiple delay operations is respectively calculated. At this time, the delay difference between the first training sampling signal and the second training sampling signal in the multiple delay operations is At least one of the first ADC and the second ADC is delayed, that is, at least one of the first training sampling signal and the second training sampling signal is delayed and compared with the other, and the minimum value of the compared delay differences indicates that after the delay operation corresponding to the minimum value is performed, the first training sampling signal and the second training sampling signal are closest to each other. Therefore, after correcting at least one of the first ADC and the second ADC based on the minimum value of the delay difference, the first ADC and the second ADC can be sampled synchronously, thereby reducing the lag relationship between data in different channels and obtaining the best state of data synchronization in different channels, so as to ensure that the data in different channels collected simultaneously are synchronized data.

[0074] Figure 3FIG. 1 is a flow chart showing a method for synchronous data processing according to an exemplary embodiment. Figure 3 As shown, the synchronous data processing method may include the following steps:

[0075] Step S301: Acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency.

[0076] In a possible implementation, the target waveform data signal is obtained based on the target waveform data signal, two synchronous training signals with the same phase frequency are obtained, and the two synchronous training signals with the same phase frequency are respectively determined as the first synchronous training signal and the second synchronous training signal.

[0077] Furthermore, in order to perform synchronous training, two channels can be provided, one channel being a training channel and the other data channel being an acquisition channel. Before performing synchronous training, the FPGA issues a training instruction and the training channel operates. At this time, the FPGA generates a fixed square wave waveform signal and, based on the fixed square wave waveform signal, generates a first synchronous training signal and a second synchronous training signal with the same phase frequency. The first ADC and the second ADC acquire the first synchronous training signal and the second synchronous training signal through the training channel to achieve synchronous training. After synchronous training, the FPGA issues an external acquisition instruction and the acquisition channel operates. At this time, the first ADC and the second ADC can achieve synchronous acquisition of the external sampling signal through the acquisition channel.

[0078] Step S302: Sample the first synchronous training signal through the first ADC to obtain a first training sampling signal.

[0079] In one possible implementation, after acquiring the first synchronous training signal and the second synchronous training signal, the first synchronous training signal is sampled through the first ADC according to the target sampling condition (the target sampling condition may be instantaneous sampling at each rising edge of the first synchronous training signal and the second synchronous training signal), and the sampling result is the first training sampling signal.

[0080] Optionally, taking the FPGA operating at a frequency of 187.5 MHz and the ADC sampling rate of 3 GHz as an example, each time a rising edge of the FPGA comes, the first ADC and the second ADC output 16 sampling points (that is, each time a rising edge of the FPGA comes, the first ADC and the second ADC perform one acquisition, sampling 16 sampling points each time). Since the number of bits of the first ADC and the second ADC is 12 bits, the data sampled each time can be combined to form data with a bit width of 192 bits.

[0081] Step S303: Sample the second synchronous training signal through the second ADC to obtain a second training sampling signal.

[0082] In a possible implementation, since the first ADC and the second ADC need to perform data synchronous sampling simultaneously, the second ADC needs to sample the second synchronous training signal to obtain the second training sampling signal while the first ADC samples the first synchronous training signal to obtain the first training sampling signal.

[0083] Step S304: delay the first training sample signal for a first specified time to obtain a first delayed signal.

[0084] In one possible implementation, after the first ADC acquires the first training sample signal and the second ADC acquires the second training sample signal, in order to determine the hysteresis relationship between the two channels of data (the first training sample signal and the second training sample signal) acquired by the first ADC and the second ADC, the 192 bits acquired by the first ADC and the second ADC must first be transmitted to a delay module for a delay operation.

[0085] For example, please refer to Figure 4 The delay operation flow diagram shown in the figure assumes that two data channels require delay: channel A (the first training sample signal) and channel B (the second training sample signal). During the delay operation, channel A is first delayed by a fixed time (X) (a first specified time) to obtain a first delayed signal (i.e., the first training sample signal formed by delaying the first training sample signal).

[0086] Step S305 : performing multiple delay operations on the second training sample signal according to the second specified time to obtain respective second delayed signals, until the second training sample signal is delayed to the set end time.

[0087] In a possible implementation, the second training sample signal is delayed multiple times, with the second designated time being the first delay and subsequent delays being performed by gradually increasing the preset time based on the second designated time, to obtain the first and subsequent second delayed signals.

[0088] In one possible implementation, the value range of the second specified time is between 0 and the first specified time; the value range of the increased preset time is between 0 and the first specified time; and the value range of the specified end time is between 1 and 3 times the first specified time.

[0089] In one possible implementation, after the first training sample signal is delayed by a first specified time to obtain a first delayed signal, a second specified time is first obtained based on the first specified time, and then the second training sample signal is delayed multiple times according to the second specified time (until the delay is twice the first specified time) to obtain respective second delayed signals (i.e., second training sample delayed signals formed by delaying the second training sample signal).

[0090] For example, please refer to Figure 4 The delay operation flow diagram shown in the figure shows that after delaying data channel A for a fixed time period of X, data channel B is delayed, starting from 0 and incrementing by one each time. Each time data channel B is delayed, a difference is calculated with the data channel A, and the absolute value is added. The result is stored in memory, and the delay ends when the data channel B is delayed to 2*X.

[0091] Furthermore, the value range of the second specified time is between 0 and the first specified time, which can be determined as needed and is not limited. The second specified time can be specifically 0, preferably within the range of 0 to 0.1 times the first specified time, but not limited to. The value range of the added preset time is between 0 and the first specified time, which can be determined as needed and is not limited; preferably within the range of 0 to 0.1 times the first specified time, but not limited to. The value range of the specified end time is between 1 to 3 times the first specified time, which can be determined as needed and is not limited; preferably within the range of 1.5 to 2.5 times the first specified time, but not limited to.

[0092] Step S306 : Calculate the differences between the first delayed signal and each of the second delayed signals, and determine the differences between the first delayed signal and each of the second delayed signals as delay differences between the first training sample signal and the second training sample signal after multiple delay operations.

[0093] In a possible implementation, for each second delayed signal, the first delayed signal is split into a target number of first signed data, and the second delayed signal is split into a target number of second signed data; the first signed data corresponds one-to-one to the second signed data;

[0094] Normalizing each of the first signed data and each of the second signed data;

[0095] Performing a difference operation on each normalized first signed data and the corresponding normalized second signed data, and obtaining an absolute value of each difference;

[0096] The absolute values ​​of the respective differences are summed to obtain a sum of the absolute values, and the sum of the absolute values ​​is respectively determined as a difference between the first delayed signal and each second delayed signal.

[0097] For further information, please refer to Figure 5 As shown in the delay difference determination process diagram, after the delay operation is performed through the delay module to obtain the delayed A-channel data (first delayed signal) and the delayed B-channel data (second delayed signal), since the data collected each time can be combined to form a data with a bit width of 192 bits, the 192-bit data after passing through the delay module (the first delayed signal and the second delayed signal) can be split into 16 12-bit signed data, and the split 16 data are filled into the memory (the memory is a memory that can fill 16 addresses), and then the 16 signed data are normalized (the first delayed signal and the second delayed signal are normalized separately).

[0098] Furthermore, when normalizing the first delayed signal and each second delayed signal, when the data obtained by splitting the delayed signal is greater than 0, the data at that time is assigned a value of 1 and stored in the memory; when the data obtained by splitting the delayed signal is less than 0, the data at that time is assigned a value of -1 and stored in the memory. Since the first delayed signal and each second delayed signal are split into 16 12-bit signed data, the first delayed signal and each second delayed signal can be represented as 16 1s or -1s.

[0099] The same operation as above is performed on the first delayed signal of the A-channel data and each second delayed signal of the B-channel data. The two normalized data are subtracted from each other, and the absolute values ​​of the 16 data after the subtraction are added together to obtain the delay difference between the first training sample signal and the second training sample signal after multiple delay operations.

[0100] Step S307 : Calibrate at least one of the first ADC and the second ADC according to the minimum value of the delay differences, so that the first ADC and the second ADC perform sampling synchronously.

[0101] In a possible implementation, a difference between the first training sample signal and the second training sample signal under each delay operation is sequentially acquired;

[0102] The corresponding differences under each delay operation are compared in sequence to obtain a minimum difference, and the minimum difference is determined as the minimum value of the delay differences.

[0103] For further information, please refer to Figure 6The schematic diagram of the minimum value determination process shown in the figure shows the principle of finding the minimum value in the result of adding the absolute values ​​of the difference between the A-way data and the B-way data after each delay operation: first, the delay difference of the first delay of the B-way data is recorded as the minimum value, and the value is saved in a register. Then, the delay difference of the second delay of the B-way data is compared with the minimum value. If it is less than the minimum value, the result of the second delay is recorded as the minimum value. If it is greater than the minimum value, the minimum value remains unchanged at this time. Then, the delay difference of the third delay of the B-way data is compared with the current minimum value. If it is less than the minimum value, the result of the third delay is recorded as the minimum value. If it is greater than the minimum value, the minimum value remains unchanged at this time. And so on, until the delay of the B-way data ends, the one with the smallest delay difference among all the delayed data of the B-way data will be found. The situation at this time is the required B-way delay data (i.e. Figure 6 Take out the corresponding number of moves on B path).

[0104] In one possible implementation, a delay time corresponding to the number of delay operations of the second training sample signal corresponding to the minimum value is obtained; and at least one of the first ADC and the second ADC is calibrated based on the delay time corresponding to the number of delay operations and the first specified time.

[0105] In a possible implementation, when the delay time corresponding to the number of delay operations is greater than the first specified time, the second ADC is calibrated based on a difference between the delay time corresponding to the number of delay operations and the first specified time;

[0106] When the delay time corresponding to the number of delay operations is less than the first specified time, the first ADC is calibrated based on a difference between the first specified time and the delay time corresponding to the number of delay operations.

[0107] Furthermore, after each delay of the B-channel data, a difference is calculated between the data on the A-channel and the absolute value of the sum (i.e. the delay difference mentioned above), and then the minimum value of the difference between the data on the A-channel and the data on the B-channel after each delay operation is found. Figure 4 In the delay operation flow diagram shown in the figure, the data after the delay of channel B (the second delayed signal) in the current state (the state corresponding to the minimum value) is recorded as Y, and the size of Y and X is judged. If Y is greater than X at this time, the data of channel A remains unchanged, and the data of channel B is delayed by the time YX. If Y is less than X at this time, the data of channel B remains unchanged, and the data of channel A is delayed by the time XY. In this way, the synchronization of the two data channels can be guaranteed.

[0108] In summary, before synchronous data sampling is performed through the first ADC and the second ADC, a first synchronous training signal and a second synchronous training signal with the same phase frequency are first obtained, and the first synchronous training signal is sampled by the first ADC to obtain a first training sampling signal, and the second synchronous training signal is sampled by the second ADC to obtain a second training sampling signal; then, multiple delay operations are performed on at least one of the first training sampling signal and the second training sampling signal, and the delay difference between the first training sampling signal and the second training sampling signal after the multiple delay operations is respectively calculated. At this time, the delay difference between the first training sampling signal and the second training sampling signal in the multiple delay operations is At least one of the first ADC and the second ADC is delayed, that is, at least one of the first training sampling signal and the second training sampling signal is delayed and compared with the other, and the minimum value of the compared delay differences indicates that after the delay operation corresponding to the minimum value is performed, the first training sampling signal and the second training sampling signal are closest to each other. Therefore, after correcting at least one of the first ADC and the second ADC based on the minimum value of the delay difference, the first ADC and the second ADC can be sampled synchronously, thereby reducing the lag relationship between data in different channels and obtaining the best state of data synchronization in different channels, so as to ensure that the data in different channels collected simultaneously are synchronized data.

[0109] Figure 7 1 is a block diagram showing a synchronous data processing device according to an exemplary embodiment. The synchronous data processing device includes:

[0110] The synchronous training signal acquisition module 701 is configured to acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency;

[0111] A first training sample signal acquisition module 702 is configured to sample the first synchronous training signal through a first ADC to obtain a first training sample signal;

[0112] A second training sample signal acquisition module 703 is configured to sample the second synchronous training signal through a second ADC to obtain a second training sample signal;

[0113] a delay difference acquisition module 704 configured to perform multiple delay operations on at least one of the first training sample signal and the second training sample signal, and calculate delay differences between the first training sample signal and the second training sample signal after the multiple delay operations;

[0114] The correction module 705 is configured to correct at least one of the first ADC and the second ADC according to a minimum value of the delay differences, so that the first ADC and the second ADC perform sampling synchronously.

[0115] In a possible implementation, the delay difference acquisition module 704 includes:

[0116] a first delayed signal acquiring unit, configured to delay the first training sample signal for a first specified time to obtain a first delayed signal;

[0117] a second delayed signal acquiring unit, configured to perform a plurality of delay operations on the second training sample signal according to a second specified time to obtain respective second delayed signals, until the second training sample signal is delayed to a set end time;

[0118] The delay difference acquiring unit is configured to calculate the difference between the first delayed signal and each of the second delayed signals, and determine the difference between the first delayed signal and each of the second delayed signals as the delay difference between the first training sample signal and the second training sample signal after multiple delay operations.

[0119] In a possible implementation, the second training sample signal is delayed multiple times, with the second designated time being the first delay and subsequent delays being performed by gradually increasing the preset time based on the second designated time, to obtain the first and subsequent second delayed signals.

[0120] In one possible implementation, the second specified time has a value range of 0 to the first specified time; the added preset time has a value range of 0 to the first specified time; and the specified end time has a value range of 1 to 3 times the first specified time.

[0121] In a possible implementation manner, the delay difference acquiring unit is further configured to:

[0122] For each second delayed signal, split the first delayed signal into a target number of first signed data, and split the second delayed signal into a target number of second signed data; the first signed data corresponds to the second signed data one-to-one;

[0123] Normalizing each of the first signed data and each of the second signed data;

[0124] Performing a difference operation on each normalized first signed data and the corresponding normalized second signed data, and obtaining an absolute value of each difference;

[0125] The absolute values ​​of the respective differences are summed to obtain a sum of the absolute values, and the sum of the absolute values ​​is respectively determined as a difference between the first delayed signal and each second delayed signal.

[0126] In one possible embodiment, the device is further used for:

[0127] Sequentially acquiring a difference between the first training sample signal and the second training sample signal under each delay operation;

[0128] The corresponding differences under each delay operation are compared in sequence to obtain a minimum difference, and the minimum difference is determined as the minimum value of the delay differences.

[0129] In a possible implementation, the correction module 705 includes:

[0130] a minimum value delay times acquisition unit, configured to acquire a delay time corresponding to the number of delay operations of the second training sample signal corresponding to the minimum value;

[0131] The calibration unit is configured to calibrate at least one of the first ADC and the second ADC based on the number of delay operations and the first specified time.

[0132] In a possible implementation, the correction unit is further configured to:

[0133] When the delay time corresponding to the number of delay operations is greater than the first specified time, calibrating the second ADC based on a difference between the delay time corresponding to the number of delay operations and the first specified time;

[0134] When the delay time corresponding to the number of delay operations is less than the first specified time, the first ADC is calibrated based on a difference between the first specified time and the delay time corresponding to the number of delay operations.

[0135] In one possible embodiment, the device is further used for:

[0136] Acquiring a target waveform data signal: Based on the target waveform data signal, acquiring two synchronous training signals with the same phase frequency, and determining the two synchronous training signals with the same phase frequency as a first synchronous training signal and a second synchronous training signal respectively.

[0137] In summary, before synchronous data sampling is performed through the first ADC and the second ADC, a first synchronous training signal and a second synchronous training signal with the same phase frequency are first obtained, and the first synchronous training signal is sampled by the first ADC to obtain a first training sampling signal, and the second synchronous training signal is sampled by the second ADC to obtain a second training sampling signal; then, multiple delay operations are performed on at least one of the first training sampling signal and the second training sampling signal, and the delay difference between the first training sampling signal and the second training sampling signal after the multiple delay operations is respectively calculated. At this time, the delay difference between the first training sampling signal and the second training sampling signal in the multiple delay operations is At least one of the first ADC and the second ADC is delayed, that is, at least one of the first training sampling signal and the second training sampling signal is delayed and compared with the other, and the minimum value of the compared delay differences indicates that after the delay operation corresponding to the minimum value is performed, the first training sampling signal and the second training sampling signal are closest to each other. Therefore, after correcting at least one of the first ADC and the second ADC based on the minimum value of the delay difference, the first ADC and the second ADC can be sampled synchronously, thereby reducing the lag relationship between data in different channels and obtaining the best state of data synchronization in different channels, so as to ensure that the data in different channels collected simultaneously are synchronized data.

[0138] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A synchronous data processing method, characterized in that: The method comprises: Acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency; Sampling the first synchronous training signal through the first ADC to obtain a first training sampling signal; Sampling the second synchronous training signal through the second ADC to obtain a second training sampling signal; performing multiple delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculating delay differences between the first training sample signal and the second training sample signal after the multiple delay operations; Correcting at least one of the first ADC and the second ADC according to a minimum value of the delay differences so that the first ADC and the second ADC perform sampling synchronously; The performing a plurality of delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculating a delay difference between the first training sample signal and the second training sample signal after the plurality of delay operations, includes: Delaying the first training sample signal for a first specified time to obtain a first delayed signal; performing a plurality of delay operations on the second training sample signal according to a second specified time to obtain respective second delayed signals, until the second training sample signal is delayed to a set end time; Differences between the first delayed signal and each of the second delayed signals are calculated, and the differences between the first delayed signal and each of the second delayed signals are respectively determined as delay differences between the first training sample signal and the second training sample signal after the multiple delay operations; a larger delay difference indicates a greater hysteresis relationship between the two signals of the first ADC and the second ADC; a smaller delay difference indicates a smaller hysteresis relationship between the two signals of the first ADC and the second ADC.

2. The method according to claim 1, characterized in that The second training sample signal is subjected to multiple delay operations, with the second designated time being the first delay and subsequent delay operations being performed by gradually increasing the preset time based on the second designated time, to obtain the first and subsequent second delayed signals.

3. The method according to claim 2, characterized in that The value range of the second specified time is between 0 and the first specified time; the value range of the added preset time is between 0 and the first specified time; the value range of the specified end time is between 1 and 3 times the first specified time.

4. The method according to claim 2, characterized in that The calculating the difference between the first delayed signal and each of the second delayed signals includes: For each second delayed signal, split the first delayed signal into a target number of first signed data, and split the second delayed signal into a target number of second signed data; the first signed data and the second signed data correspond one to one; Normalizing each of the first signed data and each of the second signed data; performing a difference operation on each normalized first signed data and the corresponding normalized second signed data, and obtaining an absolute value of each difference; The absolute values ​​of the respective differences are summed to obtain a sum of the absolute values, and the sums of the respective absolute values ​​are respectively determined as the differences between the first delayed signal and the respective second delayed signals.

5. The method according to claim 4, characterized in that Before calibrating at least one of the first ADC and the second ADC according to the minimum value of the delay differences, the method further includes: Sequentially acquiring a difference between the first training sample signal and the second training sample signal under each delay operation; The corresponding difference values ​​under each delay operation are compared in sequence to obtain a minimum difference value, and the minimum difference value is determined as the minimum value among the delay differences.

6. The method according to claim 5, characterized in that The calibrating at least one of the first ADC and the second ADC according to the minimum value of the delay differences includes: Obtaining a delay time corresponding to the number of delay operations of the second training sample signal corresponding to the minimum value; At least one of the first ADC and the second ADC is calibrated based on the delay time corresponding to the number of delay operations and the first specified time.

7. The method according to claim 6, characterized in that The calibrating at least one of the first ADC and the second ADC based on the delay time corresponding to the number of delay operations and the first specified time includes: When the delay time corresponding to the number of delay operations is greater than the first specified time, calibrating the second ADC based on a difference between the delay time corresponding to the number of delay operations and the first specified time; When the delay time corresponding to the number of delay operations is less than the first specified time, the first ADC is calibrated based on a difference between the first specified time and the delay time corresponding to the number of delay operations.

8. The method according to claim 7, characterized in that Before acquiring the first synchronous training signal and the second synchronous training signal, the method further includes: A target waveform data signal is acquired, and based on the target waveform data signal, two synchronous training signals with the same phase frequency are acquired, and the two synchronous training signals with the same phase frequency are respectively determined as a first synchronous training signal and a second synchronous training signal.

9. A synchronous data processing device, characterized in that: The device comprises: A synchronous training signal acquisition module, configured to acquire a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency; A first training sampling signal acquisition module is used to sample the first synchronous training signal through the first ADC to obtain a first training sampling signal; A second training sampling signal acquisition module is used to sample the second synchronous training signal through the second ADC to obtain a second training sampling signal; a delay difference acquisition module, configured to perform multiple delay operations on at least one of the first training sample signal and the second training sample signal, and respectively calculate the delay difference between the first training sample signal and the second training sample signal after the multiple delay operations; a correction module, configured to correct at least one of the first ADC and the second ADC according to a minimum value of the delay differences, so that the first ADC and the second ADC perform sampling synchronously; The delay difference acquisition module is further used to: Delaying the first training sample signal for a first specified time to obtain a first delayed signal; performing a plurality of delay operations on the second training sample signal according to a second specified time to obtain respective second delayed signals, until the second training sample signal is delayed to a set end time; Differences between the first delayed signal and each of the second delayed signals are calculated, and the differences between the first delayed signal and each of the second delayed signals are respectively determined as delay differences between the first training sample signal and the second training sample signal after the multiple delay operations; a larger delay difference indicates a greater hysteresis relationship between the two signals of the first ADC and the second ADC; a smaller delay difference indicates a smaller hysteresis relationship between the two signals of the first ADC and the second ADC.

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