Semiconductor device

Abstract

A semiconductor substrate (10) having an IGBT region (1a) and an FWD region (1b) includes a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer (11), a collector layer (21) of the second conductivity type formed in the drift layer (11) on a side opposite the base layer (12) in the IGBT region (1a), and a cathode layer (22) of the first conductivity type formed in the drift layer (11) on a side opposite the base layer (12) in the FWD region (1b). The collector layer (21) is formed to have an extension portion (21a) that covers only a part of the drift layer (11) side of the cathode layer (22).

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-79269, filed on April 28, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device having an insulated gate bipolar transistor (hereinafter referred to as IGBT) element and a freewheeling diode (hereinafter referred to as FWD) element having an insulated gate structure formed on a common semiconductor substrate. Background Technology

[0004] Conventionally, for example, as a switching element used in inverters, a semiconductor device has been proposed in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed on a common semiconductor substrate (for example, see Patent Document 1).

[0005] Specifically, in this semiconductor device, when N is constituting － A base layer is formed on one side of a semiconductor substrate with a drift layer, and multiple trenches are formed to penetrate the base layer. Each trench extends such that one direction along the surface of the semiconductor substrate is its length. Furthermore, a gate insulating film and a gate electrode are sequentially formed in each trench.

[0006] In the surface portion of the base layer, N is formed in a manner that connects with the trench. + A type of emitter region. On the other side of the semiconductor substrate, a P-type emitter region is formed. + Type of collector layer and N + A type of cathode layer. Furthermore, on the other side of the semiconductor substrate, a P-type cathode layer is formed over the entire region between the drift layer and the collector and cathode layers. + A shielding layer of this type. That is, the cathode layer is completely covered by the shielding layer in the entire area located on the drift layer side.

[0007] Furthermore, an upper electrode electrically connected to the emitter region and the base layer is formed on one side of the semiconductor substrate. A lower electrode electrically connected to the collector layer and the cathode layer is formed on the other side of the semiconductor substrate.

[0008] In such a semiconductor device, the region where the collector layer is formed is designated as the IGBT region, and the region where the cathode layer is formed is designated as the FWD region. Furthermore, in the FWD region, by forming the above structure, an FWD element with a PN junction is constituted by an N-type cathode layer and a drift layer and a P-type base layer.

[0009] Furthermore, in the aforementioned semiconductor device, when the IGBT element is in the on state, electrons are supplied from the emitter region to the drift layer and holes are supplied from the collector layer to the drift layer. In this case, since the entire region of the cathode layer located on the drift layer side is covered by the shielding layer, voltage snapback of the IGBT element can be suppressed.

[0010] Existing technical documents

[0011] Patent documents

[0012] Patent Document 1: Japanese Patent No. 6158123 Summary of the Invention

[0013] However, in the aforementioned semiconductor device, the entire region of the cathode layer located on the drift layer side is covered by a shielding layer. Therefore, when the FWD element becomes conductive and operates as a diode, electrons supplied from the cathode layer may have difficulty flowing to the base layer side due to the shielding layer. That is, in the aforementioned semiconductor device, the forward voltage of the FWD element may become higher.

[0014] The object of the present invention is to provide a semiconductor device capable of suppressing voltage bounce of IGBT elements and suppressing the rise of forward voltage of FWD elements.

[0015] According to a technical solution of the present invention, a semiconductor device comprises: a semiconductor substrate having an IGBT region and an FWD region, including a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a collector layer of the second conductivity type formed in the drift layer in the IGBT region on a side opposite to the base layer side, and a cathode layer of the first conductivity type formed in the drift layer in the FWD region on a side opposite to the base layer side, with the base layer side surface as one side and the collector layer and cathode layer side surfaces as the other side; A conductive emitter region is formed in the surface portion of the base layer in the IGBT region; a gate insulating film is formed in the IGBT region between the drift layer in the base layer and the emitter region; a gate electrode is formed on the gate insulating film; a first electrode is disposed on one side of the semiconductor substrate and electrically connected to the base layer and the emitter region; and a second electrode is disposed on the other side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer; the collector layer has an extended portion that covers only a portion of the drift layer side in the cathode layer.

[0016] Therefore, an extended portion is formed on the drift layer side of the cathode layer, which can suppress voltage rebound when the IGBT element is in the on state. Furthermore, the extended portion is configured to cover only a portion of the drift layer side of the cathode layer. Thus, it is possible to suppress the difficulty of carriers (e.g., electrons) moving from the cathode layer to the base layer side when the FWD element is in the on state, and to suppress the increase in the forward voltage of the FWD element.

[0017] Furthermore, according to another technical solution of the present invention, a semiconductor device comprises: a semiconductor substrate having an IGBT region and an FWD region, including a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a collector layer of the second conductivity type formed in the drift layer in the IGBT region on the side opposite to the base layer side, and a cathode layer of the first conductivity type formed in the drift layer in the FWD region on the side opposite to the base layer side, with the base layer side surface as one side and the collector layer and cathode layer side surfaces as the other side; the first conductivity type... An emitter region is formed on the surface of the base layer in the IGBT region; a gate insulating film is formed between the drift layer and the emitter region in the base layer in the IGBT region; a gate electrode is formed on the gate insulating film; a first electrode is disposed on one side of the semiconductor substrate and electrically connected to the base layer and the emitter region; and a second electrode is disposed on the other side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer; the collector layer has an extended portion that covers the entire area of ​​the cathode layer located on the drift layer side; the areal density of the extended portion is 3.5 × 10⁻⁶. 12 cm －2 the following.

[0018] Therefore, an extended portion is formed on the drift layer side of the cathode layer, which can suppress voltage bounce when the IGBT element is in the on state. Furthermore, the areal density of the extended portion is set to 3.5 × 10⁻⁶. 12 cm －2 Therefore, it is possible to suppress the increase in the forward voltage of the FWD element.

[0019] Furthermore, the parenthesized labels assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0020] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0021] Figure 2A It means along Figure 1 A graph showing the relationship between carrier concentration and depth along the IIA-IIA line.

[0022] Figure 2B It means along Figure 1 A graph showing the relationship between carrier concentration and depth along the IIB-IIB line.

[0023] Figure 3 This is a schematic diagram illustrating the flow of electrons when an IGBT element is in the on state.

[0024] Figure 4A This is a graph showing the simulation results related to the hole concentration when the IGBT element is in the on state, and it is a graph without the formation of the extension section.

[0025] Figure 4B This is a graph showing the simulation results related to the hole concentration when the IGBT element is in the on state, and it is a graph in the case where an extended setting is formed.

[0026] Figure 5A This is a graph showing the simulation results related to the relationship between the collector-emitter voltage and the collector current.

[0027] Figure 5B yes Figure 5A An enlarged view of the area VB enclosed by the double-dotted line.

[0028] Figure 6 This is a graph showing the simulation results related to the length of the extension section, the on-state voltage of the IGBT element, and the forward voltage of the FWD element.

[0029] Figure 7 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0030] Figure 8 This is a graph showing the simulation results related to the depth of the collector layer and the forward voltage of the FWD element when the carrier concentration of the collector layer is set to a certain value.

[0031] Figure 9 This is a graph showing the simulation results related to the carrier concentration of the collector layer and the forward voltage of the FWD element when the depth of the collector layer is set to a certain value.

[0032] Figure 10 This is a graph showing the relationship between surface density and the forward voltage of the FWD element.

[0033] Figure 11 This indicates the third embodiment along Figure 1 A graph showing the relationship between carrier concentration and depth along the XI-XI line. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe the identical or equivalent parts.

[0035] (First Embodiment)

[0036] The first embodiment will be described with reference to the accompanying drawings. Furthermore, the semiconductor device of this embodiment is suitable for use as a power switching element in power supply circuits such as inverters and DC / DC converters.

[0037] like Figure 1 As shown, the semiconductor device of this embodiment is an RC (Reverse Conducting)-IGBT formed on a common semiconductor substrate 10, comprising an IGBT region 1a having IGBT elements and an FWD region 1b having FWD elements. Furthermore, in this embodiment, as described later, the portion on the collector layer 21 of the other side 10b of the semiconductor substrate 10 is designated as the IGBT region 1a, and the portion on the cathode layer 22 of the other side 10b of the semiconductor substrate 10 is designated as the FWD region 1b, as will be described in detail later.

[0038] Semiconductor devices have N － The semiconductor substrate 10 has a drift layer 11. Furthermore, the semiconductor substrate 10 in this embodiment is made of silicon and has a thickness of approximately 127 μm. A base layer 12 is formed on the drift layer 11. That is, the base layer 12 is formed on one side 10a of the semiconductor substrate 10.

[0039] On the semiconductor substrate 10, a plurality of trenches 13 are formed such that the base layer 12 penetrates from one side 10a to reach the drift layer 11. Thus, the base layer 12 is separated into multiple trenches 13. In this embodiment, the plurality of trenches 13 are formed in the IGBT region 1a and the FWD region 1b, respectively. Furthermore, in this embodiment, the plurality of trenches 13 have a length direction intersecting the arrangement direction of the IGBT region 1a and the FWD region 1b (i.e., Figure 1 It forms strips (in the direction of the paper's depth).

[0040] Each trench 13 is filled with a gate insulating film 14 formed in such a way as to cover the walls of each trench 13 and a gate electrode 15 made of polysilicon or the like formed on the gate insulating film 14. Thus, a trench gate structure is formed.

[0041] Furthermore, although not specifically illustrated, the gate electrode 15 formed in the IGBT region 1a is connected to the gate driver or the like via a gate pad (not shown) and is subjected to a predetermined voltage. The gate electrode 15 formed in the FWD region 1b is connected to the upper electrode 19 (described later) and is at the same potential as the upper electrode 19.

[0042] In the surface portion of the base layer 12, within the IGBT region 1a, an N2 layer with a carrier concentration higher than that of the drift layer 11 is formed. + The emitter region 16 is of the type described above. Specifically, the emitter region 16 is formed in the IGBT region 1a on one side 10a of the semiconductor substrate 10. Furthermore, in the surface portion of the base layer 12, a P-type emitter region with a higher carrier concentration than the base layer 12 is formed in the IGBT region 1a. + The contact region 17 is of the type. Specifically, the emitter region 16 is formed to terminate within the base layer 12 and to be in contact with the side of the trench 13. Furthermore, the contact region 17 is formed to terminate within the base layer 12 and to be sandwiched between two emitter regions 16.

[0043] More specifically, the emitter region 16 extends in a rod-like manner along the length of the trench 13 in the region between adjacent trenches 13, connecting with the side of the trench 13, and terminates at a position inward of the front end of the trench 13. Furthermore, the contact region 17 extends in a rod-like manner along the length of the trench 13, connecting with the emitter region 16.

[0044] Furthermore, in this embodiment, the portion of the wall of the trench 13 located between the emitter region 16 and the drift layer 11 corresponds to the surface of the base layer located between the emitter region and the drift layer. Additionally, in this embodiment, the contact region 17 is formed to a depth greater than the emitter region 16.

[0045] An interlayer insulating film 18, composed of BPSG (short for Borophosphosilicate Glass), is formed on one side 10a of the semiconductor substrate 10. Within the interlayer insulating film 18, in the IGBT region 1a of one side 10a of the semiconductor substrate 10, a contact hole 18a is formed, exposing the emitter region 16 and contact region 17 located between adjacent trenches 13. Furthermore, within the interlayer insulating film 18, in the FWD region 1b of one side 10a of the semiconductor substrate 10, a contact hole 18b is formed, exposing the base layer 12, and a contact hole 18c is formed, exposing the gate electrode 15.

[0046] Furthermore, an upper electrode 19 is formed on the interlayer insulating film 18. The upper electrode 19 is electrically connected to the emitter region 16 and the contact region 17 in the IGBT region 1a via a contact hole 18a formed in the interlayer insulating film 18. In addition, the upper electrode 19 is electrically connected to the base layer 12 in the FWD region 1b via a contact hole 18b formed in the interlayer insulating film 18, and is electrically connected to the gate electrode 15 via a contact hole 18c formed in the interlayer insulating film 18.

[0047] That is, an upper electrode 19 is formed on the interlayer insulating film 18, which functions as the emitter electrode in the IGBT region 1a and as the anode electrode in the FWD region 1b. In this embodiment, the upper electrode 19 corresponds to the first electrode.

[0048] On the side of the drift layer 11 opposite to the base layer 12, an N-type field stop layer (hereinafter referred to as FS layer) 20 with a higher carrier concentration than the drift layer 11 is formed. That is, the FS layer 20 is formed on the other side 10b of the semiconductor substrate 10.

[0049] Furthermore, in IGBT region 1a, a P layer is formed on the side opposite to the drift layer 11, separated by the FS layer 20. + The collector layer 21 of the type, in the FWD region 1b, is formed on the side opposite to the drift layer 11, separated by the FS layer 20, with N + Type 22 cathode layer.

[0050] In this embodiment, the depth (hereinafter referred to as depth) of the collector layer 21 to the other side 10b of the semiconductor substrate 10 is greater than that of the cathode layer 22. Furthermore, the collector layer 21 has an extension portion 21a extending onto the cathode layer 22. That is, the collector layer 21 has an extension portion 21a that covers the portion of the cathode layer 22 on the drift layer 11 side. However, in this embodiment, the extension portion 21a is not formed over the entire area of ​​the cathode layer 22; the portion of the cathode layer 22 on the drift layer 11 side, opposite to the collector layer 21, is exposed from the extension portion 21a. Hereinafter, the length of the extension portion 21a along the arrangement direction of the collector layer 21 and the cathode layer 22 will be defined as the length x of the extension portion 21a.

[0051] Furthermore, an N is disposed between the portion of the cathode layer 22 exposed from the extended portion 21a and the FS layer 20. － The connection region 23 is of the type described above. In this embodiment, the carrier concentration in the connection region 23 is lower than that in the cathode layer 22, and is set to the same carrier concentration as that in the drift layer 11. More specifically, the connection region 23 is formed by a portion of the drift layer 11.

[0052] Furthermore, the FS layer 20, collector layer 21, cathode layer 22, and connection region 23 described above are formed, for example, as follows: After ion implantation of impurities constituting the FS layer 20, ion implantation of impurities constituting the collector layer 21, including the extended provision portion 21a, is performed. Then, ion implantation of impurities constituting the cathode layer 22 is performed between the portion constituting the extended provision portion 21a and the other side 10b of the semiconductor substrate 10, followed by heat treatment to form the cathode layer 22.

[0053] Furthermore, the FS layer 20, the collector layer 21, and the cathode layer 22 are constructed by ion implantation of impurities and heat treatment as described above, therefore... Figure 2A and Figure 2B As shown, the carrier concentration follows a normal distribution. Furthermore, since the connection region 23 in this embodiment is composed of a portion of the drift layer 11, the carrier concentration is constant.

[0054] In addition, such as Figure 1 As shown, on the other side 10b of the semiconductor substrate 10, the collector layer 21 and the cathode layer 22 are formed adjacent to each other. Furthermore, in this embodiment, the IGBT region 1a and the FWD region 1b are defined based on whether the layer located on the other side 10b of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22. That is, in this embodiment, the portion on the collector layer 21 located on the other side 10b of the semiconductor substrate 10 is designated as the IGBT region 1a, and the portion on the cathode layer 22 located on the other side 10b of the semiconductor substrate 10 is designated as the FWD region 1b. Therefore, the extension portion 21a in this embodiment can also be said to be formed in the FWD region 1b.

[0055] A lower electrode 24, electrically connected to the collector layer 21 and the cathode layer 22, is formed on the side opposite to the drift layer 11, separated from the collector layer 21 and the cathode layer 22. In other words, the lower electrode 24 is formed on the other side 10b of the semiconductor substrate 10. That is, a lower electrode 24 is formed that functions as a collector electrode in the IGBT region 1a and as a cathode electrode in the FWD region 1b. In this embodiment, the lower electrode 24 corresponds to the second electrode.

[0056] The semiconductor device of this embodiment is configured such that an IGBT element is formed in the IGBT region 1a with the base layer 12 as the base, the emitter region 16 as the emitter, and the collector layer 21 as the collector. Furthermore, in the FWD region 1b, an FWD element is formed with the base layer as the anode and the drift layer 11, FS layer 20, cathode layer 22, and connection region 23 as the cathode, forming a PN junction.

[0057] The above describes the structure of the semiconductor device according to this embodiment. Furthermore, in this embodiment, N-type, N...+ Type, N － Type P is equivalent to the first conductivity type, P-type, P-type + This type corresponds to the second conductivity type. Furthermore, in this embodiment, by being configured as described above, the semiconductor substrate 10 has a structure including a collector layer 21, a cathode layer 22, a connection region 23, an FS layer 20, a drift layer 11, a base layer 12, an emitter region 16, and a contact region 17.

[0058] Next, the operation and effects of the aforementioned semiconductor device will be explained. First, the basic operation of the aforementioned semiconductor device will be explained.

[0059] In a semiconductor device, if a voltage higher than that of the upper electrode 19 is applied to the lower electrode 24, the PN junction formed between the base layer 12 and the drift layer 11 becomes in a reverse conduction state, forming a depletion layer. Furthermore, when a low level (e.g., 0V) voltage less than the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 15, no current flows between the upper electrode 19 and the lower electrode 24.

[0060] To enable the IGBT element to conduct, while a higher voltage is applied to the lower electrode 24 than to the upper electrode 19, a high-level voltage exceeding the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 15 of the IGBT region 1a. Consequently, an inversion layer is formed in the base layer 12 of the IGBT region 1a, in connection with the trench 13 where the gate electrode 15 is disposed. Furthermore, in the IGBT element, electrons are supplied from the emitter region 16 to the drift layer 11 via the inversion layer, thereby supplying holes from the collector layer 21 to the drift layer 11. Through conductivity modulation, the resistance of the drift layer 11 decreases, thus enabling the element to conduct.

[0061] Furthermore, when the IGBT element is set to the off state and the FWD element is set to the on state (i.e., the FWD element operates as a diode), the voltage applied to the upper electrode 19 and the lower electrode 24 is switched, and a positive voltage is applied to the upper electrode 19 with a higher voltage than that applied to the lower electrode 24. As a result, holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 22, thereby causing the FWD element to operate as a diode.

[0062] The above describes the basic operation of the semiconductor device according to this embodiment. Furthermore, in this embodiment, an extended portion 21a is formed on the cathode layer 22. Therefore, when the IGBT element is set to the on state, or when the IGBT element is in the on state, such as Figure 3As shown, after electrons reach the portion of the FS layer 20 located in the IGBT region 1a, they move towards the FWD region 1b along the surface direction of the semiconductor substrate 10 and are discharged from the cathode layer 22. Furthermore, holes supplied from the collector layer 21 to the drift layer 11 are also supplied from the extended portion 21a to the drift layer 11. Therefore, as... Figure 4A and Figure 4B As shown, it was confirmed that when the structure is configured with an extension portion 21a on the cathode layer 22, the hole concentration at the boundary between the IGBT region 1a and the FWD region 1b is higher than when the extension portion 21a is not configured on the cathode layer 22.

[0063] in addition, Figure 4B This is a simulation result of the cathode layer 22, where the length x of the extension portion 21a is the same as the width of the cathode layer 22, with the arrangement direction of the IGBT region 1a and the FWD region 1b set to the width of the cathode layer 22. That is, Figure 4B The simulation results are based on the case where the extended setting portion 21a is configured to cover the entire area of ​​the cathode layer 22. However, even if the extended setting portion 21a is not configured to cover the entire area of ​​the cathode layer 22 as in this embodiment, holes are still supplied from the extended setting portion 21a to the drift layer 11, thus increasing the hole concentration at the boundary between the IGBT region 1a and the FWD region 1b.

[0064] And, as Figure 5A and Figure 5B As shown, it has been confirmed that when the structure is configured such that the extended portion 21a is disposed over the entire area of ​​the cathode layer 22, voltage rebound can be suppressed. Furthermore, Figure 5A and Figure 5B The so-called extended setting portion refers to the simulation results when the extended setting portion 21a is configured to cover the entire area of ​​the cathode layer 22. However, even if the extended setting portion 21a is not configured to cover the entire area of ​​the cathode layer 22 as in this embodiment, the occurrence of voltage bounce can be suppressed because the hole concentration at the boundary between the IGBT region 1a and the FWD region 1b can be increased as described above.

[0065] On the other hand, when the FWD element is in the on state, if the extended portion 21a is arranged over the entire area of ​​the cathode layer 22, electrons will have difficulty moving from the cathode layer 22 to the base layer 12. Therefore, as Figure 6 As shown, when the extended portion 21a is arranged throughout the entire area of ​​the cathode layer 22, the forward voltage of the FWD element increases. Furthermore, Figure 6The simulation results show that the width of the cathode layer 22 is set to 24 μm, and the extension setting part 21a is arranged over the entire area of ​​the cathode layer 22 with a length of 24 μm.

[0066] Therefore, in this embodiment, as described above, the extended portion 21a is not formed to cover the entire area of ​​the cathode layer 22; a portion of the cathode layer 22 is exposed from the extended portion 21a. That is, the length x of the extended portion 21a is less than 24 μm. Therefore, as... Figure 6 As shown, it can suppress the rise of the forward voltage of the FWD element.

[0067] in addition, Figure 6 These are simulation results of a 400A current flowing through the circuit at 150℃. The forward voltage is expressed as Von, and the forward voltage as Vf. Furthermore, as... Figure 6 As shown, the longer the length x of the extended portion 21a, the lower the on-state voltage. Therefore, regarding the extended portion 21a, it is preferable that a portion of the cathode layer 22 is exposed from the extended portion 21a, and the length x is set according to the required on-state voltage, etc. For example, in this embodiment, when the length x is 23 μm, the on-state voltage can be sufficiently reduced and the rise of the forward voltage can be suppressed. That is, when the ratio of the length x of the extended portion 21a to the width of the cathode layer 22 is 23 / 24, the on-state voltage can be sufficiently reduced and the rise of the forward voltage can be suppressed.

[0068] Furthermore, in this embodiment, the carrier concentration in the connection region 23 between the FS layer 20 and the cathode layer 22 is lower than that in the cathode layer 22. Therefore, for example, compared to the case where the portion of the cathode layer 22 exposed from the extension portion 21a is connected to the FS layer 20, the voltage applied to the PN junction of the collector layer 21 and the FS layer 20 can be increased. Consequently, when the IGBT element is in the on state, an increase in the number of holes supplied to the collector layer 21 can be achieved, and the rise in the on-state voltage due to the absence of the extension portion 21a on the cathode layer 22 can be suppressed.

[0069] In the embodiment described above, the extended portion 21a is formed to cover a portion of the cathode layer 22. Therefore, voltage rebound when the IGBT element is in the on-state can be suppressed. Furthermore, the cathode layer 22 has a portion exposed from the extended portion 21a. Therefore, when the FWD element is in the on-state, it is possible to suppress the difficulty of electrons moving from the cathode layer 22 to the base layer 12 side, and to suppress the increase in forward voltage.

[0070] Furthermore, in this embodiment, a connection region 23 with a lower carrier concentration than the cathode layer 22 is disposed between the FS layer 20 and the cathode layer 22. Therefore, for example, compared to the case where the portion of the cathode layer 22 exposed from the extension portion 21a is connected to the FS layer 20, the voltage applied to the PN junction of the collector layer 21 and the FS layer 20 can be increased. Consequently, when the IGBT element is in the on-state, an increase in the number of holes supplied to the collector layer 21 can be achieved, and the rise in the on-state voltage due to the absence of the extension portion 21a on the cathode layer 22 can be suppressed.

[0071] (Second Implementation)

[0072] The second embodiment will be described. This embodiment differs from the first embodiment in that the structure of the extended mounting portion 21a is modified. Everything else is the same as the first embodiment, so descriptions are omitted here.

[0073] In the semiconductor device of this embodiment, such as Figure 7 As shown, the extended portion 21a is formed over the entire area of ​​the cathode layer 22. That is, the entire area of ​​the cathode layer 22 on the drift layer 11 side is covered by the extended portion 21a. Therefore, in the semiconductor device of this embodiment, as described above, there is a possibility that the forward voltage of the FWD element may become high. Therefore, in the semiconductor device of this embodiment, the extended portion 21a has the following structure. Hereinafter, referring to... Figures 8-10 The structure of the extended mounting section 21a in this embodiment will be described. Furthermore, in Figures 8-10 In this context, the depth of the cathode layer 22 is set to 0.15 μm, using the other side 10b of the semiconductor substrate 10 as a depth reference. Figure 7 The depth of the collector layer 21 is set to depth d as shown. Furthermore, in Figures 8-10 In this context, the forward voltage of the FWD element is represented as Vf.

[0074] First, such as Figure 8 As shown, it was confirmed that when the carrier concentration of collector layer 21 is increased to 1.0 × 10⁻⁶, the following conditions are met: 18 cm －3 With a fixed value, if the depth d of the collector layer 21 becomes 0.5 μm or more, the forward voltage of the FWD device increases sharply. Furthermore, as... Figure 9 As shown, it was confirmed that when the depth d of the collector layer 21 is fixed at 0.5 μm, if the carrier concentration of the collector layer 21 becomes 1.0 × 10⁻⁶, the following results can be obtained: 17 cm －3 As a result, the forward voltage of the FWD element increases sharply. Additionally, Figure 8 and Figure 9These are simulation results assuming a fixed carrier concentration along the depth direction.

[0075] Furthermore, if based on Figure 8 and Figure 9 The areal density of the extended setting section 21a is derived, and the relationship between the areal density and the forward voltage of the FWD element becomes... Figure 10 As shown. That is, as Figure 10 As shown, if the areal density becomes greater than 3.5 × 10 12 cm －2 If the forward voltage is large, it increases dramatically. Therefore, in this embodiment, the areal density of the extended portion 21a is set to 3.5 × 10⁻⁶. 12 cm －2 the following.

[0076] According to the embodiment described above, the extended portion 21a is formed over the entire area of ​​the cathode layer 22. Therefore, voltage bounce when the IGBT element is in the on-state can be suppressed. Furthermore, the areal density of the extended portion 21a is set to 3.5 × 10⁻⁶. 12 cm －2 Therefore, it is possible to suppress the increase in the forward voltage of the FWD element.

[0077] (Third Implementation)

[0078] The third embodiment will be described. This embodiment specifies the peak position of the carrier concentration in the collector layer 21, relative to the first embodiment. Everything else is the same as in the first embodiment, so descriptions are omitted here.

[0079] The basic structure of the semiconductor device in this embodiment is the same as that in the first embodiment described above, but the collector layer 21 is as follows: Figure 11 The configuration shown allows the carrier concentration to have multiple peaks. Furthermore, the collector layer 21 is formed such that, in the depth direction of the semiconductor substrate 10, the position P1 of the maximum peak of the carrier concentration is closer to the drift layer 11 (i.e., the FS layer 20 side) than the center C1 of the collector layer 21.

[0080] In addition, such a collector layer 21 is formed, for example, by performing multiple ion implantations with varying acceleration voltages.

[0081] According to the embodiment described above, the maximum peak position P1 of the collector layer 21 is closer to the drift layer 11 than the center C1. Therefore, avalanche breakdown can be suppressed, and SCSOA (short circuit safe operating area) can be improved.

[0082] That is, if the semiconductor device as described above is short-circuited, the number of injected holes decreases while electrons become excessive, resulting in a peak in the electric field strength on the other side 10b of the semiconductor substrate 10. In this embodiment, since the FS layer 20 is formed, the peak value is generated within the FS layer 20. Furthermore, if the peak value of the electric field strength occurs on the lower electrode 24 side, the semiconductor device is prone to avalanche breakdown.

[0083] However, in this embodiment, the peak position P1 of the maximum carrier concentration in the collector layer 21 is located on the drift layer 11 side. Therefore, for example, compared to the case where the maximum peak position P1 is closer to the other side 10b of the semiconductor substrate 10 than the center C1, during a short circuit, it is easier to increase the number of holes injected into the position that may become the peak of the electric field strength, thus mitigating the excessive state of electrons. Therefore, avalanche breakdown can be suppressed.

[0084] (Other implementation methods)

[0085] The present invention has been described according to embodiments, but it should be understood that the invention is not limited to these embodiments and constructions. The invention also includes various modifications and equivalent variations. In addition, various combinations and forms, and further, other combinations and forms that include only one element, or more or less thereof, also fall within the scope and spirit of the invention.

[0086] For example, in the above embodiments, an example of setting the first conductivity type to N type and the second conductivity type to P type has been described, but it is also possible to set the first conductivity type to P type and the second conductivity type to N type.

[0087] In addition, in the above embodiments, a planar semiconductor device with the gate electrode 15 disposed on one side 10a of the semiconductor substrate 10 can be made instead of a trench gate semiconductor device.

[0088] Furthermore, in the above embodiments, the structure of one side 10a of the semiconductor substrate 10 in the FWD region 1b can be appropriately modified. For example, an N-type region corresponding to the emitter region 16 may be formed on one side 10a of the semiconductor substrate 10 in the FWD region 1b.

[0089] Furthermore, in the first and third embodiments described above, the portion of the cathode layer 22 exposed from the extension portion 21a can also be connected to the FS layer 20. Additionally, the carrier concentration in the connection region 23 can be made higher than that in the cathode layer 22. Even with such a semiconductor device, by fabricating a structure in which the cathode layer 22 has a portion exposed from the extension portion 21a, it is possible to suppress voltage bounce in the IGBT element and suppress the rise in the forward voltage of the FWD element.

[0090] Furthermore, the above embodiments can be appropriately combined. For example, the second embodiment can be combined with the third embodiment to make the maximum peak position P1 of the collector layer 21 closer to the drift layer 11 than the center C1.

Claims

1. A semiconductor device comprising an IGBT region having IGBT elements and an FWD region having FWD elements formed on a common semiconductor substrate, characterized in that, have: The semiconductor substrate described above has the IGBT region and the FWD region described above, including a drift layer of a first conductivity type, a base layer of a second conductivity type formed on the drift layer, a collector layer of the second conductivity type formed in the drift layer in the IGBT region on the side opposite to the base layer side, and a cathode layer of the first conductivity type formed in the drift layer in the FWD region on the side opposite to the base layer side, with the base layer side as one side and the collector layer and cathode layer side as the other side. The emitter region of the first conductivity type is formed in the surface portion of the base layer in the IGBT region described above; A gate insulating film is formed in the IGBT region between the drift layer in the base layer and the emitter region; A gate electrode is formed on the aforementioned gate insulating film; The first electrode is disposed on one side of the semiconductor substrate and is electrically connected to the base layer and the emitter region; and The second electrode is disposed on the other side of the semiconductor substrate and is electrically connected to the collector layer and the cathode layer. The aforementioned collector layer has an extended portion that covers the entire area of ​​the aforementioned cathode layer located on the drift layer side; The surface density of the aforementioned extended portion is 3.5 × 10⁻⁶. 12 cm －2 the following.

2. The semiconductor device as claimed in claim 1, characterized in that, In the aforementioned collector layer, the location of the maximum peak position of the carrier concentration in the depth direction to the other side of the aforementioned semiconductor substrate is closer to the drift layer side than the center of the aforementioned collector layer in the depth direction.

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