Peak current mode control of buck-boost regulator

Abstract

The controller circuit can employ a method to provide control signals to a bridge switch operating an inductor for switched mode inductive buck-boost voltage regulation. A buck mode can operate the bridge switch in a buck current control mode when an input voltage exceeds an output voltage. A boost mode can operate the bridge switch in a boost current control mode when the output voltage exceeds the input voltage. During a transition from at least one of the current control buck mode to the current control boost mode or the current control boost mode to the current control buck mode, when the output voltage is approximately equal to the input voltage, a buck-boost transition mode can operate the bridge switch in a peak buck-boost current control mode that minimizes a minimum duty cycle (with a minimum "on" duty time and a minimum "off" duty time).

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims priority to Application Serial No. 17 / 167,548, filed February 4, 2021, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] This document relates generally (but not exclusively) to the field of power management, and more particularly (but not exclusively) to fixed frequency symmetric peak current mode control schemes, such as for 4-switch buck-boost regulators. BACKGROUND

[0004] Voltage regulators are used to maintain a constant voltage. Switching voltage regulators can be used to convert a DC input voltage to an AC output voltage, or can be used to convert one DC voltage level to another. Buck regulators can be used to lower or step down an input voltage, and boost regulators can be used to raise or step up an input voltage.

[0005] Inductive voltage regulators can be set to operate in different modes, such as depending on the load connected to the input and output. Continuous conduction mode (CCM) is characterized by current flowing continuously through the inductor energy storage element. In discontinuous conduction mode (DCM), the current across the inductor energy storage element can become zero. DCM modes include burst mode and pulse skip mode. Burst mode and pulse skip mode can be used to save power when the load requires very little current. In burst mode operation, the regulator runs for a period of time, charging the output capacitor to a set threshold voltage, and then turns off completely. When the output voltage across the output capacitor drops below the set threshold voltage, the converter turns back on and the cycle starts over. This method works well when the load current is small and the converter can “sleep” for a long period of time before it can turn on again.

[0006] Pulse skip mode is similar to burst mode and allows limiting the output voltage or current to within a maximum allowed margin. It is used when the load is small to reduce switching losses. This is a useful mode, for example, for sustained low loads, such as when the desired output voltage is similar to the input voltage.

[0007] Voltage regulators using valley current mode control (e.g., operating using valley-buck-peak-boost current mode control or peak-buck-valley-boost current mode control) cannot achieve efficient discontinuous conduction mode (DCM) operation. In valley current mode control, the control comparator is tripped before the valley current value of the inductor voltage I L can occur. This leaves the device without any available zero valley inductor current detection in DCM mode. Without the reverse inductor current I L , the control comparator cannot be tripped.L sensing capability, it is difficult to implement in DCM.

[0008] To address this issue of DCM operation, a peak-buck-peak-boost current mode control scheme can be used that modulates only one side of the switching duty cycle, either peak-buck or peak-boost. The other side of the switching duty cycle remains fixed. The single-sided modulation of the switching duty cycle helps overcome the drawbacks in the previous valley current mode, but there is a large inductor current I L ripple and more power loss. The large I L ripple degrades the transient dynamic performance of the power converter. SUMMARY

[0009] Recognizing these drawbacks, the inventors describe an improved performance symmetrical peak current control scheme. The inventive scheme can reduce or optimize I L ripple. It can help improve the power efficiency of a synchronous 4-switch buck-boost regulator. The proposed symmetrical peak-buck-peak-boost current control can help provide a seamless transition between continuous conduction mode (CCM) and discontinuous conduction mode operation (DCM) and can allow easy DCM implementation. The control scheme can be more suitable for DCM, pulse skipping, providing low inductor current I L ripple and better power efficiency, especially under light load conditions. The method can allow a fixed output voltage even when the input voltage fluctuates above or below the output.

[0010] The scheme can provide better power efficiency compared to different methods that use a single-sided fixed switching duty cycle. When only one side of the switching duty cycle is modulated (peak-buck or peak-boost), the required "on" duty time of the fixed side has a large margin compared to the minimum duty cycle, which results in a large inductor current I L ripple. The large I L ripple results in more power loss and can degrade the transient dynamic performance of the power converter. The inventive aspect uses a symmetrical slope compensation circuit to set the minimum on-time period of the synchronous 4-switch buck-boost regulator, which results in a minimum switching duty cycle. The minimum switching duty cycle results in low I L ripple and better power efficiency. Thus, compared to the inventive aspect of fixing one side of the switching duty cycle, the inventive aspect with low I L ripple, the inventive aspect also has better device performance and power efficiency along with easy DCM implementation and seamless transition between CCM and DCM.

[0011] A non-limiting numbered list of illustrative aspects of the present disclosure is provided below.

[0012] Aspect 1 can include or use subject matter (such as an apparatus, system, device, method, article of manufacture, for example, can include a machine readable medium having encoded instructions for operating an apparatus or performing a method) that can include or use a circuit to provide switched mode inductive buck-boost voltage regulation via an H-bridge arrangement of an inductor, a resistor, and a set of bridge switches. The H-bridge can include input terminals to receive an input signal and output terminals to provide an output signal, the circuit including a controller circuit. The controller circuit can selectively operate the set of bridge switches using a buck mode, a boost mode, and a buck-boost mode by providing respective mode selection signals to a set of buck bridge switches and a set of boost bridge switches of the set of bridge switches. The controller circuit can include: a buck mode in which the set of buck bridge switches are determined by a peak buck current mode control scheme and the set of boost bridge switches use 0% of an "on" duty cycle time of a duty cycle; a boost mode in which the set of boost bridge switches are determined by a peak boost current mode control scheme and the set of buck bridge switches use 0% of an "off" duty cycle time of a duty cycle; and a buck-boost mode in which the set of buck bridge switches are determined by a peak buck current mode control scheme and the set of boost bridge switches are determined by a peak boost current mode control scheme, while operating at least one of (1) minimizing the "on" duty cycle time of the set of boost bridge switches or (2) minimizing the "off" duty cycle time of the set of buck bridge switches when the output signal is equal to the input signal.

[0013] Aspect 2 can include or use, or can optionally be combined with the subject matter of Aspect 1 to optionally include or use a symmetric slope compensation circuit as part of the controller circuit to determine timing of a peak buck current trip and a peak boost current trip to equalize the "on" duty cycle time of the set of boost bridge switches to the "off" duty cycle time of the set of buck bridge switches in the buck-boost mode when the output signal is equal to the input signal.

[0014] Aspect 3 can include or use, or can optionally be combined with the subject matter of Aspect 1 or 2 to optionally include or use the "on" duty cycle time of the set of boost bridge switches and the "off" duty cycle time of the set of buck bridge switches for determining a maximum switching duty cycle.

[0015] Aspect 4 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-3 to optionally include or use a clock circuit configured to generate a clock pulse in response to a slope compensation signal reaching a reference voltage, where the clock pulse determines a start of a duty cycle.

[0016] Aspect 5 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-4 to optionally include or use the controller circuit comprising or coupled to a first comparator and a second comparator, wherein: (A) the first comparator is to provide a first comparator output based on a difference between (1) the input signal and (2) the output signal modified by the maximum switching duty cycle; (B) the second comparator is to provide a second comparator output based on a difference between (1) the output signal and (2) the input signal modified by the maximum switching duty cycle; and wherein the first comparator output and the second comparator input are to select between operation in the buck mode, the boost mode, or the buck-boost mode.

[0017] Aspect 6 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-5 to optionally include or use a resistor in series with the inductor for sensing current of the inductor.

[0018] Aspect 7 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-6 to optionally include or use the controller circuit comprising a plurality of comparisons operating together to minimize the "on" duty time of the set of boost bridge switches and the "off" duty time of the set of buck bridge switches.

[0019] Aspect 8 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-7 to optionally include or use a voltage divider to derive a DC offset voltage from a reference voltage to determine a peak boost duty factor to maintain a peak buck duty factor at a maximum

[0020] Aspect 9 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-8 to optionally include or use the symmetrical slope compensation circuit to determine a minimum duty cycle of a switch mode inductive buck-boost voltage regulator. The minimum duty cycle is determined by providing a reference signal and dividing the reference signal into a first reference signal and a second reference signal; comparing a slope compensation signal to the first reference signal to determine a minimum duty cycle of a peak boost current mode; comparing the slope compensation signal to the second reference signal to determine a maximum duty cycle of a peak buck current mode. A DC offset voltage is determined using the first reference signal and the second reference signal. A peak boost current trip time and a peak buck current trip timing are determined using the DC offset voltage. In response to an output signal equal to an input signal, the peak boost current trip is determined to correspond to the minimum duty cycle and the peak buck current trip is determined to correspond to the maximum duty cycle. A duty cycle of the peak boost current mode is determined using the DC offset voltage such that when the output signal becomes higher than the input signal, the duty cycle of the peak buck current mode remains at its maximum. A duty cycle of the peak buck current mode is determined using the DC offset voltage such that when the output signal becomes lower than the input signal, the duty cycle of the peak boost current mode remains at its maximum. A transition point of the peak boost current mode to the peak buck current mode is determined using an "on" duty cycle time period of the duty cycle.

[0021] Aspect 10 can include or use subject matter (such as a device, system, apparatus, method, article of manufacture, such as a machine readable medium having encoded instructions for operating a device or performing a method), or can optionally be combined with any of Aspects 1-9, for example, to include or use a method for using a voltage regulator to smoothly transition between discontinuous conduction mode (DCM) and continuous conduction mode, for example, by sensing an inductor current, selecting an operating mode of the voltage regulator to be one of a peak buck current control mode, a peak boost current control mode, or a buck-boost current control mode based at least in part on one of a minimum "on" duty cycle time period of a set of boost control bridge switches or a minimum "off' duty cycle time period of a set of buck control bridge switches, and transitioning the voltage regulator to DCM in response to the inductor current becoming zero or transitioning from DCM in response to the inductor current becoming non-zero.

[0022] Aspect 11 can include or use, or can optionally be combined with the subject matter of any one of aspects 1-10 to optionally include or use the buck-boost current control mode, for example by measuring a first voltage of a slope compensation signal and comparing the first voltage of the slope compensation signal to a second voltage of a first reference signal to determine a minimum "on" duty cycle time of the peak boost current control mode; and comparing the first voltage of the slope compensation signal to a second reference signal to determine a minimum "off' duty cycle time of the peak buck current control mode.

[0023] Aspect 12 can include or use, or can optionally be combined with the subject matter of any one of aspects 1-11 to optionally include or use determining a minimum duty cycle, for example by dividing a reference voltage into a first reference voltage and a second reference voltage; determining a DC offset voltage using the first reference voltage and the second reference voltage; determining a maximum time of a duty cycle using the DC offset voltage; comparing a voltage of a slope compensation signal to a voltage difference of the first reference signal and the second reference signal to determine a peak boost time as a portion of the duty cycle; and comparing a voltage of the slope compensation signal to the second reference voltage, wherein the second reference voltage is derived from an input reference voltage, to determine an "on" duty cycle time of a buck control bridge switch that is a symmetrical proportion of the duty cycle to a minimum "on" duty cycle time of a boost control bridge switch.

[0024] Aspect 13 can include or use, or can optionally be combined with the subject matter of any one of aspects 1-12 to optionally include or use determining a peak buck current trip timing, for example by using the DC offset voltage, such that a peak boost current trip occurs at the minimum "on" duty cycle time of the peak boost current control mode and a peak buck current trip occurs at the minimum "off' duty cycle time of the peak buck current control mode when the trial output signal is approximately equal to the input signal.

[0025] Aspect 14 can include or use, or can optionally be combined with the subject matter of any one of aspects 1-13 to optionally include or use selecting an operating mode of the voltage regulator, for example can further include determining at least one of a clock signal, an input signal, and an output signal

[0026] Aspect 15 can include or use, or can optionally be combined with the subject matter of any one of aspects 1-14 to optionally include or use selecting an operating mode, for example by: determining a difference between an input signal and an output signal.

[0027] Aspect 16 can include or use, or can optionally be combined with the subject matter of any one of Aspects 1-15 to optionally include or use comparing the slope compensation signal to a first reference signal to determine a minimum "on" duty cycle period for peak buck; and comparing the slope compensation signal to a second reference signal to determine a minimum "off' duty cycle period for peak boost.

[0028] Aspect 17 can include or use, or can optionally be combined with the subject matter of any one of Aspects 1-16 to optionally include or use summing an indication of sensed inductor current with the slope compensation signal to produce a summed signal; and using the summed signal as an input to determine an operating mode.

[0029] Aspect 18 can include or use, or can optionally be combined with the subject matter of any one of Aspects 1-17 to optionally include or use using a reference voltage and a DC offset voltage to determine a minimum "on" duty cycle period for the set of buck control bridge switches, and wherein the minimum "on" duty cycle period is used to maintain a proportional time of an "off' duty cycle period of the set of boost control bridge switches for maintaining a maximum switch ratio.

[0030] Aspect 19 can include or use subject matter (such as an apparatus, a system, a device, a method, a product of manufacture, for example, can include a machine-readable medium having encoded instructions for operating an apparatus or performing a method), or can optionally be combined with any of Aspects 1-18, for example, to include or use a method of determining a minimum duty cycle for a switch mode inductive buck-boost voltage regulator, for example, providing a reference signal and dividing the reference signal into a first reference signal and a second reference signal. The method further includes comparing a slope compensation signal to the first reference signal to determine a minimum duty cycle for a peak boost current mode; and comparing the slope compensation signal to the second reference signal to determine a maximum duty cycle for a peak buck current mode. A DC offset voltage can be determined using the first reference signal and the second reference signal. A peak boost current trip time and a peak buck current trip timing can be determined using the DC offset voltage. A duty cycle for the peak boost current mode can be determined using the DC offset voltage such that the duty cycle for the peak buck current mode remains at its maximum value when an output signal becomes higher than an input signal. A duty cycle for the peak buck current mode can be determined using the DC offset voltage such that the duty cycle for the peak boost current mode remains at its maximum value when the output signal becomes lower than the input signal. A transition point from the peak boost current mode to the peak buck current mode can be determined using an "on" duty cycle period of the duty cycle.

[0031] Aspect 20 can include or use, or can optionally be combined with the subject matter of any of Aspects 1-19 to optionally include or use: responsive to the output signal being equal to the input signal, the peak boost current trip corresponds to a minimum duty cycle, and the peak buck current trip corresponds to a maximum duty cycle and is determined using the DC offset voltage.

[0032] Each of these non-limiting examples can exist independently, or can be combined in various permutations or combinations with one or more other examples.

[0033] This Summary is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the application. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF DRAWINGS

[0034] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0035] Figure 1 : Block diagram illustrating a proposed symmetrical peak current mode control example, e.g., for a synchronous 4-switch buck-boost regulator.

[0036] Figure 2A : Part of a proposed symmetrical peak current mode control circuit diagram example, e.g., for a synchronous 4-switch buck-boost regulator.

[0037] Figure 2B : Part of a proposed symmetrical peak current mode control circuit diagram example, e.g., for a synchronous 4-switch buck-boost regulator.

[0038] Figure 2C : Part of a proposed symmetrical peak current mode control circuit diagram example, e.g., for a synchronous 4-switch buck-boost regulator.

[0039] Figure 3A : Mode selection logic control flow diagram example of a proposed control scheme.

[0040] Figure 3B : Mode selection logic waveform of a proposed control scheme example.

[0041] Figure 4 : Operation waveforms of a proposed symmetrical peak current mode control scheme example in 4-switch buck-boost mode.

[0042] Figure 5Operation waveforms for the proposed example of the symmetrical peak current mode control scheme in 4-switch buck-boost mode.

[0043] Figure 6A Operation waveforms for the proposed example of the symmetrical peak current mode control scheme in 2-switch pure peak boost mode.

[0044] Figure 6B Operation waveforms for the proposed example of the symmetrical peak current mode control scheme in 2-switch pure peak buck mode. DETAILED DESCRIPTION

[0045] Described herein is a symmetrical peak current mode control scheme, such as for a synchronous 4-switch buck-boost regulator. It allows for inductor current (I L ) sensing, such as using a single current sense resistor. A switch mode inductive buck-boost voltage regulator operates by determining whether it should operate in a buck mode, a boost mode, or a buck-boost conversion mode. It can be used to perform symmetrical peak current regulation, such as for providing peak buck and peak boost control to modulate the switching duty cycle. When in buck-boost mode, both the peak buck current mode control scheme and the peak boost current mode control scheme can operate simultaneously, such as to minimize the "on" duty cycle time of the boost mode, or to minimize the "off" duty cycle time of the buck mode, or both.

[0046] One possible advantage of the present scheme compared to certain other control schemes is that it can provide a symmetrical slope compensation programming method. This helps to ensure that 4-switch buck-boost operation can be run at its minimum switching duty cycle, thereby reducing inductor current (I L ) ripple and improving power efficiency compared to other schemes. Another possible advantage is that the present synchronous 4-switch buck-boost regulator can help enable reverse inductor current (I L ) detection, such as operating in discontinuous conduction mode. This can include operating the voltage regulator in one or both of a pulse skip mode or a burst mode. Furthermore, by running the buck and boost in peak current mode only, the proposed control scheme can help enable seamless transitions between CCM and DCM operation.

[0047] Figure 1A block diagram example of a circuit for a synchronous 4-switch buck-boost regulator is shown. Such a circuit can include an inductor 130, a resistor 128, a buck regulator block 118, and a boost regulator block 126. A control circuit can include a peak buck control 112 circuit and a peak boost control 120 circuit. A mode selection logic block 106 can include an input that receives an input voltage 102 and an output voltage 104, respectively, and a slope compensation generator 110 can include an input that receives a reference input 108. The output of the mode selection logic block 106 is a mode selection signal that determines whether the switch mode inductive buck-boost voltage regulator is operating in a buck mode, a boost mode, or a buck-boost conversion mode. The inputs of the peak buck control 112 and the peak boost control 120 can be coupled to output signals from the mode selection logic block 106 and the slope compensation generator 110. The output signals of the peak buck control 112, V A 114, and V B 116 can be used to control respective switches via the buck regulator block 118, which is part of the peak buck control. Similarly, the output signals from the peak boost control 120, V C 122, and V D 124 can be used to control respective switches via the boost regulator block 126, which is part of the peak boost control 120.

[0048] Figure 2A 、 2B FIGS. 1C and 2C show circuit diagram examples of the symmetrical peak current mode control of the present invention, for example, for a synchronous 4-switch buck-boost regulator. The buck-boost regulator can include an inductor 130, an input capacitor 202, an output capacitor 204, and four power switches S A , S B , S C , and S D (206, 208, 212, 210), for example, can be controlled by gate signals V A , V B , V C , and V D (114, 116, 122, and 1214), respectively.

[0049] In the current mode control of the present invention, the inductor current (214) can be sensed using a current sensor. For example, the current sensor can be a current sense resistor 128 in series with the inductor 130. The node voltages at each terminal of the sense resistor Rs 128 can be fed to respective inputs of a current sense amplifier 234. The sensed inductor current 214 can be used for peak buck and peak boost current mode control. The buck mode is controlled by a peak current mode buck bridge. Thus, in a pure buck mode, SC 212 always "off, and S D 210 always "on" for the entire duty cycle. The boost mode is controlled by a peak current mode boost bridge switch, where S A 206 is always "on" and S B 208 is always "off for the entire duty cycle. The timing of the pure buck mode and the pure boost mode are described in more detail below in connection with FIG. 6. When the regulator is in the buck-boost mode, all four switches are controllable switches. When the input voltage V IN 102 is slightly greater than, equal to, or slightly less than the output voltage V OUT 104, the "on" and "off duty time of the switches control which mode the regulator is operating in. An indication of the inductor current V(I L0 )214 can be added to or otherwise combined with the slope compensation signal (V SLOPE )220 to help determine whether the regulator should be operated in the buck mode, the boost mode, or the buck-boost mode. This approach can utilize the slope compensation circuit 110 to determine which duty cycle portion will be in the buck mode and which duty cycle will be in the corresponding boost mode to maintain the desired output voltage. The resulting combined signal (V SLOPE + V(I L0 )) can be fed into the input of the main peak current comparator (PCC) 226. Such a series resistor 128 inductor current (I L ) sensing architecture facilitates reverse current detection, for example, for DCM (e.g., pulse skip mode and burst mode).

[0050] The slope compensation circuit 110 can use the input reference voltage (V REF )108 to generate a clock signal (V CLK )218 using a clock generation circuit. The clock edge determines the start of the duty cycle of the voltage regulator. The input reference voltage can also be used to generate the switching of S C 212 and S B 208 for the minimum duration of the respective "on" duty cycle in the buck-boost mode. In Figure 2C , when the node voltage V SLOPE 220 increases enough to reach the reference voltage (V REF 108) that indicates the start of the duty cycle, the clock signal V CLK 218 provides a clock pulse. The resistive divider can be arranged in series resistors. The divider can provide three different reference voltages V L 108", V REF -V L 108', and V OS224 (such as Figure 2B There are two matching voltage divider resistors R in series on the top and bottom. REF 240, V L 108" and V REF -V L 108' can be set equal. V L 108" can be used with V SLOPE 220 is compared. This may include a comparator that generates a pulse signal V MINON_C , where its duty cycle is set to S C Minimum on-time of the switch (t MINON_C ). Similarly, V REF -V L 108' can be with V SLOPE 220 to compare. This may include generating a pulse signal V MINON_B 216, where its duty cycle setting S B Minimum on-time (t MINON_B ). When V L 108" and V REF -V L 108', this will result in V MINON_C 222 and V MINON_B The on-time of 216 is also the same. Symmetrical slope compensation programming sets V MINON_B 216 and V MINON_C 222, when V L 108" and V REF -V L 108' are the same, they are equal and symmetrical in time. This will be done using a voltage divider according to V REF Determine V L 108" and V REF -V L 108'. DC offset voltage (V OS )224 can be used as V L 108" and V REF -V L 108' voltage difference is generated between the OS Can be added to the error amplifier (EA) 238 output (V EA 236), thereby generating an alternative peak current control signal (V EA +V OS )224'. Signal V EA 236 can be used to control peak boost current mode control.Alternative peak current control signal 224' can be used to control peak buck current mode control.

[0051] Figure 3A Figure 1 is a flow chart for mode selection. Mode selection can be used to determine the active mode of the voltage regulator based on the input and output signals at the beginning of the cycle. The active mode of the regulator is set to boost mode (also called peak boost mode), buck mode (also called peak buck mode), or buck-boost transition mode (also called buck-boost mode). Peak boost mode is when the regulator boosts the output voltage higher than the input voltage. In pure peak buck mode, only two switches S A 206 and S B 208 turns on alternately. Peak buck mode means the regulator steps down the output voltage to make it lower than the input voltage. In pure peak buck current mode control, S C 212 is closed during the entire switching cycle, and S D 210 is on. Buck-boost conversion mode alternates which switches are turned on depending on whether the voltage needs to be stepped down or stepped up to a lower voltage.

[0052] In some examples, two comparators (buck setting comparator 230 and boost setting comparator 232) can sense the voltage of the input signal 102 and the output signal 104 of the regulator, respectively, and can set the logic outputs. The buck comparator 230 output (ON_BUK) of the buck setting comparator 232 is set to turn on the buck mode. The boost comparator output (ON_BST) of the boost setting comparator 232 is set to turn on the boost mode. The mode selection logic block 106 obtains and uses the results of ON_BST and ON_BUK to set two peak current mode logic signals PK_BST 248 and PK_BUK 244, as shown in FIG. Figure 3A The selection mode logic diagram is shown.

[0053] exist Figure 3A In some examples shown, ON_BST may be determined before ON_BUCK. If ON_BST is set to 0, the select mode logic used by the select logic block 106 determines that the voltage regulator will operate in peak buck mode. ON_BST is set to 1 to indicate that peak boost mode is on or set to "active." When V OUT 104>k×V IN 102', ON_BSD occurs. ON_BUK is set to 1 to indicate that the peak buck mode is turned on. When V IN 102>k×V OUT 104 ', ON_BUG occurs. For both cases, k is the maximum switching duty cycle during any switching period. If ON_BUK and ON_BST are both set to 1, then the selection logic block 106 selects buck-boost mode.

[0054] Figure 3AThe illustrated selection mode logic diagram is used in the selection mode block 106 to determine the voltage regulator mode by using the outputs of the buck set comparator 230 and the boost set comparator 232 to select the mode in which the voltage regulator should run in the operating cycle. The output of the selection mode block 106 feeds into the peak buck control 112 and the peak boost control 120, which send signals to the bridge switches to open and close specific switches to operate the voltage regulator. In each switching cycle (A), the control scheme technique first checks if the peak boost phase is set to active. When ON_BST = 1, ON_BST is set to active. If not (ON_BST = 0), the regulator runs in pure peak buck mode (PK_BUK = 1 and PK_BST = 0). In pure peak buck mode, only two switches S A 206 and S B 208 are alternately turned on, per peak buck current mode control, S C 212 is off for the entire switching cycle, and S D 210 is turned on. When ON_BST is set to active (ON_BST = 1), then the process checks if the buck phase is active (ON_BUK = 1). If both ON_BST and ON_BUK are set to active (ON_BST = 1 and ON_BAK = 1), then the boost buck mode is set to active. This starts in peak enhancement mode (PK_BUK = 0 and PK_BST = 1). Thus, S C 212 is turned on and S D 210 is alternately turned on, per peak boost current mode control, until V A_PEAK 242 triggers or T MINON_C = 0. During this time, SA 206 is set to always on and SB 208 is always off until V A_PEAK 242 or T MINON_B triggers switches to peak buck mode (PK_BUK = 1 and PK_BST = 0). The peak buck mode works as described above until the clock V CLK 218 completes the duty cycle. If it is determined that the boost mode should be active, but the buck mode is not active (ON_BST = 1, ON_BUK = 0), then the regulator runs in pure boost mode (PK_BUK = 0 and PK_BST = 1). In this mode, only two switches S C 212 and S D 210 are alternately turned on, per peak boost current mode control, while S A 206 is turned on and S B 208 is off for the entire switching cycle. Upon detection of zero I L (I L=0)214', when operating in DCM, all bridge switches are closed during the remainder of the clock cycle.

[0055] Figure 3B The relationship between the comparator output and the mode selection is described. Figure 302 shows the mode selection, the pure peak buck selection is shown in Figure 304, and the pure peak boost selection is shown in Figure 306. Hysteresis can be added to the mode selection, such as Figure 3B The waveforms are shown. Hysteresis can help dampen or prevent oscillations between mode transitions. When ON_BST is set to 1 or "Active" in Figure 306 but ON_BUK is not set or "Inactive" in Figure 304, the corresponding Boost mode is selected in Figure 302. When ON_BST and ON_BUCK are set to 1 and "Active" in Figures 307 and 304, respectively, the corresponding Buck-Boost mode is selected in Figure 302. When ON_BST is not set or "Inactive" in Figure 306 and ON_BUK is set to 1 or "Active" in Figure 304, the corresponding Buck mode is selected in Figure 302.

[0056] Figure 4 The waveform diagram shows an example of how the voltage regulator operates in 4-switch buck-boost mode. For example, this mode can be selected when ON_BST is set to 1 and ON_BUK is set to 1. When V IN 102 equals V OUT 104, symmetrical peak buck and peak boost switching operations are performed. CLK 218, the mode selection logic initially sets PK_BST to 1, PK_BUK to 0, and comparator EA238, V EA The output of 236 is set to be connected directly to the input of the peak current comparator. A 206 and S C 212 open, also known as AC phase, and I L When the sensed V(I L ) increases to V EA and V SLOPE The difference between the peak current comparator 226 trips, and V A_PEAK Set to 1 or "Activate", and S C 212 Close and S D 210 open. This is Figure 4 The AD phase is displayed in the waveform. A_PEAK 242 rising edge, the mode selection logic sets PK_BST to 0, PK_BUK to 1, and V C With V OS 224 added. Since V EA236 was V OS 224 Jump up, V A_PEAK 242 will be reset to 0. When V(I L )214 increases to V EA +V OS 224' level, the level is V SLOPE (=V EA +V OS -V SLOPE ) compensation, the comparator trips again, generating a second V A_PEAK 242, and S A 206 Close and S B 208 is turned on until the next clock cycle. Figure 4 The BD phase in the waveform is displayed, where the BD phase corresponds to the open S B 208 and S D 210.

[0057] When V IN 102 and V OUT 104 are the same or substantially similar, this turns on the buck-boost stage, which means that when the input voltage V IN 102 is equal to the output voltage V OUT At 104, both AC phase and BD phase are set to open for equal symmetrical time, e.g. Figure 4 When the symmetrical slope compensation generator 110 uses the comparator to set V MINON_C 222 and V MINON_B 216, set AC phase and BD phase, V MINON_C 222 and V MINON_B 216SetS C 122 and S B 124 Minimum on-time of the switch, t MINON_C and t MINON_B Equal and symmetrical in time. V OS 224 is obtained by considering two reference voltages V L 180" and V REF -V L 180'. This difference can be used to generate V MINON_C 222 and V MINON_B 216. Same V SLOPE The 220 signal can be used for slope compensation in peak current mode control and t MINON_C and t MINON_B In some examples, V OS 224 and V SLOPE 220 are proportional to each other because they are all generated by the same VREF 108. In this case, the first and second V A_PEAK 242 are set to trigger at the same time. The timing difference between the two V OS 236 is set by the EA 238, and can be expressed as:

[0058] Δt(V A_PEAK ) = t S - (t MINON_C + t MINON_B )

[0059] where Δt(V A_PEAK ) is the timing difference between the two V A_PEAK fingers, and t S is the switching period. The first V A_PEAK 242 is triggered after t MINON_C period, and the second V A_PEAK 242 is triggered before t MINON_B . This helps to run the 4-switch buck-boost operation at its minimum switching duty cycle. In addition, the minimum switching duty cycle is symmetrical for the periods of the AC phase and the BD phase. Therefore, the efficiency is improved because the I L ripple current amplitude 130 is also at a minimum.

[0060] Figure 4 It is shown that when V IN 102 is higher than V OUT 104, the EA 238 will eventually lower V EA 236, resulting in the V A_PEAK 242 triggering early. Then, as the first V A_PEAK 242 is pushed inside t MINON_C , the BD phase will be adaptively expanded, while the AC phase is still fixed at its minimum. The inductor current I L 130 ripple is still at a minimum, allowing for improved efficiency.

[0061] Figure 4 It is shown that when V IN 102 is lower than V OUT 104, the EA 238 will raise V EA 236, so as to trigger the V A_PEAK 242 later. In this case, as the second V A_PEAK 242 is pushed out of t MINON_B , the AC phase will be adaptively expanded, while the BD phase is still fixed at its minimum load. In this case, as in the other cases, the voltage regulator still has a minimum I L 130 ripple and improved efficiency.

[0062] Figure 5is a waveform diagram showing an example of the operating waveforms of the control scheme of the present invention as it transitions between CCM and DCM. The scheme operates in peak current mode in both buck and boost modes, thus the scheme has the best DCM implementation. As the output load of the regulator decreases, the relationship between V EA 236 and the output signal V OUT 104 will cause the system to transition between CCM and DCM in response to the decrease in V EA 236 and V EA +V OS 224'. Both signals control the regulation period of V A_PEAK 242. Until the load and I L 214' decrease to the CCM and DCM boundary, the control scheme continues to operate as Figure 4 shown. As the regulator system transitions from CCM to DCM, the efficiency of the light load is improved as shown in Figure 5 , because as I L 214' decreases, V EA 236 will also continue to decrease, so V A_PEAK 242 will fire early. To obtain the minimum AC phase, V A_PEAK 242 is pushed inside t MINON_C 214. By pushing V A_PEAK 242 inside t MINON_C 214, the AC phase has the minimum "on" time within the duty cycle. As shown in the middle and rightmost waveforms of Figure 5 , when the second V A_PEAK 242 fires early, the AD phase will shrink while the BD phase remains the same as the inverse inductor current I L 214. The comparator flip-flop is the same as V(I L0 ) = 1. As I L 214' decreases linearly, the AD phase will also shrink proportionally. Ideally, this relationship will be linear when the duration of the AC phase and the BD phase remain the same. This helps to achieve a smooth decrease in charge transfer to the load in each switching cycle.

[0063] The voltage regulator can be configured to operate in peak current mode only in both buck and boost modes, thus providing easy to implement and improved performance in different modes for DCM (e.g., pulse-firing mode and burst mode), as well as a smooth transition from CCM to DCM.

[0064] Figure 6A and 6B is an example of the waveforms when operating in 2-switch pure peak boost current mode or pure peak buck current mode. When V IN 102 is much lower or much higher than V OUT 214, the waveforms will be the same as the 2-switch pure peak boost current mode or pure peak buck current mode.104, it will operate in pure peak boost current mode or pure peak buck current mode. IN 102 is much lower than V OUT 104 hours ( Figure 6A ), the voltage regulator will operate in pure peak boost current mode. In pure boost mode (PK_BST=1,PK_BUK=0), EA 238、V EA The output of 236 is directly connected to the input of the peak current comparator 226, which only verifies that V EA -V SLOPE Trigger V A_PEAK 242. Therefore, S C 212 and S D 210 is turned on alternately in each peak boost current mode control, while S A 206 is turned on, and S B 208 is off during the entire switching cycle. IN 102 is much higher than V OUT 104( Figure 6B ), the voltage regulator operates in pure peak buck current mode. In pure peak buck mode (PK_BUK=1 and PK_BST=0), V EA 236 and V OS 224 added, only verify V EA +V OS -V SLOPE Trigger V A_PEAK 242. Therefore, S A 206 and S B 208 alternately turns on each peak buck current mode control, while S C 212 is closed, and S D 210 is on during the entire switching cycle.

[0065] The above description includes reference to the accompanying drawings, which form part of the detailed description. The accompanying drawings illustrate specific embodiments in which the present invention may be implemented. These embodiments are also referred to herein as "examples." In addition to the elements shown or described, these examples may also include elements. However, the inventors also contemplate examples in which only the shown or described elements are provided. In addition, the inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), whether with respect to a specific example (or one or more aspects thereof), or with respect to other examples shown or described herein (or one or more aspects thereof).

[0066] In the event of a conflicting usage between this document and any document incorporated by reference, the usage in this document shall control.

[0067] In this document, the terms“a” or“an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of“at least one” or“one or more.” In this document, the term“or” is used to refer to a nonexclusive or, such that“A or B” includes“A but not B,”“B but not A,” and“A and B,” unless otherwise indicated. In this document, the terms“including” and“comprising” are used as the plain English equivalents of the respective terms“including” and“comprising.” Also, in the following claims, the terms“including” and“comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such open-ended terms in a claim are still within the scope of that claim. Moreover, in the following claims, the terms“first,”“second,” and“third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0068] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, in an example, the code can be tangibly embodied on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disk drives, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, RAM, ROM, etc.

[0069] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used as well, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b) and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter can reside in less than all features of a single disclosed embodiment. The following claims are hereby incorporated into the detailed description, where each claim can stand as a separate embodiment. The scope of the application should be determined, therefore, with reference to the appended claims and throughout the full range of equivalents to which such claims are entitled.

Claims

1. A circuit for providing switched mode inductor buck-boost voltage regulation via an H-bridge arrangement of an inductor, a resistor, and a set of bridge switches, the H-bridge including an input terminal that receives an input signal and an output terminal that provides an output signal, the circuit comprising: a controller circuit that selectively operates the set of bridge switches using a buck mode, a boost mode, and a buck-boost mode by providing respective mode selection signals to a set of buck bridge switches and a set of boost bridge switches in the set of bridge switches, the controller circuit including: a buck mode in which the set of buck bridge switches is determined by a peak buck current mode control scheme and the set of boost bridge switches uses an "on" duty cycle time with a duty cycle of 0%; a boost mode in which the set of boost bridge switches is determined by a peak boost current mode control scheme and the set of buck bridge switches uses an "off" duty cycle time with a duty cycle of 0%; a buck-boost mode in which the set of buck bridge switches is determined by a peak buck current mode control scheme and the set of boost bridge switches is determined by a peak boost current mode control scheme, at least one of (1) minimizing the "on" duty cycle time of the set of boost bridge switches or (2) minimizing the "off" duty cycle time of the set of buck bridge switches is simultaneously operated when the output signal is equal to the input signal; and a symmetric slope compensation circuit that times a peak buck current trip and a peak boost current trip to equalize the "on" duty cycle time of the set of boost bridge switches to the "off" duty cycle time of the set of buck bridge switches in the buck-boost mode when the output signal is equal to the input signal.

2. The circuit of claim 1, wherein the "on" duty cycle time of the set of boost bridge switches and the "off" duty cycle time of the set of buck bridge switches are used to determine a maximum switching duty cycle.

3. The circuit of claim 2, comprising a clock circuit configured to generate a clock pulse in response to a slope compensation signal reaching a reference voltage, wherein the clock pulse determines a start of a duty cycle.

4. The circuit of claim 2, the controller circuit including or coupled to a first comparator and a second comparator, wherein: (A) the first comparator is used to provide a first comparator output based on (1) the input signal and (2) the output signal modified by the maximum switching duty cycle; (B) the second comparator is used to provide a second comparator output based on (1) the output signal and (2) the input signal modified by the maximum switching duty cycle; and wherein the first comparator output and the second comparator output are used to select between operation in the buck mode, the boost mode, or the buck-boost mode.

5. The circuit of claim 1, wherein the resistor is in series with the inductor for sensing a current of the inductor.

6. The circuit of claim 1, wherein the controller circuit includes a plurality of comparisons that operate together to minimize the "on" duty cycle time of the set of boost bridge switches and to minimize the "off" duty cycle time of the set of buck bridge switches.

7. The circuit of claim 1, comprising a voltage divider that derives a DC offset voltage from a reference voltage to determine a peak boost duty cycle to maintain a peak buck duty cycle at its maximum.

8. The circuit of claim 1, wherein the symmetrical slope compensation circuit is used to determine a minimum duty cycle of a switch mode inductive buck-boost voltage regulator by: providing a reference signal and dividing the reference signal into a first reference signal and a second reference signal; comparing a slope compensation signal to the first reference signal to determine a minimum duty cycle of a peak boost current mode; comparing the slope compensation signal to the second reference signal to determine a maximum duty cycle of a peak buck current mode; determining a DC offset voltage using the first reference signal and the second reference signal; determining a peak boost current trip time and a peak buck current trip timing using the DC offset voltage; determining that the peak boost current trip corresponds to a minimum duty cycle and the peak buck current trip corresponds to a maximum duty cycle in response to an output signal being equal to an input signal; determining a duty cycle of the peak boost current mode using the DC offset voltage such that a duty cycle of the peak buck current mode is maintained at its maximum when an output signal becomes higher than an input signal; determining a duty cycle of the peak buck current mode using the DC offset voltage such that a duty cycle of the peak boost current mode is maintained at its maximum when the output signal becomes lower than the input signal; and determining a peak boost current mode to peak buck current mode transition point using a "on" duty cycle period of the duty cycles.

9. A method of using a voltage regulator to smoothly transition between discontinuous conduction mode (DCM) and continuous conduction mode (CCM), the method comprising: sensing an inductor current; selecting an operating mode of a voltage regulator to be one of a peak buck current control mode, a peak boost current control mode, or a buck-boost current control mode based at least in part on an input signal, an output signal, and a minimum "on" duty cycle period of a set of boost control bridge switches and a minimum "off" duty cycle period of a set of buck control bridge switches, the minimum "on" duty cycle period determined using a reference voltage and a DC offset voltage to maintain a proportional time of an "off" duty cycle period of the set of boost control bridge switches; and transitioning the voltage regulator into DCM in response to the inductor current becoming zero or out of DCM in response to the inductor current becoming non-zero.

10. The method of claim 9, wherein the buck-boost current control mode further comprises: measuring a first voltage of a slope compensation signal and comparing the first voltage of the slope compensation signal to a second voltage of a first reference signal to determine a minimum "on" duty cycle of a peak boost current control mode; and measuring a second voltage of the slope compensation signal and comparing the second voltage of the slope compensation signal to a third voltage of a second reference signal to determine a maximum "off" duty cycle of a peak buck current control mode. ​ ​ comparing the first voltage of the slope compensation signal to a second reference signal to determine a minimum "off" duty cycle period of the peak buck current control mode.

11. The method of claim 9, comprising determining a minimum duty cycle by: dividing a reference voltage into a first reference voltage and a second reference voltage; determining a DC offset voltage using the first reference voltage and the second reference voltage; determining a maximum time of duty cycle using the DC offset voltage; comparing a voltage of a slope compensation signal to a difference between voltages of the first reference signal and the second reference signal to determine a peak boost time as a portion of the duty cycle; and comparing a voltage of the slope compensation signal to the second reference voltage, wherein the second reference voltage is derived from an input reference voltage, to determine an "on" duty cycle period of the buck control bridge switch that is a symmetrical proportion of the minimum "on" duty cycle period of the boost control bridge switch as the duty cycle.

12. The method of claim 11, further comprising using the DC offset voltage to determine a peak buck current trip timing such that when the output signal is approximately equal to the input signal, a peak boost current trip occurs at the minimum "on" duty cycle period of the peak boost current control mode and a peak buck current trip occurs at the minimum "off" duty cycle period of the peak buck current control mode.

13. The method of claim 9, wherein selecting the operating mode of the voltage regulator further comprises determining at least one of a clock signal, or the input signal and the output signal.

14. The method of claim 13, wherein selecting an operating mode further comprises: determining a difference between the input signal and the output signal.

15. The method of claim 10, further comprising: comparing the slope compensation signal to the first reference signal to determine a minimum "on" duty cycle period of the peak boost; and comparing the slope compensation signal to the second reference signal to determine a minimum "off" duty cycle period of the peak buck.

16. The method of claim 9, wherein an indication of the sensed inductor current is summed with the slope compensation signal to produce a summed signal; and the summed signal is used as an input for determining the operating mode.

17. A method of determining a minimum duty cycle of a switched mode inductive buck-boost voltage regulator, the method comprising: providing a reference signal and dividing the reference signal into a first reference signal and a second reference signal; comparing a slope compensation signal to the first reference signal to determine a minimum duty cycle of the peak boost current mode; comparing the slope compensation signal to the second reference signal to determine a maximum duty cycle of the peak buck current mode; determining a DC offset voltage using the first reference signal and the second reference signal; determining a peak boost current trip time and a peak buck current trip timing using the DC offset voltage; determining a duty cycle of the peak boost current mode using the DC offset voltage such that when the output signal becomes higher than the input signal, the duty cycle of the peak buck current mode remains at its maximum value; determining a duty cycle of the peak buck current mode using the DC offset voltage such that a duty cycle of the peak boost current mode remains at its maximum value when the output signal becomes lower than the input signal; and and determining a transition point of the peak boost current mode to the peak buck current mode using an "on" duty cycle time period of the duty cycle.

18. The method of claim 17, wherein in response to the output signal being equal to the input signal, the peak boost current trip corresponds to a minimum duty cycle, the peak buck current trip corresponds to a maximum duty cycle, and is determined using the DC offset voltage.

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