Selection circuit, selection system and selection method

Abstract

The present disclosure describes a selection circuit, a selection system and a selection method for selecting a voltage supply. The selection circuit includes a first control switch, a first voltage supply switch, a second control switch and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and configured to receive a second voltage supply. The second control switch is configured to receive the control signal and the second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a selection circuit, a selection system, and a selection method, and more particularly, to a selection circuit, a selection system, and a selection method for selecting a voltage supply. BACKGROUND

[0002] Voltage scaling is a power management technique used in integrated circuit (IC) design, in which the voltage supply can be increased or decreased. For example, in a processor having multiple functional units, the voltage level of the power supply for idle units can be set lower than the voltage level of the power supply for active units. Thus, the power consumption of the processor can be reduced while the performance of the active units is improved. SUMMARY

[0003] The present disclosure provides a selection circuit. The selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and configured to receive a second voltage supply. The second control switch is configured to receive the control signal and the second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal. The control signal is configured to transition from a first voltage level to a second voltage level when in a logic high state before the selection circuit transitions between the first and second voltage supplies.

[0004] The present disclosure provides a selection system. The selection system includes a circuit (e.g., a processor) and a voltage supply selection circuit electrically coupled to the circuit. The circuit is configured to receive a voltage supply. The voltage supply selection circuit is configured to selectively provide a first voltage supply and a second voltage supply as the voltage supply to the circuit. The voltage supply selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and configured to receive a second voltage supply. The second control switch is configured to receive the control signal and the second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal. The control signal is configured to transition from a first voltage level to a second, higher voltage level when in a logic high state.

[0005] The present disclosure provides a selection method. The selection method includes receiving a selection signal and a first voltage using a first switch, receiving a second voltage supply using a second switch electrically coupled to the first switch, receiving the selection signal and a second voltage using a third switch, receiving the first voltage using a fourth switch electrically coupled to the third switch, and in response to the selection signal transitioning from a first logic level to a second logic level and in response to the first and second voltages being substantially at the same voltage level, transitioning the voltage supply from the first voltage to the second voltage. The selection signal is used to transition from the first voltage to the second voltage when in the first logic level. The method further includes receiving an output of the second control switch using a first control switch and receiving an output of the first control switch using a second control switch.

[0006] The present disclosure provides a selection circuit. The selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first control switch includes an inverter circuit. The inverter circuit is configured to receive the control signal and the first voltage supply. The control signal is configured to transition from a first voltage level to a second voltage level when in a logic high state. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second control switch is configured to receive the control signal and the second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and is configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

[0007] The present disclosure provides a selection circuit. The selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second control switch is configured to receive the control signal and the second voltage supply. The second control switch includes a level shifter circuit. The level shifter circuit is configured to receive the control signal and the first voltage supply. The second voltage supply switch is electrically coupled to the second control switch and is configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal. The control signal is configured to transition from a first voltage level to a second voltage level when in a logic high state.

[0008] The present disclosure provides a selection method. The selection method includes receiving a selection signal and a first voltage using a first switch. The first switch includes an inverter circuit. The inverter circuit is configured to receive a control signal and the first voltage supply. The control signal is configured to transition from a first voltage level to a second voltage level when in a logic high state. Receiving the second voltage using a second switch. Receiving the selection signal and the second voltage using a third switch. Receiving the first voltage using a fourth switch. And in response to the selection signal transitioning from a first logic level to a second logic level, and in response to the first and second voltages being at substantially the same voltage level, transitioning the voltage supply from the first voltage to the second voltage. BRIEF DESCRIPTION OF DRAWINGS

[0009] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 FIG. 1 illustrates a system for selecting a voltage supply according to some embodiments of the present disclosure;

[0011] Figure 2 FIG. 2 illustrates a voltage supply selection circuit according to some embodiments of the present disclosure;

[0012] Figure 3 FIG. 3 illustrates a voltage supply selection circuit represented in a first circuit stage according to some embodiments of the present disclosure;

[0013] Figure 4 FIG. 4 illustrates example waveforms for a voltage supply selection circuit represented in a first circuit stage according to some embodiments of the present disclosure;

[0014] Figure 5 FIG. 5 illustrates a voltage supply selection circuit represented in a second circuit stage according to some embodiments of the present disclosure;

[0015] Figure 6 FIG. 6 illustrates example waveforms for a voltage supply selection circuit represented in a second circuit stage according to some embodiments of the present disclosure;

[0016] Figure 7 FIG. 7 illustrates a voltage supply selection circuit represented in a third circuit stage according to some embodiments of the present disclosure;

[0017] Figure 8 FIG. 8 illustrates example waveforms for a voltage supply selection circuit represented in a third circuit stage according to some embodiments of the present disclosure;

[0018] Figure 9FIG. 1 illustrates a diagram of a voltage supply selection circuit according to some embodiments of the present disclosure;

[0019] Figure 10 FIG. 2 illustrates a diagram of a voltage supply selection circuit according to some embodiments of the present disclosure;

[0020] Figure 11 FIG. 3 illustrates a diagram of an example waveform of a voltage supply selection circuit according to some embodiments of the present disclosure;

[0021] Figure 12 FIG. 4 illustrates a diagram of a voltage supply selection circuit according to some embodiments of the present disclosure;

[0022] Figure 13 FIG. 5 illustrates a diagram of an example waveform of a voltage supply selection circuit according to some embodiments of the present disclosure; and

[0023] Figure 14 FIG. 6 illustrates a diagram of a selection method for a voltage supply according to some embodiments of the present disclosure.

[0024]

Symbol Description

[0025] 100: system

[0026] 110: voltage supply selection circuit

[0027] 115: voltage supply

[0028] 120: circuit

[0029] 210: selection signal, control signal

[0030] 220: first control switch

[0031] 230: first voltage supply switch

[0032] 240: second control switch

[0033] 250: second voltage supply switch

[0034] 260: first voltage supply

[0035] 270: second voltage supply

[0036] 300: voltage supply selection circuit

[0037] 310: level shifter circuit

[0038] 320: first inverter circuit

[0039] 330: second inverter circuit

[0040] 340, 360: p-type transistor

[0041] 350: third inverter circuit

[0042] 400: waveform

[0043] 410, 420, 430, 440: time window

[0044] 450, 460: time

[0045] 500: voltage supply selection circuit

[0046] 510: first inverter circuit

[0047] 520: second inverter circuit

[0048] 530: level shifter circuit

[0049] 540: third inverter circuit

[0050] 600: waveform

[0051] 610, 620, 630, 640: time window

[0052] 650, 660: time

[0053] 700: voltage supply selection circuit

[0054] 710: delay circuit

[0055] 715: second inverter circuit

[0056] 717: third inverter circuit

[0057] 719, 729: node

[0058] 720: second delay circuit

[0059] 725: fourth inverter circuit

[0060] 727: fifth inverter circuit

[0061] 730: level shifter circuit

[0062] 740: first inverter circuit

[0063] 750: first NOR circuit

[0064] 760: second NOR circuit

[0065] 800: waveform

[0066] 810, 820, 830, 840: time window

[0067] 850, 870: time

[0068] 860, 880: delay

[0069] 900: voltage supply selection circuit

[0070] 910: delay circuit

[0071] 915: second inverter circuit

[0072] 920: second delay circuit

[0073] 925: sixth inverter circuit

[0074] 930: level shifter circuit

[0075] 940: first inverter circuit

[0076] 950: first inverter circuit

[0077] 960: fourth inverter circuit

[0078] 970: fifth inverter circuit

[0079] 980: second inverter circuit

[0080] 1000: voltage supply selection circuit

[0081] 1010: delay circuit

[0082] 1015: second inverter circuit

[0083] 1017: third inverter circuit

[0084] 1019, 1029: node

[0085] 1020: second delay circuit

[0086] 1025: fourth inverter circuit

[0087] 1027: fifth inverter circuit

[0088] 1030: level shifter circuit

[0089] 1040: first inverter circuit

[0090] 1050: first inverter circuit

[0091] 1060: second inverter circuit

[0092] 1100: waveform

[0093] 1100, 1120, 1130, 1140: time window

[0094] 1150, 1170: time

[0095] 1160, 1180: delay

[0096] 1200: voltage supply selection circuit

[0097] 1210: delay circuit

[0098] 1215: second inverter circuit

[0099] 1220: second delay circuit

[0100] 1225: fifth inverter circuit

[0101] 1230: level shifter circuit

[0102] 1240: first inverter circuit

[0103] 1250: first NOR circuit

[0104] 1260: third inverter circuit

[0105] 1270: fourth inverter circuit

[0106] 1280: second NOR circuit

[0107] 1300: waveform

[0108] 1310, 1320: switching window

[0109] 1400: method

[0110] 1410, 1420, 1430, 1440, 1450: operation

[0111] V1-V3: voltage DETAILED DESCRIPTION

[0112] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present case can repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the different embodiments and / or configurations discussed.

[0113] In some embodiments, the terms“about” and“substantially” can indicate a value for a given quantity that varies by less than 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms“about” and“substantially” can refer to a percentage of a value that is interpreted by one of skill in the relevant art in light of the teachings herein.

[0114] Embodiments of the present disclosure describe a voltage supply selection circuit that can increase or decrease a supply voltage according to a selection signal (or control signal). For example, when increasing a voltage supply to support a high performance mode operation of a system (e.g., to operate a circuit faster at a higher frequency), embodiments of the present disclosure increase a single supply voltage rather than multiple supply voltages, thereby simplifying circuit design. Further, when decreasing a voltage supply to reduce power consumption of a system, embodiments of the present disclosure decrease a single voltage supply rather than multiple supply voltages, thereby again simplifying circuit design.

[0115] Figure 1 A diagram of a system 100 for selecting a voltage supply is illustrated in accordance with some embodiments of the present disclosure. The system 100 includes a voltage supply selection circuit 110 and a circuit 120. In some embodiments, the circuit 120 can be a processor device (e.g., a central processing unit (CPU) device and a graphics processing unit (GPU) device), a memory device (e.g., a dynamic random access memory (DRAM) device and a static random access memory (SRAM) device), an input / output interface device (e.g., a peripheral component interface (PCI) device and a serializer / deserializer (SerDes) device), or any other type of device that can implement a voltage adjustment technique.

[0116] In some embodiments, the voltage supply selection circuit 110 provides a voltage supply 115 to the circuit 120. In accordance with some embodiments of the present disclosure, the voltage supply 115 can be a power supply voltage such as a power supply voltage VDD associated with a logic device DD or a power supply voltage VDD associated with a memory device operation DDM The voltage level of the power supply voltage VDD can be in a range of, for example, about 0.4 volts to about 5.0 volts. Other values are within the spirit and scope of the present disclosure. The power supply voltage VDD DD DDM ​The voltage level can be in the range of, for example, about 0.6 volts to about 2.0 volts. Other values ​​are within the spirit and scope of this disclosure. In some embodiments, during normal operation of system 100 (e.g., when system 100 is not in high-performance operation mode), the supply voltage V DD The voltage level can be lower than the power supply voltage V. DDM The voltage level. When system 100 is in high-performance operating mode, the power supply voltage V... DD The voltage level can be converted to a value higher than the supply voltage V. DDM A higher voltage level. According to some embodiments of this disclosure, during the normal and high-performance operating modes of system 100, the supply voltage V... DDM The voltage level can remain approximately the same. Although for illustrative purposes, the following description of the supply voltage V... DD and power supply voltage V DDM This is referred to as a voltage supply, but other voltage supplies may be used in conjunction with the embodiments described herein. All such other voltage supplies are within the spirit and scope of this disclosure.

[0117] The voltage supply selection circuit 110 can be based on a selection signal ( Figure 1 Not shown in the text; regarding Figure 2 The selection signal 210 (described below) provides multiple voltage levels (e.g., power supply voltage V) of the voltage supply 115. DD and power supply voltage V DDM The voltage supply selection circuit 110 provides voltage regulation functionality to circuit 120, wherein circuit 120 can receive one of two voltage supplies (e.g., power supply voltage V). DD Or power supply voltage V DDM This facilitates high-performance operation and manages power consumption in circuit 120. For example, when circuit 120 requires a higher voltage supply to facilitate high-performance operation (e.g., operating the circuit at a higher frequency and faster speed), voltage supply selection circuit 110 can provide a higher voltage level (e.g., supply voltage V). DD From a lower voltage level to a higher voltage level; regarding Figure 2 The second voltage supply 270 (described below) supplies voltage 115 to circuit 120. When circuit 120 is not in a high-performance operating mode and power consumption is reduced, voltage supply selection circuit 110 can provide a lower voltage level (e.g., supply voltage V). DDM Regarding Figure 2 The voltage supply 115 (described below as a first voltage supply 260) is connected to circuit 120. In some embodiments, the higher and lower voltage levels of voltage supply 115 (e.g., power supply voltage V) are connected to circuit 120.DD and power supply voltage V DDM It can depend on the selection signal (e.g.) Figure 2 (Selection signal 210 in the middle).

[0118] Figure 2 A voltage supply selection circuit 110 is illustrated according to some embodiments of this disclosure. The voltage supply selection circuit 110 includes a first control switch 220, a first voltage supply switch 230, a second control switch 240, and a second voltage supply switch 250. The voltage supply selection circuit 110 receives (or is electrically coupled to) a selection signal 210 (also referred to herein as "control signal 210") as input. In some embodiments, the selection signal 210 may be... Figure 1 Circuit 120 or in Figure 1 Another circuit, not shown in system 100, is provided to voltage supply selection circuit 110. In some embodiments, based on selection signal 210, voltage supply selection circuit 110 may output a first voltage supply 260 or a second voltage supply 270 at voltage supply 115. According to some embodiments of this disclosure, the first voltage supply 260 may be a power supply voltage V. DDM The second voltage supply 270 can be the power supply voltage V. DD .

[0119] According to some embodiments of this disclosure, a first control switch 220 receives (or is electrically coupled to) a selection signal 210 as an input, and a first voltage supply 260 serves as a power supply voltage. The first control switch 220 controls the output of a first voltage supply switch 230, which receives (or is electrically coupled to) a second voltage supply 270 as a power supply voltage based on the selection signal 210. For example, based on the selection signal 210, the first control switch 220 can control the first voltage supply switch 230 to supply the second voltage supply 270 (e.g., power supply voltage V) as a power supply voltage. DD (Transmitted to voltage supply 115.)

[0120] According to some embodiments of this disclosure, the second control switch 240 also receives (or is electrically coupled to) the selection signal 210 as an input, and the second voltage supply 270 serves as a power supply voltage. The second control switch 240 controls the output of the second voltage supply switch 250, which receives (or is electrically coupled to) the first voltage supply 260 as a power supply voltage based on the selection signal 210. For example, based on the selection signal 210, the second control switch 240 can control the second voltage supply switch 250 to supply the first voltage supply 260 (e.g., power supply voltage V) as a power supply voltage. DDMto the voltage supply 115. In some embodiments, if the second control switch 240 controls the second voltage supply switch 250 to pass the first voltage supply 260, the first control switch 220 controls the first voltage supply switch 230 to prevent the second voltage supply 270 from passing to the voltage supply 115, and vice versa.

[0121] Figure 3 A diagram of the voltage supply selection circuit 300 represented in a first circuit level is illustrated in accordance with some embodiments of the present disclosure. The voltage supply selection circuit 300 can represent the voltage supply selection circuit 110 of Figure 1 and Figure 2 In this example, the selection signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD ). For example, when the selection signal 210 is at logic high, the selection signal 210 is at the voltage level of the second voltage supply 270 (e.g., the supply voltage V DD ). Further, when the selection signal 210 is at logic low, the selection signal 210 is at ground (e.g., 0 volts).

[0122] The first control switch 220 includes a level shifter circuit 310, a first inverter circuit 320, and a second inverter circuit 330, where the power supply of these circuits is coupled to the first voltage supply 260. The level shifter circuit 310 receives (or is electrically coupled to) the selection signal 210. In some embodiments, the level shifter circuit 310 sets the voltage level of the selection signal 210 at its output to be in the same voltage domain as the first voltage supply 260 (e.g., the supply voltage V DDM ). For example, if the selection signal 210 is at logic high (e.g., the supply voltage V DD ), the level shifter circuit 310 outputs a logic high (e.g., the supply voltage V DDM ) that is in the voltage domain of the first voltage supply 260. Conversely, if the selection signal 210 is at logic low (e.g., 0 volts), the level shifter circuit 310 outputs ground (e.g., 0 volts). The first inverter circuit 320 receives (or is electrically coupled to) and inverts the output of the level shifter circuit 310. The second inverter circuit 330 receives (or is electrically coupled to) and inverts the output of the first inverter circuit 320.

[0123] The first voltage supply switch 230 includes a p-type transistor 340, which has a gate terminal, a first source / drain (S / D) terminal, and a second source / drain terminal. The gate terminal receives (or is electrically coupled to) the output of the first control switch 220. The first source / drain terminal receives (or is electrically coupled to) the second voltage supply 270. The second source / drain terminal outputs (or is electrically coupled to) the voltage supply 115.

[0124] The second control switch 240 includes a third inverter circuit 350. The third inverter circuit 350 receives (or is electrically coupled to) a selection signal 210 and receives (or is electrically coupled to) a second voltage supply 270. The third inverter circuit 350 inverts the selection signal 210. The second voltage supply switch 250 includes a p-type transistor 360 having a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal receives (or is electrically coupled to) the output of the second control switch 240. The first source / drain terminal receives (or is electrically coupled to) a first voltage supply 260. The second source / drain terminal outputs (or is electrically coupled to) a voltage supply 115.

[0125] Figure 4 Illustrations of example waveforms 400 of a voltage supply selection circuit 300, represented at a first circuit level, are shown according to some embodiments of this disclosure. As described above, for the voltage supply selection circuit 300, the selection signal 210 is located in the voltage domain of the second voltage supply 270 (e.g., power supply voltage V). DD (In the voltage domain). In waveform 400, when Figure 1 When system 100 is in normal operating mode (e.g., system 100 is not in high-performance operating mode), voltage V1 represents the voltage level of the second voltage supply 270, voltage V2 represents the voltage level of the first voltage supply 260, and voltage V3 represents the voltage level of the second voltage supply 270 when system 100 is in high-performance operating mode (e.g., operating the circuitry at a higher frequency and faster). The voltage level of voltage V3 may be higher than the voltage level of voltage V2, and the voltage level of voltage V2 may be higher than the voltage level of voltage V1. In some embodiments, the voltage level of the first voltage supply 260 is substantially the same during both normal and high-performance operating modes of system 100.

[0126] During time window 410, selection signal 210 is at logic high (e.g., voltage V1), and system 100 is in normal operating mode. Under this condition, voltage supply 115 is electrically coupled to first voltage supply 260. (See reference...) Figure 3When the select signal 210 is at a logic high (e.g., voltage VI), the second control switch 240 outputs a logic low (e.g., 0 volts). Specifically, the third inverter circuit 350 receives the select signal 210 and outputs a logic low (e.g., 0 volts). The second voltage supply switch 250 receives the logic low output from the second control switch 240 and passes the first voltage supply 260 to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic low (e.g., 0 volts) output at its gate terminal from the third inverter circuit 350. As a result, the p-type transistor 360 is on and passes the first voltage supply 260 (e.g., voltage V2) to the voltage supply 115.

[0127] Furthermore, when the select signal 210 is at a logic high (e.g., voltage VI), the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 310 receives a logic high from the select signal 210 (which is in the voltage domain of the second voltage supply 270) and outputs a logic high in the voltage domain of the first voltage supply 260. Next, the first inverter circuit 320 receives the logic high output from the level shifter circuit 310 and outputs a logic low (e.g., 0 volts). The second inverter circuit 330 receives the logic low output from the first inverter circuit 320 and outputs a logic high (e.g., voltage V2).

[0128] The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic high (e.g., voltage V2) output at its gate terminal from the second inverter circuit 330. Because the first source / drain terminal receives the second voltage supply 270, which is lower than the voltage V2 at the gate of the p-type transistor 340, the p-type transistor 340 is non-conductive and does not pass the second voltage supply 270 to the voltage supply 115.

[0129] During the time window 420, the select signal 210 transitions from a logic high to a logic low and the second voltage supply 270 transitions from voltage VI to voltage V3, in preparation for the high performance mode of operation of the system 100. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD When the second voltage supply 270 transitions from voltage VI to voltage V3, the select signal 210 transitions in a similar manner while the select signal 210 is at a logic high. In some embodiments, the select signal 210 transitions from a logic high (e.g., voltage V2) to a logic low (e.g., 0 volts) at time 450, at which time the first voltage supply 260 and the second voltage supply 270 are approximately at the same voltage level.

[0130] Reference Figure 3When the select signal 210 is at a logic low (e.g., 0 volts), the first control switch 220 outputs a logic low (e.g., 0 volts). Specifically, the level shifter circuit 310 receives a logic low from the select signal 210 and outputs a logic low (e.g., 0 volts). Next, the first inverter circuit 320 receives the logic low output from the level shifter circuit 310 and outputs a logic high (e.g., the first voltage supply 260). The second inverter circuit 330 receives the logic high output from the first inverter circuit 320 and outputs a logic low (e.g., 0 volts). The first voltage supply switch 230 receives the logic low output from the first control switch 220 and passes the second voltage supply 270 to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic low (e.g., 0 volts) output at its gate terminal from the second inverter circuit 330. As a result, the p-type transistor 340 is on and passes the second voltage supply 270 (e.g., converted from voltage VI to voltage V3) to the voltage supply 115.

[0131] Further, when the select signal 210 is at a logic low (e.g., 0 volts), the second control switch 240 outputs a logic high (e.g., the second voltage supply 270). Specifically, the third inverter circuit 350 receives the select signal 210 and outputs a logic high (e.g., the second voltage supply 270). The second voltage supply switch 250 receives the logic high output from the second control switch 240, which action prevents the first voltage supply 260 from being passed to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic high (e.g., the second voltage supply 270) output at its gate terminal from the third inverter circuit 350. As a result, the p-type transistor 360 is off and does not pass the first voltage supply 260 to the voltage supply 115. Figure 4 At time 450, the first voltage supply 260 and the second voltage supply 270 are at the same or approximately the same voltage level. As a result, the p-type transistor 360 is off and does not pass the first voltage supply 260 to the voltage supply 115.

[0132] During the time window 430, the select signal 210 is at a logic low and the second voltage supply 270 is at voltage V3. Because the second voltage supply 270 is passed to the voltage supply 115 through the first voltage supply switch 230, the voltage supply 115 is at voltage V3. As a result, Figure 1 The circuit 120 receives a higher voltage supply to facilitate a high performance mode of operation, which can operate the circuit faster at higher frequencies.

[0133] During the time window 440, the select signal 210 transitions from logic low to logic high, and the second voltage supply 270 transitions from voltage V3 to voltage VI, in preparation for the normal mode of operation of the system 100. In some embodiments, the select signal 210 transitions from logic low to logic high at time 460, at which time the first voltage supply 260 and the second voltage supply 270 are at approximately the same voltage level. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD When the second voltage supply 270 transitions from voltage V3 to voltage VI, the select signal 210 transitions in a similar manner, while the select signal 210 is at logic high.

[0134] Referring to Figure 3 When the select signal 210 is at logic high, the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 310 receives a logic high from the select signal 210 and outputs a logic high (e.g., the first voltage supply 260). Next, the first inverter circuit 320 receives the logic high output from the level shifter circuit 310 and outputs a logic low (e.g., 0 volts). The second inverter circuit 330 receives the logic low output from the first inverter circuit 320 and outputs a logic high (e.g., the first voltage supply 260). The first voltage supply switch 230 receives the logic high output from the first control switch 220, which action prevents the second voltage supply 270 from passing to the voltage supply 115. Specifically, the p-type transistor 340 receives a logic high (e.g., the first voltage supply 260) output at its gate terminal from the second inverter circuit 330. As a result, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., transitioning from voltage V3 to voltage VI) from passing to the voltage supply 115. Figure 4 At time 460, the first voltage supply 260 and the second voltage supply 270 are at the same or approximately the same voltage level. As a result, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., transitioning from voltage V3 to voltage VI) from passing to the voltage supply 115.

[0135] Further, when the select signal 210 is at logic high, the second control switch 240 outputs a logic low level (e.g., 0 volts). Specifically, the third inverter circuit 350 receives the select signal 210 and outputs a logic low (e.g., 0 volts). The second voltage supply switch 250 receives the logic low output from the second control switch 240 and passes the first voltage supply 260 to the voltage supply 115. Specifically, the p-type transistor 360 receives a logic low (e.g., 0 volts) output at its gate terminal from the third inverter circuit 350. As a result, the p-type transistor 360 is conductive and passes the first voltage supply 260 to the voltage supply 115.

[0136] Figure 5A diagram of voltage supply selection circuit 500 represented in a second circuit level is illustrated according to some embodiments of the present disclosure. Voltage supply selection circuit 500 can represent Figure 1 and Figure 2 voltage supply selection circuit 110. In this example, selection signal 210 is in the voltage domain of first voltage supply 260 (e.g., supply voltage V DDM ). For example, when selection signal 210 is at logic high, selection signal 210 is at the voltage level of first voltage supply 260 (e.g., supply voltage V DDM ). Furthermore, when selection signal 210 is at logic low, selection signal 210 is at ground (e.g., 0 volts).

[0137] First control switch 220 includes first inverter circuit 510 and second inverter circuit 520, where the power supply of these circuits is coupled to first voltage supply 260. First inverter circuit 510 receives (or is electrically coupled to) and inverts selection signal 210 as an output. Second inverter circuit 520 receives (or is electrically coupled to) and inverts the output of first inverter circuit 510. First voltage supply switch 230 in voltage supply selection circuit 500 has the same circuit level representation as first voltage supply switch 230 in voltage supply selection circuit 300. Figure 3

[0138] Second control switch 240 includes level shifter circuit 530 and third inverter circuit 540, where the power supply of these circuits is coupled to second voltage supply 270. Level shifter circuit 530 receives (or is electrically coupled to) selection signal 210. In some embodiments, level shifter circuit 530 sets the voltage level of selection signal 210 at its output to be the same voltage domain as second voltage supply 270 (e.g., supply voltage V DD ). For example, if selection signal 210 is at logic high (e.g., supply voltage V DDM ), level shifter circuit 530 outputs a logic high (e.g., supply voltage V DD ) that is in the voltage domain of second voltage supply 270. Conversely, if selection signal 210 is at logic low (e.g., 0 volts), level shifter circuit 530 outputs ground (e.g., 0 volts). Third inverter circuit 540 receives (or is electrically coupled to) and inverts the output of level shifter circuit 530. Second voltage supply switch 250 in voltage supply selection circuit 500 has the same circuit level representation as second voltage supply switch 250 in voltage supply selection circuit 300. Figure 3

[0139] Figure 6 ​​FIG. 6 illustrates an example waveform 600 for voltage supply selection circuit 500 represented at the second circuit level, according to some embodiments of the present disclosure. As described above, for voltage supply selection circuit 500, selection signal 210 is in the voltage domain of first voltage supply 260 (e.g., the supply voltage V DDM In waveform 600, when Figure 1 When system 100 is in normal mode of operation (e.g., system 100 is not in high performance mode of operation), voltage VI represents the voltage level of second voltage supply 270, voltage V2 represents the voltage level of first voltage supply 260, and voltage V3 represents the voltage level of second voltage supply 270 when system 100 is in high performance mode of operation (e.g., operating circuits faster at higher frequencies). Voltage level of voltage V3 can be higher than voltage level of voltage V2, which can be higher than voltage level of voltage VI. In some embodiments, the voltage level of first voltage supply 260 is approximately the same during normal and high performance modes of operation of system 100.

[0140] During time window 610, selection signal 210 is at logic high (e.g., voltage V2) and system 100 is in normal mode of operation. Under this condition, voltage supply 115 is electrically coupled to first voltage supply 260. Referring to Figure 5 When selection signal 210 is at logic high (e.g., voltage V2), second control switch 240 outputs logic low (e.g., 0 volts). Specifically, level shifter circuit 530 receives logic high from selection signal 210 (which is in the voltage domain of first voltage supply 260) and outputs logic high in the voltage domain of second voltage supply 270. Next, third inverter circuit 540 receives the logic high output from level shifter circuit 530 and outputs logic low (e.g., 0 volts). Second voltage supply switch 250 receives the logic low output from second control switch 240 and passes first voltage supply 260 to voltage supply 115. Specifically, p-type transistor 360 receives the logic low (e.g., 0 volts) output from third inverter circuit 540 at its gate terminal. As a result, p-type transistor 360 is on and passes first voltage supply 260 (e.g., voltage V2) to voltage supply 115.

[0141] Furthermore, when the select signal 210 is at a logic high (e.g., voltage V2), the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the first inverter circuit 510 receives a logic high from the select signal 210 and outputs a logic low. Next, the second inverter circuit 520 receives the logic low output from the first inverter circuit 510 and outputs a logic high (e.g., the first voltage supply 260). The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing through to the voltage supply 115. Specifically, the p-type transistor 340 receives a logic high (e.g., voltage V2) output at its gate terminal from the second inverter circuit 520. Because the first source / drain terminal receives the second voltage supply 270 (which is lower than the voltage V2 at the gate of the p-type transistor 340), the p-type transistor 340 is non-conductive and does not pass the second voltage supply 270 to the voltage supply 115.

[0142] During the time window 620, the select signal 210 transitions from a logic high to a logic low, and the second voltage supply 270 transitions from voltage VI to voltage V3, in preparation for the high performance mode of operation of the system 100. Because the select signal 210 is in the voltage domain of the first voltage supply 260 (e.g., the supply voltage V DDM the voltage domain of the second voltage supply 270), the select signal 210 retains its voltage level (unlike when the select signal 210 is in the voltage domain of the second voltage supply 270, as shown in the time window 420) when the second voltage supply 270 transitions from voltage VI to voltage V3. In some embodiments, at time 650, the select signal 210 transitions from a logic high (e.g., voltage V2) to a logic low (e.g., 0 volts), at which time the first voltage supply 260 and the second voltage supply 270 are at approximately the same voltage level. Figure 4

[0143] Referring to Figure 5 When the select signal 210 is at a logic low (e.g., 0 volts), the first control switch 220 outputs a logic low (e.g., 0 volts). Specifically, the first inverter circuit 510 receives a logic low from the select signal 210 and outputs a logic high (e.g., the first voltage supply 260). Next, the second inverter circuit 520 receives the logic high output from the first inverter circuit 510 and outputs a logic low (e.g., 0 volts). The first voltage supply switch 230 receives the logic low output from the first control switch 220 and passes the second voltage supply 270 to the voltage supply 115. Specifically, the p-type transistor 340 receives a logic low (e.g., 0 volts) output at its gate terminal from the second inverter circuit 520. As a result, the p-type transistor 340 is conductive and passes the second voltage supply 270 (e.g., from voltage VI to voltage V3) to the voltage supply 115. ​

[0144] Further, when the select signal 210 is at a logic low (e.g., 0 volts), the second control switch 240 outputs a logic high (e.g., the second voltage supply 270). Specifically, the level shifter circuit 530 receives the select signal 210 and outputs a logic low (e.g., 0 volts). The third inverter circuit 540 receives the logic low output from the level shifter circuit 530 and outputs a logic high (e.g., the second voltage supply 270). The second voltage supply switch 250 receives the logic high output from the second control switch 240, which action prevents the first voltage supply 260 from passing through to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic high (e.g., the second voltage supply 270) output at its gate terminal from the third inverter circuit 540. The p-type transistor 360 is non-conductive and does not pass the first voltage supply 260 to the voltage supply 115. Figure 6 At time 650, the first voltage supply 260 and the second voltage supply 270 are at the same or approximately the same voltage level. Thus, the p-type transistor 360 is non-conductive and does not pass the first voltage supply 260 to the voltage supply 115.

[0145] During the time window 630, the select signal 210 is at a logic low and the second voltage supply 270 is at voltage V3. Because the second voltage supply 270 is passed to the voltage supply 115 through the first voltage supply switch 230, the voltage supply 115 is at voltage V3. Thus, Figure 1 The circuit 120 receives a higher voltage supply to facilitate a high performance mode of operation, which can operate the circuit faster at higher frequencies.

[0146] During the time window 640, the select signal 210 transitions from a logic low to a logic high and the second voltage supply 270 transitions from voltage V3 to voltage VI, in preparation for the normal mode of operation of the system 100. Because the select signal 210 is in the voltage domain of the first voltage supply 260 (e.g., the power supply voltage V DDM the voltage domain of the second voltage supply 270), the select signal 210 maintains its voltage level when the second voltage supply 270 transitions from voltage V3 to voltage VI (unlike when the select signal 210 is in the voltage domain of the second voltage supply 270, as shown in the time window 440). In some embodiments, the select signal 210 transitions from a logic low to a logic high at time 660, at which time the first voltage supply 260 and the second voltage supply 270 are approximately at the same voltage level. Figure 4

[0147] Reference is made to Figure 5 ​When the select signal 210 is at a logic high, the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the first inverter circuit 510 receives a logic high from the select signal 210 and outputs a logic low (e.g., 0 volts). Next, the second inverter circuit 520 receives the logic low output from the first inverter circuit 510 and outputs a logic high (e.g., the first voltage supply 260). The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing through to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic high (e.g., the first voltage supply 260) output at its gate terminal from the second inverter circuit 520. As a result, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., from voltage V3 to voltage VI) from passing through to the voltage supply 115. Figure 6 At time 660, the first voltage supply 260 and the second voltage supply 270 are at the same or substantially the same voltage level. As a result, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., from voltage V3 to voltage VI) from passing through to the voltage supply 115.

[0148] Further, when the select signal 210 is at a logic high, the second control switch 240 outputs a logic low (e.g., 0 volts). Specifically, the level shifter circuit 530 receives a logic high from the select signal 210 (which is in the voltage domain of the first voltage supply 260) and outputs a logic high in the voltage domain of the second voltage supply 270. Next, the third inverter circuit 540 receives the logic high output from the level shifter circuit 530 and outputs a logic low (e.g., 0 volts). The second voltage supply switch 250 receives the logic low output from the second control switch 240 and passes the first voltage supply 260 to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic low (e.g., 0 volts) output at its gate terminal from the third inverter circuit 540. As a result, the p-type transistor 360 is conductive and passes the first voltage supply 260 (e.g., voltage V2) to the voltage supply 115.

[0149] Figure 7 A diagram of a voltage supply selection circuit 700 is shown in a third circuit level according to some embodiments of the present disclosure. The voltage supply selection circuit 700 can represent the voltage supply selection circuit 110 of Figure 1 and Figure 2 In this example, the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD ). For example, when the select signal 210 is at a logic high, the select signal 210 is at the voltage level of the second voltage supply 270 (e.g., the supply voltage V DD ). Further, when the select signal 210 is at a logic low, the select signal 210 is at ground (e.g., 0 volts).

[0150] The first control switch 220 includes a level shifter circuit 730, a first inverter circuit 740, a first NOR circuit 750, and a first delay circuit 710. The level shifter circuit 730 receives (or is electrically coupled to) the select signal 210. In some embodiments, the level shifter circuit 730 sets the voltage level of the select signal 210 at its output to be in the same voltage domain as the first voltage supply 260 (e.g., the supply voltage V DDM , for example). If the select signal 210 is at a logic high (e.g., the supply voltage V DD , for example), the level shifter circuit 730 outputs a logic high (e.g., the supply voltage V DDM , for example) that is in the voltage domain of the first voltage supply 260. Conversely, if the select signal 210 is at a logic low (e.g., 0 volts), the level shifter circuit 730 outputs ground (e.g., 0 volts). The first inverter circuit 740 receives (or is electrically coupled to) and inverts the output of the level shifter circuit 730. The first NOR circuit 750 receives (or is electrically coupled to) the output of the first inverter circuit 740 at a first input, and receives (or is electrically coupled to) the output of the second control switch 240 (e.g., node 729) at a second input. The first delay circuit 710 receives (or is electrically coupled to) the output of the first NOR circuit 750. The first delay circuit 710 includes a second inverter circuit 715 and a third inverter circuit 717. The second inverter circuit 715 receives (or is electrically coupled to) and inverts the output of the first NOR circuit 750. The third inverter circuit 717 receives (or is electrically coupled to) and inverts the output of the second inverter circuit 715. The first voltage supply switch 230 in the voltage supply selection circuit 700 has the same circuit level representation as the first voltage supply switch 230 in the voltage supply selection circuit 300 of Figure 3 .

[0151] The second control switch 240 includes a second NOR circuit 760 and a second delay circuit 720. The second NOR circuit 760 receives (or is electrically coupled to) the select signal 210 at a first input, and receives (or is electrically coupled to) the output of the first control switch 220 (e.g., node 719) at a second input. The second delay circuit 720 receives (or is electrically coupled to) the output of the second NOR circuit 760. The second delay circuit 720 includes a fourth inverter circuit 725 and a fifth inverter circuit 727. The fourth inverter circuit 725 receives (or is electrically coupled to) and inverts the output of the second NOR circuit 760. The fifth inverter circuit 727 receives (or is electrically coupled to) and inverts the output of the fourth inverter circuit 725. The second voltage supply switch 250 in the voltage supply selection circuit 700 has the same circuit level representation as the second voltage supply switch 250 in the voltage supply selection circuit 300 of Figure 3 .

[0152] Figure 8 A plot of example waveforms 800 for voltage supply selection circuit 700 represented at a third circuit level is illustrated in accordance with some embodiments of the present disclosure. As described above, for voltage supply selection circuit 700, selection signal 210 is in the voltage domain of second voltage supply 270 (e.g., power supply voltage V DD In waveforms 800, when Figure 1 When system 100 is in a normal mode of operation (e.g., system 100 is not in a high performance mode of operation), voltage VI represents the voltage level of second voltage supply 270, voltage V2 represents the voltage level of first voltage supply 260, and voltage V3 represents the voltage level of second voltage supply 270 when system 100 is in a high performance mode of operation (e.g., operating circuits faster at higher frequencies). Voltage V3 can be at a higher voltage level than voltage V2, which can be at a higher voltage level than voltage VI. In some embodiments, the voltage level of first voltage supply 260 is approximately the same during normal and high performance modes of operation of system 100.

[0153] During time window 810, selection signal 210 is at a logic high (e.g., voltage VI), and system 100 is in a normal mode of operation. Under this condition, voltage supply 115 is electrically coupled to first voltage supply 260. Referring to Figure 7 When selection signal 210 is at a logic high (e.g., voltage VI), second control switch 240 outputs a logic low (e.g., 0 volts). Specifically, second NOR circuit 760 receives selection signal 210 at a first input and outputs a logic low (e.g., 0 volts). Second delay circuit 720 receives the logic low output from second control switch 240 and outputs a logic low to second voltage supply switch 250. Specifically, fourth inverter circuit 725 receives the logic low output from second NOR circuit 760 and outputs a logic high (e.g., second voltage supply 270). Fifth inverter circuit 727 receives the logic high output from fourth inverter circuit 725 and outputs a logic low (e.g., 0 volts). Second voltage supply switch 250 receives the logic low output from second control switch 240 and passes first voltage supply 260 to voltage supply 115. Specifically, p-type transistor 360 receives the logic low (e.g., 0 volts) output from fifth inverter circuit 727 at its gate terminal. As a result, p-type transistor 360 is on and passes first voltage supply 260 (e.g., voltage V2) to voltage supply 115.

[0154] Furthermore, when the select signal 210 is at a logic high (e.g., voltage VI), the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 730 receives a logic high from the select signal 210 (which is in the voltage domain of the second voltage supply 270) and outputs a logic high in the voltage domain of the first voltage supply 260. Next, the first inverter circuit 740 receives the logic high output from the level shifter circuit 730 and outputs a logic low (e.g., 0 volts). The first NOR circuit 750 receives the logic low output from the first inverter circuit 740 at a first input and a logic low output from the second control switch 240 at a second input, where the first NOR circuit 750 outputs a logic high (e.g., the first voltage supply 260). The first delay circuit 710 receives the logic high output from the first NOR circuit 750 and outputs a logic high (e.g., the first voltage supply 260). Specifically, the second inverter circuit 715 receives the logic high output from the first NOR circuit 750 and outputs a logic low (e.g., 0 volts). The third inverter circuit 717 receives the logic low output from the second inverter circuit 715 and outputs a logic high (e.g., voltage V2).

[0155] The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing through to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic high (e.g., voltage V2) output at its gate terminal from the third inverter circuit 717. Because the first source / drain terminal receives the second voltage supply 270 (which is lower than the voltage V2 at the gate of the p-type transistor 340), the p-type transistor 340 is non-conductive and does not pass the second voltage supply 270 to the voltage supply 115.

[0156] During the time window 820, the select signal 210 transitions from a logic high to a logic low and the second voltage supply 270 transitions from voltage VI to voltage V3, in preparation for the high performance mode of operation of the system 100. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V

[0157] Reference Figure 7When the select signal 210 is at logic low (e.g., 0 volts), the first control switch 220 outputs logic low (e.g., 0 volts). Specifically, the level shifter circuit 730 receives logic low from the select signal 210 and outputs logic low (e.g., 0 volts). Next, the first inverter circuit 740 receives the logic low output from the level shifter circuit 730 and outputs logic high (e.g., the first voltage supply 260). The first NOR circuit 750 receives the logic high output from the first inverter circuit 740 and outputs logic low (e.g., 0 volts). The first delay circuit 710 receives the logic low output from the first NOR circuit 750 and outputs logic low. Specifically, the second inverter circuit 715 receives the logic low output from the first NOR circuit 750 and outputs logic high (e.g., the first voltage supply 260). The third inverter circuit 717 receives the logic high output from the second inverter circuit 715 and outputs logic low (e.g., 0 volts).

[0158] The first voltage supply switch 230 receives the logic low output from the first control switch 220 and passes the second voltage supply 270 to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic low (e.g., 0 volts) output at its gate terminal from the third inverter circuit 717. As a result, the p-type transistor 340 is on and passes the second voltage supply 270 (e.g., converted from voltage VI to voltage V3) to the voltage supply 115.

[0159] Further, when the select signal 210 is at logic low (e.g., 0 volts), the second control switch 240 outputs logic high (e.g., the second voltage supply 270). Specifically, the second NOR circuit 760 receives the select signal 210 at a first input and the output of the first control switch 220 (e.g., node 719) at a second input. Because both the select signal 210 and the output of the first control switch 220 are at logic low (e.g., 0 volts), the output of the second NOR circuit 760 is at logic high (e.g., the second voltage supply 270). The second delay circuit 720 receives the logic high output from the second NOR circuit 760 and outputs a delayed version of logic high. Specifically, the fourth inverter circuit 725 receives the logic high output from the second NOR circuit 760 and outputs logic low. The fifth inverter circuit 727 receives the logic low output from the fourth inverter circuit 725 and outputs logic high (e.g., the second voltage supply 270) and further outputs a delayed version of the logic high output from the second NOR circuit 760. Figure 8The delay 860 in FIG. 8 represents a time delay of a delayed version of the logic high output from the second inverter circuit 760, which shows the delay between the transition of the output of the first control switch 220 (e.g., node 719) from logic high to logic low and the transition of the output of the second control switch 240 (e.g., node 729) from logic low to logic high. During the delay 860, because the output of the first control switch 220 (e.g., node 719) and the output of the second control switch 240 (e.g., node 729) are at logic low, the p-type transistors 340 and 360 (located in the first voltage supply switch 230 and the second voltage supply switch 250, respectively) are simultaneously turned on, thereby preventing the voltage supply 115 from floating during the transition of the select signal 210.

[0160] Referring to Figure 7 After the delay 860, the second voltage supply switch 250 receives a logic high output from the second control switch 240, which prevents the first voltage supply 260 from passing to the voltage supply 115 after the delay 860. Specifically, after the delay 860, the p-type transistor 360 receives a logic high (e.g., the second voltage supply 270) output at its gate terminal from the fifth inverter circuit 727. Because the p-type transistor 360 is turned on, the first voltage supply 260 is prevented from passing to the voltage supply 115. Figure 8 After the time 850 (e.g., the time 850 plus the delay 860), the voltage level of the second voltage supply 270 is higher than the first voltage supply 260. Thus, the p-type transistor 360 is non-conductive and does not pass the first voltage supply 260 to the voltage supply 115.

[0161] During the time window 830, the select signal 210 is at logic low and the second voltage supply 270 is at voltage V3. Because the second voltage supply 270 passes through the first voltage supply switch 230 to the voltage supply 115, the voltage supply 115 is at voltage V3. Thus, Figure 1 The circuit 120 receives a higher voltage supply to facilitate a high performance mode of operation in which the circuit 120 can operate the circuit faster at a higher frequency.

[0162] During the time window 840, the select signal 210 transitions from logic low to logic high and the second voltage supply 270 transitions from voltage V3 to voltage VI, in preparation for the normal mode of operation of the system 100. In some embodiments, the select signal 210 transitions from logic low to logic high at time 870, at which time the first voltage supply 260 and the second voltage supply 270 are at approximately the same voltage level. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the power supply voltage V DD Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the power supply voltage V

[0163] Referring to Figure 7 When the select signal 210 is at a logic high, the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 730 receives a logic high from the select signal 210 and outputs a logic high (e.g., the first voltage supply 260). Next, the first inverter circuit 740 receives the logic high output from the level shifter circuit 730 and outputs a logic low (e.g., 0 volts). The first NOR circuit 750 receives the logic low output from the first inverter circuit 740 at a first input and receives the output of the second control switch 240 (e.g., node 729) at a second input. Because the output of the first inverter circuit 740 and the output of the second control switch 240 are both at a logic low (e.g., 0 volts), the first NOR circuit 750 outputs a logic high (e.g., the first voltage supply 260). The first delay circuit 710 receives the logic high output from the first NOR circuit 750 and outputs a logic high delayed version. Specifically, the second inverter circuit 715 receives the logic high output from the first NOR circuit 750 and outputs a logic low. The third inverter circuit 717 receives the logic low output from the second inverter circuit 715 and outputs a logic high (e.g., the first voltage supply 260) and further outputs a delayed version of the logic high output of the first NOR circuit 750. Figure 8 The delay 880 in the timing diagram 800 represents the time delay of the delayed version of the logic high output of the first NOR circuit 750, which shows the delay between the output of the second control switch 240 (e.g., node 729) transitioning from a logic high to a logic low and the output of the first control switch 220 (e.g., node 719) transitioning from a logic low to a logic high. During the delay 880, because the output of the first control switch 220 (e.g., node 719) and the output of the second control switch 240 (e.g., node 729) are at a logic low, the p-type transistors 340 and 360 (located in the first voltage supply switch 230 and the second voltage supply switch 250, respectively) are both turned on, thereby preventing the voltage supply 115 from floating during the transition of the select signal 210.

[0164] Referring to Figure 7 After the delay 880, the first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing to the voltage supply 115. Specifically, after the delay 880, the p-type transistor 340 receives a logic high (e.g., the first voltage supply 260) output at its gate terminal from the third inverter circuit 717. After the time 870 (e.g., the time 870 plus the delay 880), the voltage level of the first voltage supply 260 is higher than the second voltage supply 270. Thus, the p-type transistor 340 is non-conductive and does not pass the second voltage supply 270 to the voltage supply 115. Figure 8 ​

[0165] Furthermore, when the select signal 210 is at a logic high, the second control switch 240 outputs a logic low (e.g., 0 volts). Specifically, the second NOR circuit 760 receives the select signal 210 at a first input and the output of the first control switch 220 (e.g., node 719) at a second input. Because both the select signal 210 and the output of the first control switch 220 are at a logic high (e.g., the second voltage supply 270), the output of the second NOR circuit 760 is at a logic low (e.g., 0 volts). The second delay circuit 720 receives the logic low output from the second NOR circuit 760 and outputs a logic low. Specifically, the fourth inverter circuit 725 receives the logic low output from the second NOR circuit 760 and outputs a logic high (e.g., the second voltage supply 270). The fifth inverter circuit 727 receives the logic high output from the fourth inverter circuit 725 and outputs a logic low (e.g., 0 volts).

[0166] After the delay 880, the second voltage supply switch 250 receives the logic low output from the second control switch 240 and passes the first voltage supply 260 to the voltage supply 115. Specifically, after the delay 880, the p-type transistor 360 receives the logic low (e.g., 0 volts) output from the fifth inverter circuit 727 at its gate terminal. Thus, the p-type transistor 360 is on and passes the first voltage supply 260 to the voltage supply 115.

[0167] Figure 9 A diagram of a voltage supply selection circuit 900 represented in a fourth circuit level is illustrated in accordance with some embodiments of the present disclosure. The voltage supply selection circuit 900 can represent the voltage supply selection circuit 110 of Figure 1 and Figure 2 In this example, the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD When the select signal 210 is at a logic high, the select signal 210 is at the voltage level of the second voltage supply 270 (e.g., the supply voltage V DD Furthermore, when the select signal 210 is at a logic low, the select signal 210 is at ground (e.g., 0 volts).

[0168] The first control switch 220 includes a level shifter circuit 930, a first inverter circuit 940, a first NAND circuit 950, and a first delay circuit 910. The level shifter circuit 930 receives (or is electrically coupled to) the select signal 210. In some embodiments, the level shifter circuit 930 sets the voltage level of the select signal 210 at its output to be in the same voltage domain as the first voltage supply 260 (e.g., the supply voltage V DDM(In the voltage domain). For example, if the selection signal 210 is at logic high (e.g., power supply voltage V... DD If the voltage level is specified, then the level offset circuit 930 outputs a logic high (e.g., power supply voltage V) located in the voltage domain of the first voltage supply 260. DDM (Voltage level). Conversely, if the selection signal 210 is logic low (e.g., 0 volts), the level offset circuit 930 output is grounded (e.g., 0 volts). The first inverter circuit 940 receives (or is electrically coupled to) and inverts the output of the second control switch 240. The first inverter circuit 950 receives (or is electrically coupled to) the output of the level offset circuit 930 at a first input and receives (or is electrically coupled to) the output of the first inverter circuit 940 at a second input. The first delay circuit 910 receives (or is electrically coupled to) the output of the first inverter circuit 950. The first delay circuit 910 includes a second inverter circuit 915, which receives (or is electrically coupled to) and inverts the output of the first inverter circuit 950. The first voltage supply switch 230 in the voltage supply selection circuit 900 has a... Figure 3 The voltage supply selection circuit 300 is represented by the same circuit level as the first voltage supply switch 230.

[0169] The second control switch 240 includes a fourth inverter circuit 960, a fifth inverter circuit 970, a second inverter circuit 980, and a second delay circuit 920. The fourth inverter circuit 960 receives (or is electrically coupled to) and inverts the selection signal 210. The fifth inverter circuit 970 receives (or is electrically coupled to) and inverts the output of the first control switch 220. The second inverter circuit 980 receives (or is electrically coupled to) the output of the fourth inverter circuit 960 at a first input and receives (or is electrically coupled to) the output of the fifth inverter circuit 970 at a second input. The second delay circuit 920 receives (or is electrically coupled to) the output of the second inverter circuit 980. The second delay circuit 920 includes a sixth inverter circuit 925, which receives (or is electrically coupled to) and inverts the output of the second inverter circuit 980. The second voltage supply switch 250 in the voltage supply selection circuit 900 has a... Figure 3 The voltage supply selection circuit 300 is represented by the same circuit level as the second voltage supply switch 250.

[0170] Figure 9 Voltage supply selection circuit 900 to be compatible with Figure 7 The voltage supply selection circuit 700 operates in a similar manner. For example, refer to... Figure 8 The waveforms 800, 860, and 880 are generated by... Figure 9The delay circuits 910 and 920 generate delays during the delays 860 and 880. During the delays 860 and 880, the first voltage supply switch 230 and the second voltage supply switch 250 are both on, thereby preventing the voltage supply 115 from floating during the transition of the selection signal 210. After the delay 860, the second voltage supply switch 250 is off. Further, after the delay 880, the first voltage supply switch 230 is off.

[0171] Figure 10 A diagram of a voltage supply selection circuit 1000 represented in a fifth circuit level is shown in accordance with some embodiments of the present disclosure. The voltage supply selection circuit 1000 can represent the voltage supply selection circuit 110 of Figure 1 and Figure 2 In this example, the selection signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD is in the voltage domain of the second voltage supply 270). For example, when the selection signal 210 is at a logic high, the selection signal 210 is at the voltage level of the second voltage supply 270 (e.g., the supply voltage V DD is at the voltage level of the second voltage supply 270). Further, when the selection signal 210 is at a logic low, the selection signal 210 is at ground (e.g., 0 volts).

[0172] The first control switch 220 includes a level shifter circuit 1030, a first inverter circuit 1040, a first AND circuit 1050, and a first delay circuit 1010. The level shifter circuit 1030 receives (or is electrically coupled to) the selection signal 210. In some embodiments, the level shifter circuit 1030 sets the voltage level of the selection signal 210 at its output to be in the same voltage domain as the first voltage supply 260 (e.g., the supply voltage V DDM is in the voltage domain of the first voltage supply 260). For example, if the selection signal 210 is at a logic high (e.g., the supply voltage V DD is at the voltage level of the first voltage supply 260), the level shifter circuit 1030 outputs a logic high (e.g., V DDMthe logic low (e.g., 0 volts) on the select signal 210, the level shifter circuit 1030 outputs ground (e.g., 0 volts). The first inverter circuit 1040 receives (or is electrically coupled to) and inverts the output of the level shifter circuit 1030. The first AND circuit 1050 receives (or is electrically coupled to) the output of the first inverter circuit 1040 at a first input and receives (or is electrically coupled to) the output of the second control switch 240 (e.g., node 1029) at a second input. The first delay circuit 1010 receives (or is electrically coupled to) the output of the first AND circuit 1050. The first delay circuit 1010 includes a second inverter circuit 1015 and a third inverter circuit 1017. The second inverter circuit 1015 receives (or is electrically coupled to) and inverts the output of the first AND circuit 1050. The third inverter circuit 1017 receives (or is electrically coupled to) and inverts the output of the second inverter circuit 1015. The first voltage supply switch 230 in the voltage supply selection circuit 1000 has the same circuit level representation as the first voltage supply switch 230 in the voltage supply selection circuit 300. Figure 3 The first voltage supply switch 230 in the voltage supply selection circuit 1000 has the same circuit level representation as the first voltage supply switch 230 in the voltage supply selection circuit 300.

[0173] The second control switch 240 includes a second AND circuit 1060 and a second delay circuit 1020. The second AND circuit 1060 receives (or is electrically coupled to) the select signal 210 at a first input and receives (or is electrically coupled to) the output of the first control switch 220 (e.g., node 1019) at a second input. The second delay circuit 1020 receives (or is electrically coupled to) the output of the second AND circuit 1060. The second delay circuit 1020 includes a fourth inverter circuit 1025 and a fifth inverter circuit 1027. The fourth inverter circuit 1025 receives (or is electrically coupled to) and inverts the output of the second AND circuit 1060. The fifth inverter circuit 1027 receives (or is electrically coupled to) and inverts the output of the fourth inverter circuit 1025. The second voltage supply switch 250 in the voltage supply selection circuit 1000 has the same circuit level representation as the second voltage supply switch 250 in the voltage supply selection circuit 300. Figure 3 The second voltage supply switch 250 in the voltage supply selection circuit 1000 has the same circuit level representation as the second voltage supply switch 250 in the voltage supply selection circuit 300.

[0174] Figure 11 An example waveform 1100 for the voltage supply selection circuit 1000 represented in the fifth circuit level is illustrated in accordance with some embodiments of the present disclosure. As described above, for the voltage supply selection circuit 1000, the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the power supply voltage V DD The voltage domain of the second voltage supply 270). In the waveform 1100, when Figure 1When the system 100 is in the normal mode of operation (e.g., the system 100 is not in the high performance mode of operation), the voltage VI represents the voltage level of the second voltage supply 270, the voltage V2 represents the voltage level of the first voltage supply 260, and the voltage V3 represents the voltage level of the second voltage supply 270 when the system 100 is in the high performance mode of operation (e.g., operating the circuitry faster at a higher frequency). The voltage level of the voltage V3 can be higher than the voltage level of the voltage V2, which can be higher than the voltage level of the voltage VI. In some embodiments, the voltage level of the first voltage supply 260 is approximately the same during the normal and high performance modes of operation of the system 100.

[0175] During the time window 1110, the select signal 210 is at a logic high (e.g., voltage VI), and the system 100 is in the normal mode of operation. Under this condition, the voltage supply 115 is electrically coupled to the first voltage supply 260. Referring to FIG. 10, the first control switch 220 is at a logic low (e.g., 0 volts) and the second control switch 240 is at a logic high (e.g., voltage V2). The first control switch 220 is at a logic low because the select signal 210 is at a logic high. The second control switch 240 is at a logic high because the first control switch 220 is at a logic low. Figure 10 When the select signal 210 is at a logic high (e.g., voltage VI), the second control switch 240 outputs a logic low (e.g., 0 volts). Specifically, the second NAND circuit 1060 receives the select signal 210 at a first input and the output of the first control switch 220 (which is at a logic high, as described below) at a second input. Thus, the second NAND circuit 1060 outputs a logic low (e.g., 0 volts). The second delay circuit 1020 receives the logic low output from the second control switch 240 and outputs a logic low to the second voltage supply switch 250. Specifically, the fourth inverter circuit 1025 receives the logic low output from the second NAND circuit 1060 and outputs a logic high (e.g., the second voltage supply 270). The fifth inverter circuit 1027 receives the logic high output from the fourth inverter circuit 1025 and outputs a logic low (e.g., 0 volts). The second voltage supply switch 250 receives the logic low output from the second control switch 240 and passes the first voltage supply 260 to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic low (e.g., 0 volts) output from the fifth inverter circuit 1027 at its gate terminal. Thus, the p-type transistor 360 is on and passes the first voltage supply 260 (e.g., voltage V2) to the voltage supply 115.

[0176] Furthermore, when the select signal 210 is at a logic high (e.g., voltage VI), the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 1030 receives a logic high from the select signal 210 (which is in the voltage domain of the second voltage supply 270) and outputs a logic high in the voltage domain of the first voltage supply 260. Next, the first inverter circuit 1040 receives the logic high output from the level shifter circuit 1030 and outputs a logic low (e.g., 0 volts). The first NAND circuit 1050 receives the logic low output from the first inverter circuit 1040 at a first input and a logic low output from the second control switch 240 at a second input, where the first NAND circuit 1050 outputs a logic high (e.g., the first voltage supply 260). The first delay circuit 1010 receives the logic high output from the first NAND circuit 1050 and outputs a logic high (e.g., the first voltage supply 260). Specifically, the second inverter circuit 1015 receives the logic high output from the first NAND circuit 1050 and outputs a logic low (e.g., 0 volts). The third inverter circuit 1017 receives the logic low output from the second inverter circuit 1015 and outputs a logic high (e.g., voltage V2).

[0177] The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing through to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic high (e.g., voltage V2) output from the third inverter circuit 1017 at its gate terminal. Because the first source / drain terminal receives the second voltage supply 270 (which is lower than the voltage V2 at the gate of the p-type transistor 340), the p-type transistor 340 is non-conductive and does not pass the second voltage supply 270 to the voltage supply 115.

[0178] During the time window 1120, the select signal 210 transitions from a logic high to a logic low and the second voltage supply 270 transitions from voltage VI to voltage V3, in preparation for the high performance mode of operation of the system 100. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DD When the second voltage supply 270 transitions from voltage VI to voltage V3, the select signal 210 transitions in a similar manner while the select signal 210 is at a logic high, because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V

[0179] Reference Figure 10When the select signal 210 is at a logic low (e.g., 0 volts), the first control switch 220 outputs a logic low (e.g., 0 volts). Specifically, the level shifter circuit 1030 receives a logic low from the select signal 210 and outputs a logic low (e.g., 0 volts). Next, the first inverter circuit 1040 receives the logic low output from the level shifter circuit 1030 and outputs a logic high (e.g., the first voltage supply 260). The first NAND circuit 1050 receives a logic high output at a first input from the first inverter circuit 1040 and a logic high output at a second input from the second control switch 240 (as described below). Thus, the first NAND circuit 1050 outputs a logic low (e.g., 0 volts). The first delay circuit 1010 receives the logic low output from the first NAND circuit 1050 and outputs a delayed version of the logic low. Specifically, the second inverter circuit 1015 receives the logic low output from the first NAND circuit 1050 and outputs a logic high (e.g., the first voltage supply 260). The third inverter circuit 1017 receives the logic high output from the second inverter circuit 1015 and outputs a logic low (e.g., 0 volts) and further outputs a delayed version of the logic low output from the first NAND circuit 1050. In Figure 11 During the delay 1160, which represents a time delay of the delayed version of the logic low output from the first NAND circuit 1050, the output (e.g., node 1029) of the second control switch 240 transitions from a logic low to a logic high and the output (e.g., node 1019) of the first control switch 220 transitions from a logic high to a logic low. During the delay 1160, because the output (e.g., node 1019) of the first control switch 220 and the output (e.g., node 1029) of the second control switch 240 are at a logic high, the p-type transistors 340 and 360 (located in the first voltage supply switch 230 and the second voltage supply switch 250, respectively) are both non-conductive at the same time, thereby preventing the voltage supply 115 from receiving the first voltage supply 260 or the second voltage supply 270 during the transition of the select signal 210.

[0180] Reference is made to Figure 10 After the delay 1160, the first voltage supply switch 230 receives the logic low output from the first control switch 220 and passes the second voltage supply 270 to the voltage supply 115. Specifically, after the delay 1160, the p-type transistor 340 receives a logic low (e.g., 0 volts) output at its gate terminal from the third inverter circuit 1017. Thus, the p-type transistor 340 is conductive and passes the second voltage supply 270 (e.g., transitions from voltage VI to voltage V3) to the voltage supply 115.

[0181] Further, when the select signal 210 is at a logic low (e.g., 0 volts), the second control switch 240 outputs a logic high (e.g., the second voltage supply 270). Specifically, the second NAND circuit 1060 receives the select signal 210 at a first input and the output of the first control switch 220 (e.g., node 1019) at a second input. Because both the select signal 210 and the output of the first control switch 220 are at a logic low (e.g., 0 volts), the output of the second NAND circuit 1060 is at a logic high (e.g., the second voltage supply 270). The second delay circuit 1020 receives the logic high output from the second NAND circuit 1060 and outputs a logic high output. Specifically, the fourth inverter circuit 1025 receives the logic high output from the second NAND circuit 1060 and outputs a logic low. The fifth inverter circuit 1027 receives the logic low output from the fourth inverter circuit 1025 and outputs a logic high (e.g., the second voltage supply 270).

[0182] The second voltage supply switch 250 receives the logic high output from the second control switch 240, which prevents the first voltage supply 260 from passing to the voltage supply 115. Specifically, the p-type transistor 360 receives the logic high (e.g., the second voltage supply 270) output at its gate terminal from the fifth inverter circuit 1027. The p-type transistor 360 is non-conductive and prevents the second voltage supply 270 (e.g., from voltage VI to voltage V3) from passing to the voltage supply 115. Figure 11 At time 1150, the first voltage supply 260 and the second voltage supply 270 are at the same or approximately the same voltage level. Thus, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., from voltage VI to voltage V3) from passing to the voltage supply 115.

[0183] During the time window 1130, the select signal 210 is at a logic low and the second voltage supply 270 is at voltage V3. Because the second voltage supply 270 passes to the voltage supply 115 through the first voltage supply switch 230, the voltage supply 115 is at voltage V3. Thus, the p-type transistor 340 is non-conductive and prevents the second voltage supply 270 (e.g., from voltage VI to voltage V3) from passing to the voltage supply 115. Figure 1 The circuit 120 receives a higher voltage supply to facilitate a high performance mode of operation, operating the circuit faster at higher frequencies.

[0184] During the time window 1140, the select signal 210 transitions from a logic low to a logic high and the second voltage supply 270 transitions from voltage V3 to voltage VI, in preparation for the normal mode of operation of the system 100. In some embodiments, the select signal 210 transitions from a logic low to a logic high at time 1170, when the first voltage supply 260 and the second voltage supply 270 are approximately at the same voltage level. Because the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., the supply voltage V DDWhen the second voltage supply 270 transitions from voltage V3 to voltage VI, the select signal 210 transitions in a similar manner while the select signal 210 is at a logic high.

[0185] Referring to Figure 10 When the select signal 210 is at a logic high, the first control switch 220 outputs a logic high (e.g., the first voltage supply 260). Specifically, the level shifter circuit 1030 receives a logic high from the select signal 210 and outputs a logic high (e.g., the first voltage supply 260). Next, the first inverter circuit 1040 receives the logic high output from the level shifter circuit 1030 and outputs a logic low (e.g., 0 volts). The first NAND circuit 1050 receives the logic low output from the first inverter circuit 1040 at a first input and receives the output of the second control switch 240 (e.g., node 1029) at a second input. Because the output of the first inverter circuit 1040 and the output of the second control switch 240 are both at a logic low (e.g., 0 volts), the first NAND circuit 1050 outputs a logic high (e.g., the first voltage supply 260). The first delay circuit 1010 receives the logic high output from the first NAND circuit 1050 and outputs a logic high. Specifically, the second inverter circuit 1015 receives the logic high output from the first NAND circuit 1050 and outputs a logic low. The third inverter circuit 1017 receives the logic low output from the second inverter circuit 1015 and outputs a logic high (e.g., the first voltage supply 260).

[0186] The first voltage supply switch 230 receives the logic high output from the first control switch 220, which prevents the second voltage supply 270 from passing to the voltage supply 115. Specifically, the p-type transistor 340 receives the logic high (e.g., the first voltage supply 260) output from the third inverter circuit 1017 at its gate terminal. At time 1170, the first voltage supply 260 and the second voltage supply 270 are at the same or approximately the same voltage level. Thus, the p-type transistor 340 is non-conducting and does not pass the second voltage supply 270 to the voltage supply 115.

[0187] Furthermore, when the selection signal 210 is logic high, the second control switch 240 outputs logic low (e.g., 0 volts). Specifically, the second inverter circuit 1060 receives the selection signal 210 at the first input and receives the output of the first control switch 220 (e.g., node 1019) at the second input. Because both the selection signal 210 and the output of the first control switch 220 are logic high (e.g., the second voltage supply 270), the output of the second inverter circuit 1060 is logic low (e.g., 0 volts). The second delay circuit 1020 receives the logic low output from the second inverter circuit 1060 and outputs a delayed version of the logic low. Specifically, the fourth inverter circuit 1025 receives the logic low output from the second inverter circuit 1060 and outputs logic high (e.g., the second voltage supply 270). The fifth inverter circuit 1027 receives the logic high output from the fourth inverter circuit 1025 and outputs logic low (e.g., 0 volts), and further outputs a delayed version of the logic low output from the second inverter circuit 1060. Figure 11 The delay 1180 represents a delayed version of the logic low output from the second inverse circuit 1060, illustrating the delay between the logic low transition of the output of the first control switch 220 (e.g., node 1019) and the logic high transition of the output of the second control switch 240 (e.g., node 1029) and the logic low transition. During delay 1180, because the outputs of the first control switch 220 (e.g., node 1019) and the second control switch 240 (e.g., node 1029) are logic high, p-type transistors 340 and 360 (located in the first voltage supply switch 230 and the second voltage supply switch 250, respectively) are simultaneously de-energized, thereby preventing voltage supply 115 from receiving either the first voltage supply 260 or the second voltage supply 270 during the transition of selection signal 210.

[0188] After a delay of 1180, the second voltage supply switch 250 receives a logic low output from the second control switch 240 and supplies the first voltage supply 260 to the voltage supply 115. Specifically, after a delay of 1180, the p-type transistor 360 receives a logic low (e.g., 0 volts) output at its gate terminal from the fifth inverter circuit 1027. Therefore, the p-type transistor 360 turns on and supplies the first voltage supply 260 to the voltage supply 115.

[0189] Figure 12 A diagram illustrating a voltage supply selection circuit 1200, represented as a sixth circuit level, is shown according to some embodiments of this disclosure. The voltage supply selection circuit 1200 can represent... Figure 1 as well as Figure 2 The voltage supply selection circuit 110. In this example, the selection signal 210 is located in the voltage domain of the second voltage supply 270 (e.g., power supply voltage V). DDthe voltage domain of the first voltage supply 260 (e.g., power supply voltage V DD the voltage domain of the first voltage supply 260 (e.g., power supply voltage V

[0190] The first control switch 220 includes a level shifter circuit 1230, a first inverter circuit 1240, a first NOR circuit 1250, and a first delay circuit 1210. The level shifter circuit 1230 receives (or is electrically coupled to) the select signal 210. In some embodiments, the level shifter circuit 1230 sets the voltage level of the select signal 210 at its output to be in the same voltage domain as the first voltage supply 260 (e.g., power supply voltage V DDM the voltage domain of the first voltage supply 260 (e.g., power supply voltage V DD the voltage domain of the first voltage supply 260 (e.g., power supply voltage V DDM the voltage domain of the first voltage supply 260 (e.g., power supply voltage VIn contrast, if the select signal 210 is at a logic low (e.g., 0 volts), the level shifter circuit 1230 outputs ground (e.g., 0 volts). The first inverter circuit 1240 receives (or is electrically coupled to) and inverts the output of the second control switch 240. The first NOR circuit 1250 receives (or is electrically coupled to) the output of the level shifter circuit 1230 at a first input and receives (or is electrically coupled to) the output of the first inverter circuit 1240 at a second input. The first delay circuit 1210 receives (or is electrically coupled to) the output of the first NOR circuit 1250. The first delay circuit 1210 includes a second inverter circuit 1215 that receives (or is electrically coupled to) and inverts the output of the first NOR circuit 1250. The first voltage supply switch 230 in the voltage supply selection circuit 1200 has the same circuit level representation as the first voltage supply switch 230 in the voltage supply selection circuit 300 of FIG. 3. Figure 3

[0191] The second control switch 240 includes a third inverter circuit 1260, a fourth inverter circuit 1270, a second NOR circuit 1280, and a second delay circuit 1220. The third inverter circuit 1260 receives (or is electrically coupled to) and inverts the select signal 210. The fourth inverter circuit 1270 receives (or is electrically coupled to) and inverts the output of the first control switch 220. The second NOR circuit 1280 receives (or is electrically coupled to) the output of the third inverter circuit 1260 at a first input and receives (or is electrically coupled to) the output of the fourth inverter circuit 1270 at a second input. The second delay circuit 1220 receives (or is electrically coupled to) the output of the second NOR circuit 1280. The second delay circuit 1220 includes a fifth inverter circuit 1225 that receives (or is electrically coupled to) and inverts the output of the second NOR circuit 1280. The second voltage supply switch 250 in the voltage supply selection circuit 1200 has the same circuit level representation as the second voltage supply switch 250 in the voltage supply selection circuit 300 of Figure 3 The voltage supply selection circuit 1200 of

[0192] Figure 12 The voltage supply selection circuit 1200 of Figure 10 operates in a similar manner as the voltage supply selection circuit 1000 of Figure 11 Referring to the waveform 1100 of Figure 12 the delays 1160 and 1180 are the delays generated by the delay circuits 1210 and 1220, respectively. During the delays 1160 and 1180, the first voltage supply switch 230 and the second voltage supply switch 250 are both non-conductive, thereby preventing the voltage supply 115 from receiving either the first voltage supply 260 or the second voltage supply 270 during the transition of the select signal 210. After the delay 1160, the first voltage supply switch 230 becomes conductive. Also, after the delay 1180, the second voltage supply switch 250 becomes conductive.

[0193] Figure 13 An example waveform 1300 for optimizing the select signal switching window of a voltage supply selection circuit is illustrated in accordance with some embodiments of the present disclosure. In this example, the select signal 210 is in the voltage domain of the second voltage supply 270 (e.g., a power supply voltage V DD the voltage domain of the second voltage supply 270). In the waveform 1300, when Figure 1When the system 100 is in a normal mode of operation (e.g., the system 100 is not in a high performance mode of operation), the voltage VI represents the voltage level of the second voltage supply 270, the voltage V2 represents the voltage level of the first voltage supply 260, and the voltage V3 represents the voltage level of the second voltage supply 270 when the system 100 is in a high performance mode of operation (e.g., operating the circuitry faster at a higher frequency). The voltage level of the voltage V3 can be higher than the voltage level of the voltage V2, which can be higher than the voltage level of the voltage VI. In some embodiments, the voltage level of the first voltage supply 260 is approximately the same during the normal and high performance modes of operation of the system 100.

[0194] The switching window 1310 refers to a time window in which the selection signal 210 should transition from a logic high to a logic low in order to minimize leakage current. The switching window 1320 refers to a time window in which the selection signal 210 should transition from a logic low to a logic high in order to minimize leakage current. In some embodiments, the switching windows 1310 and 1320 can be based on the voltage difference between the first voltage supply 260 and the second voltage supply 270 at different points in time. In some embodiments, the switching windows 1310 and 1320 can be set based on the following condition:

[0195] | (voltage supply 115) - (first voltage supply 260) - (second voltage supply 270) |.

[0196] In other words, in some embodiments, the selection signal 210 should transition from a logic high to a logic low within a time window when the voltage level of the voltage supply 115 is greater than the absolute value of the difference between the first voltage supply 260 and the second voltage supply 270, and vice versa. In some embodiments, if the selection signal 210 transitions within this condition, leakage current can be minimized, thereby reducing power consumption.

[0197] Figure 14 A diagram of a method 1400 for selecting a voltage supply is illustrated in accordance with some embodiments of the present disclosure. The operations depicted in the method 1400 can be performed by, for example, Figure 1 a system 100, Figure 2 a voltage supply selection circuit 110, Figure 3 a voltage supply selection circuit 300, Figure 5 a voltage supply selection circuit 500, Figure 7 a voltage supply selection circuit 700, Figure 9 a voltage supply selection circuit 900, Figure 10 a voltage supply selection circuit 1000, and Figure 12the voltage supply selection circuit 1200. It should be understood that not all of the operations need to be performed to implement the disclosure provided herein, and one or more additional operations can be performed. Also, some operations can be performed simultaneously, or in a different order than shown in Figure 14

[0198] In operation 1410, a control signal and a first voltage supply are received by a first control switch. For example, referring to Figure 2 , the first control switch 220 receives the selection signal 210 (also referred to herein as the "control signal 210") and the first voltage supply 260. In some embodiments, the first control switch 220 can also receive the output of the second control switch 240, as shown in Figure 7 the voltage supply selection circuit 700, Figure 9 the voltage supply selection circuit 900, Figure 10 the voltage supply selection circuit 1000, and Figure 12 the voltage supply selection circuit 1200.

[0199] In operation 1420, a second voltage supply is received by a first voltage supply switch electrically coupled to the first control switch. For example, referring to Figure 2 , the first voltage supply switch 230 receives the second voltage supply 270 and is electrically coupled to the first control switch 220.

[0200] In operation 1430, a control signal and a second voltage supply are received by a second control switch. For example, referring to Figure 2 , the second control switch 240 receives the selection signal 210 (or the control signal 210) and the second voltage supply 270. In some embodiments, the second control switch 240 can also receive the output of the first control switch 220, as shown in Figure 7 the voltage supply selection circuit 700, Figure 9 the voltage supply selection circuit 900, Figure 10 the voltage supply selection circuit 1000, and Figure 12 the voltage supply selection circuit 1200.

[0201] In operation 1440, a first voltage supply is received by a second voltage supply switch electrically coupled to the second control switch. For example, referring to Figure 2 , the second voltage supply switch 250 receives the first voltage supply 260 and is electrically coupled to the second control switch 240.

[0202] For operations 1410 and 1430, based on the outputs of the first control switch 220 and the second control switch 240 being opposite each other, the first control switch 220 and the second control switch 240 can use a delay circuit (e.g. Figure 7 ​Delay circuit 710, Figure 9 Delay circuit 910, Figure 10 The delay circuit 1010 and Figure 12 The delay circuit 1210 is used to generate a timing delay, so that when the selection signal 210 (or control signal 210) transitions from logic high to logic low or from logic low to logic high, the first voltage supply switch 230 and the second voltage supply switch 250 will be activated or deactivated for a period of time.

[0203] The following text continues the description Figure 14 In method 1400, during operation 1450, a first voltage supply and a second voltage supply are selectively output according to a control signal. For example, refer to... Figure 4 Waveform 400 Figure 6 Waveform 600 Figure 8 Waveform 800, Figure 11 Waveform 1100 and Figure 13 The waveform 1300, the first voltage supply 260 and the second voltage supply 270 can be selectively output to the voltage supply 115 based on the selection signal 210 (or control signal 210).

[0204] Embodiments of this disclosure describe a selection circuit that can increase or decrease a voltage supply based on a selection signal (or control signal). For example, when increasing the voltage supply to support high-performance mode operation of the system (e.g., operating the circuit at a higher frequency and faster speed), embodiments of this disclosure increase a single voltage supply rather than multiple voltage supplies, thereby simplifying circuit design. Furthermore, when decreasing the voltage supply to reduce system power consumption, embodiments of this disclosure decrease a single voltage supply rather than multiple voltage supplies, again simplifying circuit design.

[0205] Embodiments of this disclosure describe a selection circuit. This selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is used to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is used to receive a second voltage supply. The second control switch is used to receive a control signal and a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and is used to receive the first voltage supply. The first and second voltage supply switches are used to selectively output the first and second voltage supplies based on the control signal.

[0206] In some embodiments of the selection circuit, the first control switch includes a level offset circuit for receiving a control signal and electrically coupled to an inverter circuit, wherein the level offset circuit and the inverter circuit are used to receive a first voltage supply.

[0207] In some embodiments of the selection circuit, the first voltage supply switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to: receive an output of the first control switch at the gate terminal; receive the second voltage supply at the first source / drain terminal; and output the second voltage supply at the second source / drain terminal.

[0208] In some embodiments of the selection circuit, the second control switch includes an inverter circuit to receive the control signal and the second voltage supply.

[0209] In some embodiments of the selection circuit, the second control switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to: receive an output of the second control switch at the gate terminal; receive the first voltage supply at the first source / drain terminal; and output the first voltage supply at the second source / drain terminal.

[0210] In some embodiments of the selection circuit, the first control switch includes an inverter circuit to receive the control signal and the first voltage supply.

[0211] In some embodiments of the selection circuit, the second control switch includes a level shifter circuit to receive the control signal and electrically coupled to the inverter circuit, and the level shifter circuit and the inverter circuit are to receive the first voltage supply.

[0212] In some embodiments of the selection circuit, the first control switch includes a first output electrically coupled to an input of the second control switch, and the second control switch includes a second output electrically coupled to an input of the first control switch.

[0213] In some embodiments of the selection circuit, each of the first control switch and the second control switch includes a delay circuit.

[0214] In some embodiments of the selection circuit, the delay circuit includes one or more inverter circuits.

[0215] Embodiments of the present disclosure describe a selection system. The selection system includes a circuit (e.g., a processor) and a voltage supply selection circuit electrically coupled to the circuit. The circuit is to receive a voltage supply. The voltage supply selection circuit is to selectively provide a first voltage supply and a second voltage supply as the voltage supply to the circuit. The voltage supply selection circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is to receive a control signal and the first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is to receive the second voltage supply. The second control switch is to receive the control signal and the second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and is to receive the first voltage supply. The first and second voltage supply switches are to selectively output the first and second voltage supplies based on the control signal.

[0216] In some embodiments of the selection system, the circuit includes a processor.

[0217] In some embodiments of the selection system, the first control switch includes a level shifter circuit to receive the control signal and electrically coupled to an inverter circuit, and wherein the level shifter and inverter circuits are to receive the first voltage supply.

[0218] In some embodiments of the selection system, the first voltage supply switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to: receive an output of the first control switch at the gate terminal; receive the second voltage supply at the first source / drain terminal; and output the second voltage supply at the second source / drain terminal.

[0219] In some embodiments of the selection system, the second control switch includes an inverter circuit to receive the control signal and the second voltage supply.

[0220] In some embodiments of the selection system, the second control switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to: receive an output of the second control switch at the gate terminal; receive the first voltage supply at the first source / drain terminal; and output the first voltage supply at the second source / drain terminal.

[0221] In some embodiments of the selection system, the first control switch includes a first output electrically coupled to an input of the second control switch, and the second control switch includes a second output electrically coupled to an input of the first control switch.

[0222] Embodiments of the present disclosure describe a selection method. The selection method includes receiving a selection signal and a first voltage using a first switch, receiving a second voltage supply using a second switch electrically coupled to the first switch, receiving the selection signal and a second voltage using a third switch, receiving the first voltage using a fourth switch electrically coupled to the third switch, and in response to the selection signal transitioning from a first logic level to a second logic level and in response to the first and second voltages being substantially at the same voltage level, transitioning the voltage supply from the first voltage to the second voltage. The method further includes receiving an output of the second control switch using a first control switch and receiving an output of the first control switch using a second control switch.

[0223] In some embodiments of the selection method, the step of receiving the selection signal and the first voltage using the first switch includes the step of receiving an output of the third switch using the first switch. The step of receiving the selection signal and the second voltage using the third switch includes the step of receiving an output of the first switch using the third switch.

[0224] In some embodiments of the selection method, the step of receiving the outputs of the first and third switches includes the step of simultaneously enabling or disabling the third and fourth switches for a period of time.

[0225] It is to be understood that the embodiments of the present disclosure, rather than the abstract, are intended to be illustrative of the scope of the application. The abstract may set forth one or more, but not all possible embodiments of the present disclosure, and thus, the abstract is not intended to limit the scope of the application in any way.

[0226] The foregoing outlines features of several embodiments so that a thorough comprehension of the present disclosure can be attained. It should be appreciated that those skilled in the art can readily apply the broad principles of the present disclosure to a wide variety of other processes and structures without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and spirit of the present disclosure.

Claims

1. A selection circuit, characterized by, Comprises: a first control switch to receive a control signal and a first voltage supply; a first voltage supply switch electrically coupled to the first control switch and to receive a second voltage supply; a second control switch to receive the control signal and the second voltage supply; and a second voltage supply switch electrically coupled to the second control switch and to receive the first voltage supply, wherein the first voltage supply switch and the second voltage supply switch are to selectively output the first voltage supply and the second voltage supply based on the control signal, and wherein the control signal is to transition from a first voltage level to a second voltage level when in a logic high state prior to the selection circuit transitioning between the first voltage supply and the second voltage supply. The first control switch comprises a level shifter circuit to receive the control signal and electrically coupled to an inverter circuit, and wherein the level shifter and the inverter circuit are to receive the first voltage supply.

2. The selection circuit of claim 1, wherein, The first voltage supply switch comprises a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to:

3. The selection circuit of claim 1, wherein, receive an output of the first control switch at the gate terminal; receive the second voltage supply at the first source / drain terminal; and output the second voltage supply at the second source / drain terminal. The second control switch comprises a logic circuit to receive the control signal and the second voltage supply.

4. The selection circuit of claim 1, wherein, The logic circuit comprises a NOR circuit.

5. The selection circuit of claim 4, wherein, The second voltage supply switch comprises a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is to:

6. The selection circuit of claim 1, wherein, receive an output of the second control switch at the gate terminal; receive the first voltage supply at the first source / drain terminal; and output the first voltage supply at the second source / drain terminal. The first control switch comprises an inverter circuit to receive the control signal and the first voltage supply.

7. The selection circuit of claim 1, wherein, The second control switch comprises a level shifter circuit to receive the control signal and electrically coupled to an inverter circuit, and wherein the level shifter circuit and the inverter circuit are to receive the first voltage supply.

8. The selection circuit of claim 1, wherein, The first control switch comprises a first output electrically coupled to an input of the second control switch, and wherein the second control switch comprises a second output electrically coupled to an input of the first control switch.

9. The selection circuit of claim 1, wherein, Each of the first control switch and the second control switch comprises a delay circuit.

10. The selection circuit of claim 9, wherein, The delay circuit comprises one or more inverter circuits.

11. The selection circuit of claim 10, wherein, It comprises:

12. A selection system characterized by, a circuit to receive a voltage supply; and a voltage supply selection circuit electrically coupled to the circuit and to selectively provide a first voltage supply and a second voltage supply as the voltage supply to the circuit, wherein the voltage supply selection circuit comprises: a first control switch to receive a control signal and the first voltage supply; ​ a first voltage supply switch electrically coupled to the first control switch and configured to receive the second voltage supply; a second control switch configured to receive the control signal and the second voltage supply; and a second voltage supply switch electrically coupled to the second control switch and configured to receive the first voltage supply, wherein the first voltage supply switch and the second voltage supply switch are configured to selectively output the first voltage supply and the second voltage supply based on the control signal, and wherein the control signal is configured to transition from a first voltage level to a second voltage level that is higher when in a logic high state.

13. The selection system of claim 12, wherein, The circuit includes a processor.

14. The selection system of claim 12, wherein, The first control switch includes a level shifter circuit configured to receive the control signal and electrically coupled to an inverter circuit, and wherein the level shifter circuit and the inverter circuit are configured to receive the first voltage supply.

15. The selection system of claim 12, wherein, The first voltage supply switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is configured to: receive an output of the first control switch at the gate terminal; receive the second voltage supply at the first source / drain terminal; and output the second voltage supply at the second source / drain terminal.

16. The selection system of claim 12, wherein, The second control switch includes a logic circuit configured to receive the control signal and the second voltage supply.

17. The selection system of claim 16, wherein, The logic circuit includes a NOR circuit.

18. The selection system of claim 12, wherein, The second voltage supply switch includes a p-type transistor having a gate terminal, a first source / drain terminal, and a second source / drain terminal, and wherein the p-type transistor is configured to: receive an output of the second control switch at the gate terminal; receive the first voltage supply at the first source / drain terminal; and output the first voltage supply at the second source / drain terminal.

19. The selection system of claim 12, wherein, The first control switch includes a first output electrically coupled to an input of the second control switch, and wherein the second control switch includes a second output electrically coupled to an input of the first control switch.

20. A selection method characterized by, It includes the following steps: receiving a select signal and a first voltage using a first switch; receiving a second voltage using a second switch electrically coupled to the first switch; receiving the select signal and the second voltage using a third switch; receiving the first voltage using a fourth switch electrically coupled to the third switch; and in response to the select signal transitioning from a first logic level to a second logic level and in response to the first voltage and the second voltage being substantially at the same voltage level, transitioning a voltage supply from the first voltage to the second voltage, wherein the select signal is configured to transition from a first voltage to a second voltage when in the first logic level.

21. The selection method of claim 20, wherein, The step of receiving the select signal and the first voltage includes the step of receiving an output of the third switch using the first switch, and wherein the step of receiving the select signal and the second voltage includes the step of receiving an output of the first switch using the third switch.

22. The selection method of claim 21, wherein, The step of receiving the outputs of the first switch and the third switch includes the step of simultaneously enabling or disabling the third switch and the fourth switch for a period of time.

23. A selection circuit, comprising: Including: a first control switch to receive a control signal and a first voltage supply, wherein the first control switch includes an inverter circuit to receive the control signal and the first voltage supply, and wherein the control signal is to transition from a first voltage level to a second voltage level when in a logic high state; a first voltage supply switch electrically coupled to the first control switch and to receive a second voltage supply; a second control switch to receive the control signal and the second voltage supply; and a second voltage supply switch electrically coupled to the second control switch and to receive the first voltage supply, wherein the first voltage supply switch and the second voltage supply switch are to selectively output the first voltage supply and the second voltage supply based on the control signal.

24. The selection circuit of claim 23, wherein, The first control switch further includes a level shifter circuit to receive the control signal and the first voltage supply and electrically coupled to the inverter circuit.

25. The selection circuit of claim 23, wherein, The first voltage supply switch further includes a p-type transistor to output the second voltage supply based on an output of the first control switch.

26. The selection circuit of claim 23, wherein, The second control switch includes another inverter circuit to receive the second voltage supply.

27. The selection circuit of claim 23, wherein, The second voltage supply switch includes a p-type transistor to output the first voltage supply based on an output of the second control switch.

28. The selection circuit of claim 23, wherein, The first control switch includes a first output electrically coupled to an input of the second control switch, and wherein the second control switch includes a second output electrically coupled to an input of the first control switch.

29. The selection circuit of claim 23, wherein, Each of the first control switch and the second control switch includes a delay circuit.

30. The selection circuit of claim 29, wherein, The delay circuit includes one or more inverter circuits.

31. A selection circuit, comprising: Including: a first control switch to receive a control signal and a first voltage supply; a first voltage supply switch electrically coupled to the first control switch and to receive a second voltage supply; a second control switch to receive the control signal and the second voltage supply, wherein the second control switch includes a level shifter circuit to receive the control signal and the first voltage supply; and a second voltage supply switch electrically coupled to the second control switch and to receive the first voltage supply, wherein the first voltage supply switch and the second voltage supply switch are to selectively output the first voltage supply and the second voltage supply based on the control signal, and wherein the control signal is to transition from a first voltage level to a second voltage level when in a logic high state.

32. The selection circuit of claim 31, wherein, The first control switch includes another level shifter circuit to receive the control signal and the first voltage supply.

33. The selection circuit of claim 31, wherein, The first voltage supply switch includes a p-type transistor to output the second voltage supply based on an output of the first control switch.

34. The selection circuit of claim 31, wherein, The second control switch further includes an inverter circuit to receive the first voltage supply and electrically coupled to the level shifter circuit.

35. The selection circuit of claim 31, wherein, The second control switch further includes an inverter circuit to receive the second voltage supply.

36. The selection circuit of claim 31, wherein, The second voltage supply switch includes a p-type transistor to output the first voltage supply based on an output of the second control switch.

37. The selection circuit of claim 31, wherein, The first control switch includes a first output electrically coupled to an input of the second control switch, and wherein the second control switch includes a second output electrically coupled to an input of the first control switch.

38. The selection circuit of claim 31, wherein, Each of the first control switch and the second control switch includes a delay circuit.

39. A method of selection, comprising: It includes the following steps: receiving a selection signal and a first voltage using a first switch, wherein the first switch includes an inverter circuit to receive a control signal and the first voltage supply, and wherein the control signal is to transition from a first voltage level to a second voltage level when in a logic high state; receiving a second voltage using a second switch; receiving the selection signal and the second voltage using a third switch; receiving the first voltage using a fourth switch; and in response to the selection signal transitioning from a first logic level to a second logic level and in response to the first voltage and the second voltage being substantially at the same voltage level, transitioning a voltage supply from the first voltage to the second voltage.

40. The selection method of claim 39, wherein, The step of receiving the selection signal and the first voltage includes the step of receiving an output of the third switch using the first switch.

41. The selection method of claim 39, wherein the step of selecting is performed by a user. The step of receiving the selection signal and the second voltage includes the step of receiving an output of the first switch using the third switch.

42. The selection method of claim 39, wherein the step of selecting is performed by a user. The steps of receiving the selection signal and the first voltage and receiving the selection signal and the second voltage include the step of simultaneously enabling or disabling the third switch and the fourth switch for a period of time.

Images