Communication method of FPGA-based magnetic levitation needle array system and PC

Abstract

A kind of communication method of magnetic levitation needle array system based on FPGA and PC, comprising the following steps: PC sends drive data protocol to FPGA;FPGA receives first byte data of data frame through serial port, and compares first byte data with set drive data frame header;If first byte data is drive data frame header, continue to receive remaining data to cache space, and wait to receive drive data frame tail;FPGA analyzes the data value received, judges the integrity and correctness of data sending frame by CRC check;If correct, data is taken out from cache space and placed in specified register, and response data frame is sent to PC;PC receives the response data frame sent by FPGA;Magnetic levitation needle array system takes out data instruction from specified register to complete knitting action.The design not only improves data transmission speed, but also improves data transmission reliability.

Description

Technical Field

[0001] This invention relates to the field of magnetic levitation driven knitting needle technology, and in particular to a communication method between an FPGA-based magnetic levitation knitting needle array system and a PC, which is mainly applicable to improving data transmission speed and reliability. Background Technology

[0002] Computerized flat knitting machines are widely used mechatronic devices in knitting machinery. The needle drive mechanism, as a crucial component, significantly impacts the knitting efficiency and fabric quality. Magnetic levitation needle drive, a novel needle drive method, solves the problems of friction, heat generation, and noise associated with traditional cam-type drives, thus greatly improving knitting efficiency. Due to the complexity, precision, and real-time nature of magnetic levitation needle control, the large amount of knitting data, massive real-time computation, and complex knitting algorithms in actual knitting processes place higher demands on processing and transmission speeds. High-speed, stable, real-time, and efficient data transmission solutions reflect the overall performance of the flat knitting machine system and represent a pressing technical challenge that needs to be addressed.

[0003] Traditional flat knitting machine needle systems mostly adopt a single-layer centralized control system framework, with the main CPU simultaneously responsible for human-computer interaction, real-time control, and data transmission. With continuous structural improvements and increasing requirements for knitting processes, the amount of data and tasks processed by the system has greatly increased. At this point, traditional flat knitting machine systems can hardly achieve real-time data transmission and parallel processing, resulting in low data transmission speed and low reliability. Summary of the Invention

[0004] The purpose of this invention is to overcome the defects and problems of low data transmission speed and low reliability in the existing technology, and to provide a communication method between an FPGA-based magnetic levitation knitting needle array system and a PC with high data transmission speed and high reliability.

[0005] To achieve the above objectives, the technical solution of this invention is: a communication method between an FPGA-based magnetic levitation knitting needle array system and a PC, the method comprising the following steps:

[0006] S1. The PC compiles the pattern data into a driving data protocol and sends the driving data protocol to the FPGA according to the serial communication protocol.

[0007] S2. The FPGA receives the first byte of data from the data frame via the serial port and compares the first byte with the set driver data frame header.

[0008] If the first byte of data is the driver data frame header, the remaining data will continue to be received into the buffer space. When the driver data frame tail is received, it indicates that a data frame transmission is over.

[0009] If the first byte of data is not the driver data frame header, then no data will be received;

[0010] S3, the FPGA parses the received data values ​​and uses CRC check to determine the integrity and correctness of the data transmission frame;

[0011] If the verification is successful, the data is retrieved from the cache and placed into the specified register, and a response data frame is sent to the PC.

[0012] If the verification fails, a response data frame is sent to the PC, and the data in the cache is cleared.

[0013] S4. The PC receives the response data frame sent by the FPGA; if the response identifier is correct, a new data frame is transmitted; if the response identifier is incorrect, the previously transmitted data frame is retransmitted.

[0014] S5, the magnetic levitation needle array system retrieves data instructions from the designated register to complete the knitting action.

[0015] In step S1, the driving data protocol includes a frame header, action identifier, needle status, electromagnet status, knitting action, CRC check, and frame tail.

[0016] The frame header occupies 1 byte and is used to determine whether data reception is required.

[0017] The action identifier occupies 2 bytes and is used to represent needle drive data and motor motion data;

[0018] The needle status occupies 2N bytes and is used to represent the position information, needle number information, and action information of N needles.

[0019] The electromagnet status occupies N bytes and is used to represent the magnitude and direction of the current flowing through the N electromagnets on the machine head;

[0020] The knitting action occupies 2 bytes and is used to indicate that the Nth needle is performing a floating yarn action, a gathering action, or a forming action;

[0021] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0022] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission.

[0023] In the knitting action, OxN01 represents the floating yarn action of the Nth needle, OxN02 represents the gathering action of the Nth needle, and OxN03 represents the forming action of the Nth needle.

[0024] In step S3, the response data frame consists of a frame header, a response identifier, a CRC checksum, and a frame trailer;

[0025] The frame header occupies 1 byte and is used to determine whether data reception is required.

[0026] The response identifier occupies 1 byte and is used to indicate the data reception status;

[0027] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0028] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission.

[0029] In the response identifier, 0x00 indicates data reception failure, and 0x01 indicates data reception success.

[0030] In step S3, the cache space uses a FIFO circular queue to perform circular caching of data.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0032] 1. In the communication method between the FPGA-based magnetic levitation knitting needle array system and a PC, this invention employs serial communication between the FPGA and the PC, leveraging the high parallelism of the FPGA to improve transmission speed. Simultaneously, a driving data protocol is defined specifically for the unique structure of the magnetic levitation knitting needle. This protocol offers high flexibility and adaptability, and different data contents are set for commonly used FPGA state control machines, facilitating FPGA state machine transitions and improving overall system performance. Therefore, this invention improves both the speed and reliability of data transmission.

[0033] 2. In the communication method between the FPGA-based magnetic levitation needle array system and a PC, serial communication is used to achieve long-distance communication, reducing communication costs. By setting frame header data to determine whether it is transmission data, the system's handling of interference and instability is reduced, ensuring the rational use of FPGA internal resources and preventing buffer space from being occupied by error or interference data, thus ensuring timely reception of correct transmission data. To improve the accuracy of data received by the FPGA, CRC check is added to the driver data protocol. CRC check can correct errors in the information transmission process at a high rate, completing data verification calculations and error correction in a very short time. Automatic retransmission of data packets significantly improves the computer's communication speed, providing assurance for communication efficiency and security. Therefore, this invention features low communication cost, high communication efficiency, and high communication reliability.

[0034] 3. In the communication method between the FPGA-based magnetic levitation knitting needle array system and a PC, the driving data protocol can be flexibly modified based on the data from the knitting needles and electromagnets. Adding a knitting action component to the driving data protocol increases the overall operating speed of the FPGA. Combined with state transitions, it saves the data parsing process, allowing direct extraction of corresponding data and reducing the overall system computation. Therefore, this invention has a wide range of applications, high operating efficiency, and low computational load.

[0035] 4. In the communication method between the FPGA-based magnetic levitation needle array system and the PC, the buffer space adopts a FIFO circular queue for circular data buffering, realizing high-speed and stable transmission of data driven by the magnetic levitation needle array. Therefore, this invention improves the data transmission rate and stability. Attached Figure Description

[0036] Figure 1 This is a flowchart of a communication method between an FPGA-based magnetic levitation needle array system and a PC. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] See Figure 1 A communication method between an FPGA-based magnetic levitation knitting needle array system and a PC, the method comprising the following steps:

[0039] S1. The PC compiles the pattern data into a driving data protocol and sends the driving data protocol to the FPGA according to the serial communication protocol.

[0040] S2. The FPGA receives the first byte of data from the data frame via the serial port and compares the first byte with the set driver data frame header.

[0041] If the first byte of data is the driver data frame header, the remaining data will continue to be received into the buffer space. When the driver data frame tail is received, it indicates that a data frame transmission is over.

[0042] If the first byte of data is not the driver data frame header, then no data will be received;

[0043] S3, the FPGA parses the received data values ​​and uses CRC check to determine the integrity and correctness of the data transmission frame;

[0044] If the verification is successful, the data is retrieved from the cache and placed into the specified register, and a response data frame is sent to the PC.

[0045] If the verification fails, a response data frame is sent to the PC, and the data in the cache is cleared.

[0046] S4. The PC receives the response data frame sent by the FPGA; if the response identifier is correct, a new data frame is transmitted; if the response identifier is incorrect, the previously transmitted data frame is retransmitted.

[0047] S5, the magnetic levitation needle array system retrieves data instructions from the designated register to complete the knitting action.

[0048] In step S1, the driving data protocol includes a frame header, action identifier, needle status, electromagnet status, knitting action, CRC check, and frame tail.

[0049] The frame header occupies 1 byte and is used to determine whether data reception is required.

[0050] The action identifier occupies 2 bytes and is used to represent needle drive data and motor motion data;

[0051] The needle status occupies 2N bytes and is used to represent the position information, needle number information, and action information of N needles.

[0052] The electromagnet status occupies N bytes and is used to represent the magnitude and direction of the current flowing through the N electromagnets on the machine head;

[0053] The knitting action occupies 2 bytes and is used to indicate that the Nth needle is performing a floating yarn action, a gathering action, or a forming action;

[0054] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0055] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission.

[0056] In the knitting action, OxN01 represents the floating yarn action of the Nth needle, OxN02 represents the gathering action of the Nth needle, and OxN03 represents the forming action of the Nth needle.

[0057] In step S3, the response data frame consists of a frame header, a response identifier, a CRC checksum, and a frame trailer;

[0058] The frame header occupies 1 byte and is used to determine whether data reception is required.

[0059] The response identifier occupies 1 byte and is used to indicate the data reception status;

[0060] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0061] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission.

[0062] In the response identifier, 0x00 indicates data reception failure, and 0x01 indicates data reception success.

[0063] In step S3, the cache space uses a FIFO circular queue to perform circular caching of data.

[0064] The principle of this invention is explained as follows:

[0065] FPGA devices are a type of semi-custom circuit within the category of application-specific integrated circuits (ASICs). They are programmable logic arrays that effectively address the issue of limited gate counts in traditional devices. The basic structure of an FPGA includes programmable input / output units, configurable logic blocks, a digital clock management module, embedded block RAM, routing resources, embedded dedicated hard cores, and low-level embedded functional units.

[0066] This design uses a two-layer distributed control system structure of PC and FPGA as the framework, defines the driving data for needle control by combining a magnetic levitation needle array model, and uses a FIFO circular queue for circular buffering of data, providing a serial communication method between the FPGA-based magnetic levitation needle array and the host.

[0067] The FIFO circular queue structure consists of several main parts: a write pointer (Wr_pointer), a read pointer (Rd_pointer), a data area (Data), and a data empty area (Empty). The positions of the data area and the empty area are determined by comparing the addresses of the write pointer and the read pointer. **Write Pointer (Wr_pointer):** This pointer points to the first memory space. Since data is sent directly to the output port, the write pointer starts counting from 0. It is updated and incremented by 1 each time data is received, until it reaches the end of the buffer. If all data in the data area has been read, it automatically returns to the head of the buffer for the next loop, repeating this process. **Read Pointer (Rd_pointer):** This pointer reads data. When the read port is enabled, data is read sequentially starting from 0. Similar to the write pointer, its pointer address is updated each time data is read. After all data has been read, it returns to the head of the buffer to prepare for the next read operation. **Data Area (Data):** The area between the write pointer and the read pointer, already filled with data, storing the buffered data that has just entered the queue. Empty area: This is an empty area where data has been retrieved by the read pointer but not yet written by the write pointer. The empty and data areas alternate during data transmission for reading and writing. Internally, the processor doesn't use a true circular memory structure; the circular queue is actually implemented using the linear space of an array. When data reaches the end of the array, it loops back to position 0 like a ring before resuming data transmission, thus realizing the circular queue. A circular FIFO can be divided into four modules: a storage module, a pointer generation module, a pointer comparison module, and a flag generation module. Dual-port RAM serves as the foundation of the FIFO, using two completely independent read and write ports for transmission and reception. The entire FIFO uses the read and write pointer modules to generate their respective address pointers, which are then entered into the comparison module to determine whether the FIFO is empty or full. Finally, the flag generation module provides the current internal storage state of the FIFO, and the FIFO uses this state to implement the circular data reception.

[0068] Example:

[0069] See Figure 1 A communication method between an FPGA-based magnetic levitation knitting needle array system and a PC, the method comprising the following steps:

[0070] S1. The PC compiles the pattern data into a driving data protocol and sends the driving data protocol to the FPGA according to the serial communication protocol.

[0071] The drive data protocol includes a frame header, action identifier, needle status, electromagnet status, weaving action, CRC checksum, and frame tail.

[0072] Table 1 Driver Data Protocol

[0073] content Number of bytes occupied illustrate Frame header 1 0x3F Action identifier 2 0x5100 knitting needle state 16 0000H~FFFFH Electromagnet state 8 0000H~FFFFH knitting movements 2 00H~FFH CRC check 4 0000H~FFFFH Frame end 1 0x3E

[0074] The frame header occupies 1 byte and is used to determine whether data reception is required. If it is 0x3F, it meets the requirements for a driver data frame header, and the FPGA will receive data; otherwise, it will not receive data.

[0075] The action identifier occupies 2 bytes and is used to represent needle drive data and motor motion data; 0x5100 represents needle drive data and 0x4A01 represents motor motion data.

[0076] The needle status occupies 16 bytes and is used to represent the position information, needle number information, and action information of 8 needles. The information of 8 needles is recorded at a time, and the information of 1 needle occupies 2 bytes. For example, 0x011F indicates that the 31st needle of the front needle plate is moving, and 0x102F indicates that the 47th needle of the rear needle plate is not moving.

[0077] The electromagnet status occupies 8 bytes, used to indicate the magnitude and direction of the current flowing through the 8 electromagnets on the machine head; each electromagnet occupies 1 byte, such as 0xD2 indicating that the 5th electromagnet is flowing with a 2A positive current, and 0x52 indicating that the 5th electromagnet is flowing with a 2A reverse current.

[0078] The knitting action occupies 2 bytes and is used to indicate whether the Nth needle is performing a floating yarn action, a gathering knitting action, or a knitting loop action; for example, 0x0F01 indicates that the 16th needle is performing a floating yarn action.

[0079] Table 2 Weaving Movements

[0080]

[0081] In the knitting action, OxN01 represents the floating yarn action of the Nth needle, OxN02 represents the gathering action of the Nth needle, and OxN03 represents the forming action of the Nth needle.

[0082] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0083] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission;

[0084] S2. The FPGA receives the first byte of data from the data frame via the serial port and compares the first byte with the set driver data frame header 0x3F.

[0085] If the first byte of data is the driver data frame header, the remaining data will continue to be received into the buffer space. When the driver data frame tail 0x3E is received, it indicates that a data frame transmission is over.

[0086] If the first byte of data is not the driver data frame header, then no data will be received;

[0087] S3, the FPGA parses the received data values ​​and uses CRC check to determine the integrity and correctness of the data transmission frame;

[0088] If the verification is successful, the data is retrieved from the cache and placed into the specified register, and a response data frame is sent to the PC.

[0089] If the verification fails, a response data frame is sent to the PC, and the data in the cache is cleared.

[0090] The response data frame consists of a frame header, a response identifier, a CRC checksum, and a frame trailer;

[0091] Table 3 Response Data Frames

[0092] content Number of bytes occupied illustrate Frame header 1 0x3E Response identifier 1 0x00~0x01 CRC check 4 0000H~FFFFH Frame end 1 0x3F

[0093] The frame header occupies 1 byte and is used to determine whether data reception is required.

[0094] The response identifier occupies 1 byte and is used to indicate the data reception status;

[0095] In the response identifier, 0x00 indicates data reception failure, and 0x01 indicates data reception success;

[0096] Table 4 Response Identifiers

[0097]

[0098] The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission.

[0099] The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission;

[0100] The cache space uses a FIFO circular queue for circular data caching;

[0101] S4. The PC receives the response data frame sent by the FPGA; if the response identifier is correct, a new data frame is transmitted; if the response identifier is incorrect, the previously transmitted data frame is retransmitted.

[0102] S5. The magnetic levitation needle array system retrieves data instructions from the designated register. The needle array moves under the drive of the machine head, waiting for the arrival of the next new instruction to change the current action and repeat the process.

Claims

1. A communication method between an FPGA-based magnetic levitation needle array system and a PC, characterized in that, The method includes the following steps: S1. The PC compiles the pattern data into a driving data protocol and sends the driving data protocol to the FPGA according to the serial communication protocol. The drive data protocol includes a frame header, action identifier, needle status, electromagnet status, weaving action, CRC check, and frame tail. The frame header occupies 1 byte and is used to determine whether data reception is required. The action identifier occupies 2 bytes and is used to represent needle drive data and motor motion data; The needle status occupies 2N bytes and is used to represent the position information, needle number information, and action information of N needles. The electromagnet status occupies N bytes and is used to represent the magnitude and direction of the current flowing through the N electromagnets on the machine head; The knitting action occupies 2 bytes and is used to indicate that the Nth needle is performing a floating yarn action, a gathering action, or a forming action; The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission. The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission; S2. The FPGA receives the first byte of data from the data frame via the serial port and compares the first byte with the set driver data frame header. If the first byte of data is the driver data frame header, the remaining data will continue to be received into the buffer space. When the driver data frame tail is received, it indicates that a data frame transmission is over. If the first byte of data is not the driver data frame header, then no data will be received; S3, the FPGA parses the received data values ​​and uses CRC check to determine the integrity and correctness of the data transmission frame; If the verification is successful, the data is retrieved from the cache and placed into the specified register, and a response data frame is sent to the PC. If the verification fails, a response data frame is sent to the PC, and the data in the cache is cleared. S4. The PC receives the response data frame sent by the FPGA; if the response identifier is correct, a new data frame is transmitted; if the response identifier is incorrect, the previously transmitted data frame is retransmitted. S5, the magnetic levitation needle array system retrieves data instructions from the designated register to complete the knitting action.

2. The communication method between an FPGA-based magnetic levitation needle array system and a PC according to claim 1, characterized in that: In the knitting action, OxN01 represents the floating yarn action of the Nth needle, OxN02 represents the gathering action of the Nth needle, and OxN03 represents the forming action of the Nth needle.

3. The communication method between an FPGA-based magnetic levitation needle array system and a PC according to claim 1, characterized in that: In step S3, the response data frame consists of a frame header, a response identifier, a CRC checksum, and a frame trailer; The frame header occupies 1 byte and is used to determine whether data reception is required. The response identifier occupies 1 byte and is used to indicate the data reception status; The CRC check occupies 4 bytes and is used to verify whether data loss or error has occurred during data transmission. The frame tail occupies 1 byte and is used to indicate the completion of a complete data frame transmission.

4. The communication method between an FPGA-based magnetic levitation needle array system and a PC according to claim 3, characterized in that: In the response identifier, 0x00 indicates data reception failure, and 0x01 indicates data reception success.

5. The communication method between an FPGA-based magnetic levitation needle array system and a PC according to claim 1, characterized in that: In step S3, the cache space uses a FIFO circular queue to perform circular caching of data.

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