Aging prediction modeling method under open-state arbitrary stress condition suitable for dram peripheral transistor

Abstract

This invention discloses an aging prediction modeling method applicable to DRAM peripheral transistors under arbitrary stress conditions in the open state. Based on the dominant stress regions of different types of defects, this invention extracts data within these regions to determine the corresponding parameters of defects Nit1, Not-e, Not-h, and Nit2. By integrating all obtained parameters and inputting them under arbitrary stress conditions, the aging amount of the device at any time under those conditions can be obtained. This invention allows for overall calibration and parameter fine-tuning with all experimental data, achieving optimal consistency between the model and experimental data. This invention can predict the long-term aging of devices under different stress conditions in the open state (different combinations of Vg / Vd). It has advantages such as high reliability, good prediction accuracy, and strong practicality.

Description

Technical Field

[0001] This invention relates to the field of DRAM peripheral device technology, and more specifically to an aging prediction modeling method applicable to DRAM peripheral transistors under arbitrary stress conditions in the open state. Background Technology

[0002] As process nodes continue to advance, device leakage current issues become increasingly severe. In the current sub-20nm DRAM process, major DRAM manufacturers are introducing high-k materials into the transistor gate oxide layer to suppress leakage current. However, this introduces numerous gate oxide defects and a large number of Si-H bonds during annealing, exacerbating the hot carrier degradation (HCD) phenomenon. Furthermore, although the operating voltage of DRAM is continuously decreasing, a high voltage such as 3V is required internally to achieve greater drive capability when the transistor is turned on, necessitating the use of thick oxide devices to achieve this function. In recent years, international DRAM giants Samsung, SK Hynix, and Micron have reported severe HCD phenomena on thick oxide devices in sub-20nm processes. Following closely behind, domestic DRAM manufacturer Changxin also discovered severe HCD phenomena in thick oxide PMOS devices. Therefore, it is necessary to predict the long-term aging of HCD phenomena.

[0003] Current aging models for sub-20nm DRAM processes include the defect-based physical model proposed by SK Hynix in 2020 (Seung-Geun Jung published in EDL) and the mathematical model used by Samsung in 2021 that only considers aging time (D. Son published in IRPS). However, the former only stays at the physical mechanism level and has not established a corresponding mathematical model to predict device aging; while the latter only considers the effect of aging time under a specific stress voltage (Vg = 0.5Vd) and cannot be extended to the entire stress voltage region. Although there are complete aging models that can be used in logic devices, the aging laws are different due to the differences in defect types between DRAM fabricated by gate-first process and logic devices fabricated by traditional gate-back process, making it impossible to directly apply the models proposed for traditional logic devices to DRAM devices.

[0004] In summary, existing technical solutions cannot achieve good prediction results on PMOS peripheral devices of DRAM. A complete HCD model is needed to accurately predict the long-term degradation caused by HCD of DRAM peripheral devices under arbitrary turn-on voltage. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes an aging prediction modeling method applicable to DRAM peripheral transistors under arbitrary stress conditions in the open state.

[0006] The technical solution provided by this invention is as follows:

[0007] An aging prediction modeling method applicable to DRAM peripheral transistors under arbitrary stress conditions in the open state, comprising the following steps:

[0008] 1) Based on all possible defect types in the gate oxide layer of the DRAM peripheral transistor and the magnitude of the influence of various defects on the device when different voltages are applied to the device, all possible operating voltage regions of the DRAM peripheral transistor are divided into stress regions dominated by different defect types, and physical models of device threshold voltage degradation caused by different defects are established.

[0009] 2) Select several groups of different V values ​​in the stress regions dominated by the different defect types mentioned above. D / V G Data under high electric field stress conditions, including leakage voltage |V D |or gate voltage|V G |Greater than the typical operating voltage of 3V, by achieving a match between the model prediction effect and the measured data, the model fitting parameter values ​​representing the corresponding defects in this region are determined, and the threshold voltage offset caused by different defect types under any voltage and any operating time is obtained.

[0010] 3) Integrate the calculation formulas characterizing the magnitude of threshold voltage degradation caused by all defect types to obtain a complete aging model, under low electric field stress conditions, i.e., leakage voltage |V D |and gate voltage|V G All values ​​are less than or equal to the typical operating voltage of 3V, verifying the good agreement between the device threshold voltage degradation calculated by the model and the actual experimental data.

[0011] 4) Using the aging model obtained in step 3), input V under arbitrary open-state conditions. D / V G Stress and aging time of arbitrary length, where the gate voltage |V| under open-state conditions G If the voltage is greater than the threshold voltage of 0.85V, the degradation of the device under that condition can be predicted.

[0012] Furthermore, the high electric field regions of the DRAM peripheral transistors are divided into: Region 1, which is dominated by interface state defects Nit1; Region 2, which is dominated by oxide electron traps Not-e; Region 3, which is dominated by oxide hole traps Not-h; and Region 4, which is dominated by interface state defects Nit2.

[0013] Select several different V groups in region1 D / V GSubstituting the data under stress conditions into formula (1) for defect Nit1, the values ​​of the corresponding fitting parameters A1, B1, and C1 are determined through experimental data:

[0014]

[0015] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stress, n1 is the defect N it1 The time constant, ΔV th_Nit1 Represented by N it1 The resulting threshold voltage offset;

[0016] It was determined that Not-e would be modeled using a stretching exponential model, and several different V values ​​were selected in region2. D / V G Substituting the data under stress conditions into the corresponding formulas (2), (3), and (4) for the defect Not-e, the values ​​of the corresponding fitting parameters E, p, and q are determined through experimental data;

[0017] ΔV th_Not-e =D{1-exp[-(t / τ)]} β ]} (2)

[0018] In equation (2), D represents the total density of the Not-e defect, τ represents the time constant of the defect, β reflects the distribution width of the defect type, t is the time of stress application, and ΔV th_Not-e Representing the threshold voltage offset caused by Not-e, D and τ respectively satisfy the following equations:

[0019] D = E1 exp(p1V G )exp(q1V D (3)

[0020] τ=E2 exp(p2V G )exp(q2V D (4)

[0021] V G and V D Represents the applied gate and drain stress;

[0022] Select several different V groups in region3 D / V G Substituting the data under stress conditions into formula (5) for defect Not-h, the values ​​of the corresponding fitting parameters A2, B2, and C2 are determined through experimental data:

[0023]

[0024] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stress, n2 is the time constant of defect Not-h, and ΔV th_Not-h This represents the threshold voltage offset generated by Not-h;

[0025] Select several different V groups in region4 D / V G Substituting the data under stress conditions into formula (6) for defect Nit2, the values ​​of the corresponding fitting parameters A3, B3, and C3 are determined through experimental data:

[0026]

[0027] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stress, n3 is the time constant of defect Nit2, and ΔV th_Nit2 This represents the threshold voltage offset generated by Nit2;

[0028] Using the values ​​of all the above fitting parameters, and inputting any VG / VD stress voltage under the on-state condition, the Vth degradation of the device after any aging time is predicted according to formula (7):

[0029] ΔV th =ΔV th_Nit1 +ΔV th_Not-h +ΔV th_Not-e +ΔV th_Nit2 (7)

[0030] Furthermore, considering that region2 has a small number of defects Nit1 influences, the Nit1 model can be added to region2 to determine the fitting parameters (E, p, q) of Not-e: Therefore, the values ​​of fitting parameters A1, B1, and C1 are substituted into formula (1) and then added to formula (2).

[0031] Furthermore, considering that region 3 has a small number of defects Nit1 influences, the Nit1 model can be added to region 3 to determine the fitting parameters (A2, B2, C2) of Not-h: Therefore, the values ​​of fitting parameters A1, B1, and C1 are substituted into formula (1) and then added to formula (5).

[0032] Furthermore, considering the influence of Not-h in region4, the Not-h model can be added to region4 to determine the corresponding parameters (A3, B3, C3) of Nit2: Therefore, the values ​​of the fitting parameters A2, B2, and C2 are substituted into formula (5) and then added to formula (6).

[0033] The beneficial effects of this invention are: This invention can guarantee good prediction accuracy while possessing advantages such as strong operability, ease of implementation, and applicability. Once a device under a new process condition is obtained, it is only necessary to extract parameters from multiple sets of measured data based on the established model to achieve prediction of long-term device aging under arbitrary stress conditions. Attached Figure Description

[0034] Figure 1 This is a schematic diagram illustrating various types of defects during the aging process of the device of the present invention;

[0035] Figure 2 This is a schematic diagram illustrating the specific implementation process of the present invention;

[0036] Figure 3 This is a comparison chart of the model fitting effect of the present invention with the measured data, where a) in |V G |<=|V D The result under the condition |; b) under |V G |>=|V D The result under the condition of |

[0037] Figure 4 This is a comparison chart of the prediction results of the model of the present invention and the measured data, where a) in |V G |<=|V D The result under the condition |; b) under |V G |>=|V D The result under the condition |. Detailed Implementation

[0038] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments.

[0039] The model of this invention is completed in a high electric field region; then, based on the extracted model parameters, predictions are made under low electric field conditions, and the accuracy of the model can be verified by comparing with experimental results.

[0040] like Figure 1 As shown, this invention divides the stress regions dominated by four types of defects to determine the approximate range of model parameters for each defect. This avoids the situation where too many parameters result in poor fitting. The specific regions are divided as follows:

[0041] 1) Region1 (0.5*|VD|<|VG|<|VD|): Interface state defect Nit1 dominates device aging;

[0042] 2) Region2(|VG|<0.5*|VD|): Oxide layer electron trap Not-e dominates device aging;

[0043] 3) Region3(|VG|>|VD|): Oxide hole traps (Not-h) dominate device aging;

[0044] 4) Region4 (|VD|≈0V): Interface state defect Nit2 dominates device aging.

[0045] Then, complete the overall parameter verification and confirmation. The specific implementation process is as follows: Figure 2 As shown, it includes:

[0046] 1) In Figure 1 Select at least three different V groups in region 1 shown. D / V G Data under stress conditions, such as V D / V G = ①-3.6V / -3.6V ②-4.0V / -3.6V ③-3.6V / -3.2V, substitute the data into the corresponding formula for defect Nit1 to determine the values ​​of the corresponding fitting parameters (A1, B1, C1):

[0047]

[0048] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stress, n1 is the defect N it1 The time constant, A1, B1, and C1 are fitting parameters that need to be extracted from experimental data, and ΔV th_Nit1 Represented by N it1 The resulting threshold voltage offset (in millivolts). After data fitting, the results are A1 = 1.16e5, B1 = -0.88, and C1 = 49.

[0049] 2) In Figure 1 As shown in region 2, at least three different V groups are selected. D / V G Data under stress conditions, such as V D / V G = ①-3.0V / -1.2V ②-3.6V / -1.2V ③-3.6V / -1.8V. Because a small amount of defect Nit1 influences region 2, the Nit1 model can be added to region 2 to determine the fitting parameters (E, p, q) for Not-e:

[0050]

[0051] In the formula, D represents the total density of Not-e defects, τ represents the time constant of Not-e defects, β represents the distribution width of Not-e defects (an empirical constant, 0.34 is used here), t is the time of stress application, and ΔV th_Not-e Representing the threshold voltage offset (in millivolts) caused by Not-e, D and τ respectively satisfy the following equations:

[0052] D = E1 exp(p1V G )exp(q1V D )

[0053] τ=E2 exp(p2V G )exp(q2V D )

[0054] Parameters E, p, and q are all fitting parameters that need to be extracted from the measured data, and V G and V D These represent the applied gate and drain stresses. After data fitting, the results are E1 = -19.6, p1 = 3.4, q1 = -1.83, E2 = 8.55e9, p2 = 15.7, and q2 = 0.17.

[0055] 3) In Figure 1 As shown in region 3, at least three different V groups are selected. D / V G Data under stress conditions, such as V D / V G = ①-2.4V / -3.6V ②-1.2V / -3.6V ③-2.4V / -4.0V. Because region 3 also has a small amount of Nit1 influence, the Nit1 model can also be added to region 3 to determine the fitting parameters (A2, B2, C2) for Not-h:

[0056]

[0057] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stresses, n2 is the time constant of the defect Not-h, A2, B2, and C2 are fitting parameters that need to be extracted from experimental data, and ΔV th_Not-h This represents the threshold voltage offset (in millivolts) generated by Not-h. After data fitting, the results are A2 = 1.1, B2 = -0.6, and C2 = 2.44.

[0058] 4) In Figure 1 The region 4 shown also selects at least three different V groups. D / V GData under stress conditions, such as V D / V G = ①0V / -3.6V ②0V / -4.0V ③-0.6V / -4.0V. Because of the Not-h effect in region 4, the Not-h model needs to be added to this region to determine the corresponding parameters (A3, B3, C3):

[0059]

[0060] Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stresses, n3 is the time constant of defect Nit2, A3, B3, and C3 are fitting parameters that need to be extracted from experimental data, and ΔV th_Nit2 This represents the threshold voltage offset generated by Nit2. After data fitting, the results are A3 = 0.16, B3 = -0.7, and C3 = 2.95.

[0061] After the above steps, the values ​​of all parameters have been obtained. Finally, the 12 sets of all measured data are used to perform overall global fitting parameter calibration with the mathematical models of the four types of defects to obtain the final complete model:

[0062] ΔV th =ΔV th_Nit1 +ΔV th_Not-h +ΔV th_Not-e +ΔV th_Nit2

[0063] ΔV th_Nit1 =1.16E5exp(-0.88V) G )exp(49 / V D )t 0.5

[0064] ΔV th_Not-h =1.1exp(-0.6V) G )exp(2.44 / V D )t 0.2

[0065] ΔV th_Not-e =D{1-exp[-(t / τ)]} 0.34 ]}

[0066] D = -19.6exp(3.4V) G )exp(-1.83V D )

[0067] τ=8.55E9exp(15.7V G )exp(0.17VD )

[0068] ΔV th_Nit2 =0.16exp(-0.7V) G )exp(2.95V D )t 0.2

[0069] Based on the aging model established above, by simply inputting any VG / VD stress voltage under the on-state condition, the Vth degradation of the device after any aging time can be calculated and predicted.

[0070] This invention is based on an aging prediction model for devices under arbitrary stress. Its implementation starts from the underlying physics (the increase of different types of defects in the stress). The prediction results achieved by the established model show good agreement with measured data (see [link]). Figure 3 and Figure 4 The overall solution is highly reliable.

[0071] like Figure 3 The parameter extraction process under high field conditions shown in Figure (a) demonstrates that, regardless of the three sets of stress results (V) in region 1,... D / V G = ①-3.8V / -3.0V ②-3.6V / -3.0V ③-3.4V / -3.0V), and the three sets of results for region 2 (V) D / V G =①-3.8V / -1.2V ②-3.6V / -1.2V ③-3.4V / -1.2V), or the three sets of results (V) in region 3 of Figure (b). D / V G = ①-3.6V / -3.6V ②-3.4V / -3.6V ③-3.0V / -3.6V), and the two sets of results from region 4 (V) D / V G =①0V / -3.6V ②-0.4V / -3.6V), the measured data (hollow symbol) and the values ​​calculated by the model through parameter fitting (solid line) have excellent consistency.

[0072] Based on the parameters obtained from the above fitting, a device aging model has been established, such as... Figure 4 Device aging prediction is achieved under low electric field conditions. Whether it's region 1 (V) in Figure (a)... D / V G =①-3.2V / -3.0V②-3.0V / -3.0V) and region2(V D / V G=①-3.2V / -1.2V ②-3.0V / -1.2V) The prediction result is still as shown in Figure (b) at the boundary between region 3 and region 4 (V D / V G The predicted results (solid lines) for (①-2.8V / -3.6V ②-2.0V / -3.6V ③-1.2V / -3.6V) all show good agreement with the experimental results (hollow symbols), proving the reliability of this technical solution and the accuracy of the model.

[0073] This invention proposes an aging model for peripheral thick oxide PMOS devices fabricated using sub-20nm DRAM processes. This model is based on different types of defects present during device stress, enabling prediction of long-term device aging under various stress conditions (different combinations of Vg / Vd) in the open state. It offers advantages such as high reliability, good prediction accuracy, and strong practicality.

[0074] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A method for predicting and modeling aging under arbitrary stress conditions in the open state of DRAM peripheral transistors, comprising the following steps: 1) Based on all the defect types present in the gate oxide layer of the DRAM peripheral transistor and the magnitude of the influence of various defects on the device when different voltages are applied to the device, all the working voltage regions of the DRAM peripheral transistor are divided into stress regions dominated by different defect types, and physical models of the device threshold voltage degradation caused by different defects are established. 2) Select several groups of different V values ​​in the stress regions dominated by the different defect types mentioned above. D / V G Data under high electric field stress conditions, including leakage voltage |V D |or gate voltage|V G |Greater than the typical operating voltage of 3V, by achieving a match between the model prediction effect and the measured data, the model fitting parameter values ​​representing the corresponding defects in this region are determined, and the threshold voltage offset caused by different defect types under any voltage and any operating time is obtained. 3) Integrate the calculation formulas characterizing the magnitude of threshold voltage degradation caused by all defect types to obtain a complete aging model, under low electric field stress conditions, i.e., leakage voltage |V D |and gate voltage|V G All values ​​are less than or equal to the typical operating voltage of 3V, verifying the good agreement between the device threshold voltage degradation calculated by the model and the actual experimental data. 4) Using the aging model obtained in step 3, input V under arbitrary open-state conditions. D / V G Stress and aging time of arbitrary length, where the gate voltage |V| under open-state conditions G If the voltage is greater than the threshold voltage of 0.85V, the degradation of the device under that condition can be predicted.

2. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 1, characterized in that, The operating voltage regions of all peripheral transistors in DRAM are divided into: Region 1, dominated by interface state defects Nit1; Region 2, dominated by oxide electron traps Not-e; Region 3, dominated by oxide hole traps Not-h; and Region 4, dominated by interface state defects Nit2.

3. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 2, characterized in that, Select several different V groups in region1 D / V G Substituting the data under stress conditions into formula (1) for defect Nit1, the values ​​of the corresponding fitting parameters A1, B1, and C1 are determined through experimental data, and the result is obtained from N it1 The resulting threshold voltage offset: （1） Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stress, n1 is the defect N it1 The time constant, ΔV th_Nit1 Represented by N it1 The resulting threshold voltage offset.

4. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 2, characterized in that, It was determined that Not-e would be modeled using a stretching exponential model, and several different V values ​​were selected in region2. D / V G Substituting the data under stress conditions into the corresponding formulas (2), (3), and (4) for the defect Not-e, the values ​​of the corresponding fitting parameters E1, E2, p, and q are determined through experimental data to obtain the threshold voltage offset generated by Not-e; （2） In equation (2), D represents the total density of the Not-e defect, τ represents the time constant of the defect, β reflects the distribution width of the defect type, t is the time of stress application, and ΔV th_Not-e Representing the threshold voltage offset caused by Not-e, D and τ respectively satisfy the following equations: （3） （4） V G and V D This represents the applied gate and drain stress.

5. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 2, characterized in that, Select several different V groups in region3 D / V G Substituting the data under stress conditions into formula (5) for defect Not-h, the values ​​of the corresponding fitting parameters A2, B2, and C2 are determined through experimental data, and the threshold voltage offset generated by Not-h is obtained: （5） Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stresses, n2 is the time constant of the defect Not-h, and ΔV th_Not-h This represents the threshold voltage offset generated by Not-h.

6. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 2, characterized in that, Select several different V groups in region4 D / V G Substituting the data under stress conditions into formula (6) for defect Nit2, the values ​​of the corresponding fitting parameters A3, B3, and C3 are determined through experimental data, and the threshold voltage offset generated by Nit2 is obtained: （6） Where t is the time for applying stress, and V G and V D Represents the applied gate and drain stresses, n3 is the time constant of defect Nit2, and ΔV th_Nit2 This represents the threshold voltage offset generated by Nit2.

7. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 4, characterized in that, Substitute the values ​​of the fitting parameters A1, B1, and C1 into formula (1) and then add them to formula (2).

8. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 5, characterized in that, Substitute the values ​​of the fitting parameters A1, B1, and C1 into formula (1) and then add them to formula (5).

9. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 6, characterized in that, Substitute the values ​​of the fitting parameters A2, B2, and C2 into formula (5) and then add them to formula (6).

10. The aging prediction modeling method for DRAM peripheral transistors under arbitrary stress conditions in the open state as described in claim 2, characterized in that, Region1, V D / V G The stress value range is 0.5 * |V D | < |V G | < |V D |;Region2 inner V D / V G The stress value range is |V G | < 0.5* |V D |;Region3 V D / V G The stress value range is |V G | > |V D | ;Region4 data V D / V G The stress value range is |V D | < 0.8V.

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