Triggering of Next State Verification in a Program Loop of a Non-Volatile Memory

Abstract

Apparatus and methods for programming memory cells and controlling bit line discharge schemes during data pattern-based programming are described. A memory controller may predict a programming data pattern based on the number of SLC pulses and the TLC data completion signal, and use these signals to adjust the time when a bit line is prohibited from discharging. Once the TLC programming operation has more than one data, the memory controller makes EQVDDSA_PROG equal to VDDSA and then discharges. In SLC programming, the memory controller enables EQVDDSA_PROG only in the first programming pulse and then disables the EQVDDSA_PROG thereafter.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention relates to the operation of memory devices. The use of semiconductor memory devices in various electronic devices has become increasingly common. For example, non-volatile semiconductor memories are used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Memory devices have always been committed to improving operation efficiency and speed. SUMMARY OF THE INVENTION

[0002] Various embodiments for operating non-volatile memories such as NAND, BICS memories, etc. are described herein.

[0003] According to one aspect of the present disclosure, a device is provided that includes a plurality of memory cells configured to store a plurality of states. The device further includes a memory controller operably connected to the plurality of memory cells to control data storage therein. The controller is configured to apply a programming control signal to a selected bit line to program a selected memory cell among the plurality of memory cells, and to apply a prohibit control signal to unselected memory cells among the plurality of memory cells to prevent programming of the unselected memory cells. The controller is further configured to deactivate an equalization signal applied to the selected bit line after applying an initial programming pulse to the selected memory cell. The controller is further configured to immediately activate the equalization signal applied to the selected bit line after reaching a threshold number of programming pulses.

[0004] According to another aspect of the present disclosure, the memory controller is configured to set a threshold of a programming pulse to a value at which at least half of the plurality of memory cells are programmed to respective final memory states.

[0005] According to another aspect of the present disclosure, the memory controller is further configured to deactivate the equalization signal to reduce power consumption and reduce prohibited memory cell interference.

[0006] According to yet another aspect of the present disclosure, the memory controller is configured to control programming of single-level cells and deactivate the equalization signal for a first programming pulse.

[0007] According to another aspect of the present disclosure, the memory controller is configured to activate bit line equalization after a second programming pulse or a later programming pulse.

[0008] According to yet another aspect of the present disclosure, the memory controller is configured to control programming of single-level cells on a partial page by selectively activating and deactivating the equalization signal for a predetermined programming pulse.

[0009] According to yet another aspect of the present disclosure, the memory controller is configured to control programming of three-level cells and deactivate the equalization signal for the first three programming pulses.

[0010] According to another aspect of the present disclosure, the memory controller is configured to enable equalization after completion of C-level programming.

[0011] According to yet another aspect of the present disclosure, the memory controller is configured to disable equalization after completion of F-level programming.

[0012] According to yet another aspect of the present disclosure, the memory controller is configured to control programming of four-level cells, disable the equalization signal for at least a first programming pulse, enable the equalization signal after completion of S7 programming, and disable the equalization signal after completion of S13 programming.

[0013] According to another aspect of the present disclosure, the memory controller is configured to control programming of four-level cells using MLS / fine programming, disable the equalization signal for at least a first programming pulse, enable the equalization signal after completion of A programming, and disable the equalization signal after completion of C programming.

[0014] Yet another aspect of the present disclosure relates to a non-volatile memory control method. The method includes the steps of: applying a select control signal to a selected bit line to address a selected memory cell among a plurality of memory cells, thereby programming the selected memory cell. The method proceeds to the step of: applying a prohibit control signal to unselected memory cells among the plurality of memory cells to prevent programming of the unselected memory cells. The method proceeds to the step of: disabling discharge of the selected bit line until an initial programming pulse is applied to the selected memory. The method proceeds to the step of: enabling discharge of the selected bit line immediately after a threshold of the programming pulse is reached.

[0015] According to another aspect of the present disclosure, the step of enabling discharge of the selected bit line includes equalizing the bit line to VDDSA before discharging the bit line.

[0016] According to yet another aspect of the present disclosure, the method further includes the step of: setting a threshold of the programming pulse to a value at which at least half of the memory cells are programmed to their respective final memory states.

[0017] According to yet another aspect of the present disclosure, the method further includes the step of: controlling programming of single-level cells, and wherein disabling discharge of the selected bit line includes disabling discharge for a first programming pulse.

[0018] According to another aspect of the present disclosure, the method further includes the step of: controlling programming of three-level cells, and wherein disabling discharge of the selected bit line includes disabling discharge of the bit line for the first three programming pulses.

[0019] According to yet another aspect of the present disclosure, enabling the discharge of the selected bit lines further includes enabling the previously disabled bit lines to discharge after C programming is completed.

[0020] According to yet another aspect of the present disclosure, the step of disabling the discharge of the selected bit lines includes disabling the previously enabled bit lines after F programming is completed.

[0021] Yet another aspect of the present disclosure relates to a non-volatile memory control method. The method includes the following steps: setting the programming pulse count to zero. The method proceeds to the following step: executing programming pulses using the bit lines at a programming level. The method proceeds to the following step: incrementing the programming pulse count. In the case where the programming pulse count is below a first threshold, the method proceeds to the following: disabling the discharge of the bit lines between programming pulses, and then executing subsequent programming pulses by returning to executing programming pulses using the bit lines at a programming level. In the case where the programming pulse count is at or above the first threshold, the method proceeds to the following steps: enabling the discharge of the bit lines between programming pulses, and then returning to executing programming pulses using the bit lines at a programming level and incrementing the programming pulse count. In the case where the programming pulse count is above a second threshold, the method proceeds to the following: disabling the discharge of the bit lines between programming pulses.

[0022] According to another aspect of the present disclosure, the step of executing programming pulses includes executing programming pulses for a QLC memory, setting the first threshold at an S7 programming pulse level, and setting the second threshold at an S13 programming pulse level. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following includes a more specific description with reference to specific embodiments shown in the accompanying drawings. It should be understood that these drawings only depict certain embodiments of the present disclosure and should not be considered as limiting its scope. By using the drawings, the present disclosure is described and explained with additional features and details. In the drawings:

[0024] Figure 1 An embodiment of a memory cell array including bit lines and word lines according to an example embodiment is shown;

[0025] Figure 2 A diagram showing a three-dimensional (3D) memory in a NAND configuration according to an example embodiment is shown;

[0026] Figure 3 A schematic block diagram showing an embodiment illustrating a 3D vertical memory structure according to an example embodiment is shown;

[0027] Figure 4 A diagram showing a top view of a 3D memory block according to an example embodiment is shown;

[0028] Figure 5Shows an array of sense amplifier groups for a 3D memory block according to an example embodiment; Figure 4 for

[0029] Figure 6 Shows a schematic block diagram illustrating an embodiment of a memory system according to an example embodiment;

[0030] Figure 7 Shows a schematic block diagram of a non - volatile memory device for memory cell subgroup identification and selection;

[0031] Figure 8 Shows a schematic diagram of a memory according to an example embodiment;

[0032] Figure 9 Shows a schematic diagram of a memory according to an example embodiment;

[0033] Figure 10 Shows a memory process according to an example embodiment;

[0034] Figure 11 Shows a memory process according to an example embodiment;

[0035] Figure 12 Shows a memory process according to an example embodiment;

[0036] Figure 13 Shows a memory process according to an example embodiment;

[0037] Figure 14 Shows a memory process according to an example embodiment;

[0038] Figure 15 Shows a simplified timing diagram according to an example embodiment;

[0039] Figure 16 Shows a threshold voltage distribution for memory cells;

[0040] Figure 17 Shows a table depicting an example of the assignment of data values to data states;

[0041] Figure 18 Is a flowchart depicting an embodiment of a process for programming;

[0042] Figure 19 Is a flowchart depicting an embodiment of a process for programming data into memory cells connected to a common word line; and

[0043] Figure 20 Depicts word line voltages during programming and verification operations; and Detailed Description

[0044] The present invention describes systems and methods for controlling programming operations of a non-volatile memory to adjust a bit line (BL) discharge scheme based at least in part on data patterns programmed into associated memory cells. In an example embodiment, a memory controller circuit system may predict a programming data pattern based on the number of programming pulses and a data done signal. The embodiments described herein will reduce the bit line discharge time by controlling the voltage equalization enable time, thereby improving the programming time (Tprog). The method of the present invention enables elimination of programming interference. In a multi-level cell (e.g., three-level cell) program operation having more than one data bit, the controller circuit system may enable and equalize an equalized data latch voltage (EQVDDSA) to VDDSA during programming on the bit line and then discharge. In an operation of a single-level cell (SLC), a programming signal enable (EQVDDSA_PROG) is used only in the first programming pulse. The programming operations for both the single-level cell and the multi-level cell each use a plurality of cycles each including a programming pulse and a verification operation.

[0045] Each memory cell may be associated with a memory state according to write data in a programming command having a plurality of cycles of programming pulses and verification. As used herein, a "memory state" is a detectable characteristic of a memory cell that can be used to represent a data value (e.g., the threshold voltage of a NAND memory cell, the resistance of a ReRAM memory cell, the magnetization state of a magnetoresistive random access memory), the data value including, for example, a binary data value having more than one binary bit. As used herein, the detectable characteristic of a memory cell that is used to represent a data value is referred to as a "programming characteristic". Based on the write data in the programming command, the memory cell will remain in an erased state or be programmed to a memory state (programmed memory state) different from the erased state.

[0046] For example, in a two bits per cell (MLC) memory device, there are four memory states including an erased state and three programmed memory states. In a three bits per cell (TLC) memory device, there are eight memory states including an erased state and seven programmed memory states. In a four bits per cell (QLC) memory device, there are sixteen memory states including an erased state and fifteen programmed memory states. Programming the cell into each of these memory states requires a plurality of cycles of programming pulses and verification phases.

[0047] When a programming command is issued, the write data is stored in a data latch associated with the memory cell. For example, in a two-bit-per-cell memory device, each memory cell is associated with two data latches (e.g., DL1, DL2) that store the two-bit write data for the memory cell. Similarly, in a three-bit-per-cell memory device, each memory cell is associated with three data latches (e.g., DL1, DL2, DL3) that store the three-bit write data for the memory cell. Similarly, in a four-bit-per-cell memory device, each memory cell is associated with four data latches (e.g., DL1, DL2, DL3, DL4) that store the four-bit write data for the memory cell. An example of a data latch can be found in U.S. Patent No. 10,535,401, which is incorporated herein by reference.

[0048] Figure 1 An embodiment of a memory depicted as a NAND flash memory cell in a memory array 126 is described. As used herein, the term "memory" refers to a semiconductor memory. Types of semiconductor memory include volatile memory and non-volatile memory. Non-volatile memory allows the storage and preservation of information even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), electrically erasable programmable read-only memory (EEPROM), ferroelectric memory (e.g., FeRAM), magnetoresistive memory (e.g., MRAM), spin-transfer torque magnetic random access memory (STT-RAM or STT-MRAM), resistive random access memory (e.g., ReRAM or RRAM), and phase change memory (e.g., PRAM or PCM). The non-volatile memory can be a BiCS memory architecture. The non-volatile memory includes one or more memory cells. A "memory cell" is an electronic device or component capable of storing electronic information. In an embodiment, the non-volatile memory utilizes a floating gate transistor or a charge trapping transistor as a memory cell. The ability to adjust the threshold voltage of the floating gate transistor or the charge trapping transistor allows the transistor to act as a non-volatile storage element or memory cell, such as a single-level cell (SLC). However, in some cases, by programming and reading multiple threshold voltages or threshold voltage ranges, more than one data bit per memory cell (e.g., multi-level cell), including MLC, TLC, QLC, etc., can be provided.

[0049] The memory array 126 may include a number of memory blocks. A "memory block" is a group of memory cells. For example, a memory block (e.g., an array of memory cells) includes memory cells arranged in word lines and bit lines. A memory "sub-block" is a subset of a memory block. For example, a sub-block is a subset of memory cells corresponding to a subset of word lines of a memory block. In an embodiment, a sub-block includes fifty word lines in a memory block, where the memory block includes more than fifty word lines. A sub-block may represent a physical sub-block, a logical sub-block, or both. A memory block includes two or more sub-blocks. In an embodiment, the memory is configured as two-dimensional (2D) NAND. In another embodiment, the memory is configured as three-dimensional (3D) NAND. In an embodiment, one or more of the components described herein (e.g., a memory die, a memory, a block, a sub-block, a memory cell, a circuit, a controller, and / or a non-volatile storage system) are implemented as one or more elements in an integrated circuit system (e.g., a transistor, a resistor, a capacitor, an inductor, and / or a conductor).

[0050] As Figure 1 Shown, illustrative memory block (or block) 100 includes a number of NAND strings (NS0 to NS11) and corresponding bit lines (e.g., BL0 to BL11 shared between blocks). Each NAND string is connected at one end to a drain select gate (SGD), and the control gate of the drain select gate is connected via a common SGD line. Each NAND string is connected at its other end to a source select gate (SGS), which in turn is connected to a common source line 154. For example, NS0 includes a source side select gate transistor 152 and a drain side select gate transistor 140. Example storage elements 142, 144, 146, 148, and 149 are in NS0 to NS4, respectively, and are connected to word line WL3. For example, WL3 may be the selected word line for programming, and the example storage elements may be the storage elements selected for programming. Other storage elements connected to WL3 may also be selected storage elements. Sixty-four word lines (e.g., WL0 to WL63) extend between the source side select gate and the drain side select gate.

[0051] In addition to NAND flash memories, other types of non-volatile memories can be used. For example, another type of memory cell available in flash EEPROM systems uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. In an embodiment, a three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (ONO) is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above a memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited region. This stored charge then changes the voltage level of a portion of the cell channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. Similar cells can be arranged in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. Another type of memory uses metal (conductive) charge storage elements in a NAND architecture.

[0052] In another method, NROM cells are used. For example, two bits are stored in each NROM cell, where the ONO dielectric layer extends across the channel between a source diffusion and a drain diffusion. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known. In an alternative embodiment, resistance levels rather than threshold voltage levels can be stored and sensed.

[0053] Figure 2 An embodiment of a 3D memory 226 in a NAND flash configuration is shown. The 3D memory 226 includes a plurality of physical layers formed monolithically above a substrate 234 such as a silicon substrate. Memory elements such as representative memory cells 246 (e.g., memory cells) are arranged in an array in the physical layers.

[0054] The representative memory cell 246 includes a charge trapping structure 244 between a word line / control gate WL4 and a conductive channel 242. Charge can be injected into or released from the charge trapping structure 244 via a bias of the conductive channel 242 relative to the word line WL4. For example, the charge trapping structure 244 can include silicon nitride and can be separated from the word line WL4 and the conductive channel 242 by a gate dielectric such as silicon oxide. The amount of charge in the charge trapping structure 244 affects the amount of current flowing through the conductive channel 242 during a read operation of the memory cell 246 and indicates one or more bit values stored in the memory cell 246.

[0055] The 3D memory 226 includes a plurality of erase blocks, including a first block (block 0) 276, a second block (block 1) 278, and a third block (block 2) 280. Each of the blocks 276, 278, 280 includes "vertical lamellae" of the physical layer, and the vertical lamellae include word line stacks, shown as a first word line WL0, a second word line WL1, a third word line WL2, a fourth word line WL3, and a fifth word line WL4. A plurality of conductive channels (having a generally vertical orientation, as Figure 2 shown) extend through the word line stacks. Each conductive channel is coupled to a storage element in each of the word lines WL0 to WL4, thereby forming a NAND string of storage elements. For clarity of illustration, Figure 2 three blocks 276, 278, 280, five word lines WL0 to WL4 in each of the blocks 276, 278, 280, and three conductive channels in each of the blocks 276, 278, 280 are shown. However, the 3D memory 226 may have more than three blocks, each block may have more than five word lines, and each block may have more than three conductive channels.

[0056] The read / write circuitry 268 (which may be part of a controller) is coupled to the conductive channels via a plurality of conductive lines, shown as a first bit line BL0, a second bit line BL1, and a third bit line BL2 at a first end of the conductive channels (e.g., the end farthest from the substrate 234) and a first source line SL0, a second source line SL1, and a third source line SL2 at a second end of the conductive channels (e.g., the end closer to or within the substrate 234). The read / write circuitry 268 is shown as being coupled to the bit lines BL0 to BL2 via a "P" control line, to the source lines SL0 to SL2 via an "M" control line, and to the word lines WL0 to WL4 via an "N" control line. Each of P, M, and N may have a positive integer value based on a specific configuration of the 3D memory 226. In the Figure 2 example shown, P = 3, M = 3, and N = 5.

[0057] In a particular embodiment, each of the bit lines BL0 to BL2 and each of the source lines SL0 to SL2 may be coupled to the same end (e.g., the first end or the second end) of different conductive channels. For example, specific bit lines BL0 to BL2 may be coupled to the first end of the conductive channel 282, and a specific source line may be coupled to the first end of the conductive channel 242. The second end of the conductive channel 282 may be coupled (e.g., electrically coupled) to the second end of the conductive channel 242. Thus, the conductive channel 282 and the conductive channel 242 may be coupled in series and may be coupled to specific bit lines BL0 to BL2 and specific source lines SL0 to SL2, each of the specific bit lines and source lines being coupled to a specific NAND string.

[0058] Although each conductive channel, such as conductive channels 242, 282, is shown as a single conductive channel, each of the conductive channels may include a plurality of conductive channels in a stacked configuration. The plurality of conductive channels in the stacked configuration may be coupled by one or more connectors. Additionally, an etch stop layer having conductive connectors coupled to physically adjacent portions of the conductive channels ( Figure 2 not shown in) may be included in the plurality of conductive channels, such as between the first physical layer group 232 and the second physical layer group 233. Additionally or alternatively, one or more sub-block gate transistors ( Figure 2 not shown in) may be coupled between the first physical layer group 232 and the second physical layer group 233.

[0059] In an embodiment, the first physical layer group 232 is an instance of a first sub-block, and the second physical layer group 233 is an instance of a second sub-block. For example, each sub-block (e.g., a “word line-based” sub-block) may include memory cells corresponding to a subset of word lines WL0 to WL4. In an alternative embodiment, each sub-block (e.g., a “string-based” sub-block) may include memory cells corresponding to a subset of strings (e.g., NAND strings) and may have, for example, common source lines SL0 to SL2 but not common bit lines BL0 to BL2, or may have common bit lines BL0 to BL2 but not common source lines SL0 to SL2.

[0060] The read / write circuitry 268 facilitates and / or performs read and write operations performed on the 3D memory 226. For example, data may be stored into storage elements coupled to word lines WL0 to WL4, and the read / write circuitry 268 may read bit values from the storage elements (e.g., memory cells) using one or more sense blocks 236. As another example, the read / write circuitry 268 may apply select signals to control lines coupled to word lines WL0 to WL4, bit lines BL0 to BL2, and source lines SL0 to SL2 such that a programming voltage (e.g., a voltage pulse or a series of voltage pulses) is applied across selected storage elements across a selected word line (e.g., the fourth word line WL4). The read / write circuitry 268 may also perform verification operations as part of a programming operation.

[0061] The read / write circuitry 268 includes one or more sense blocks 236. The sense blocks 236 are used to read or sense one or more values stored in the memory cells. In one method, one sense block 236 is provided for one group of NAND strings, each of the NAND strings being coupled to a specific bit line BL0 to BL2. For example, a sense block 236 is associated with BL0. Another sense block 236 is associated with BL1, and yet another sense block 236 is associated with BL2. Each sense block 236 may include a memory controller ( Figure 2(not shown). Each sensing block 236 also includes a sensing module for each NAND string. Alternatively, the sensing blocks 236 may be coupled to the bit lines in an interleaved manner, such as even- or odd-numbered bit lines.

[0062] During a read operation, the controller may receive a request from a host device such as a computer, a smart phone, or a laptop computer. The controller may cause the read / write circuitry 268 to read bits from a particular memory element of the 3D memory 226 by applying appropriate signals to the control lines to sense the memory elements of the selected word line. Thus, the 3D memory 226 having a plurality of conductive channels in a stacked configuration may be configured to read data from and write data to one or more memory elements.

[0063] One or more sub-blocks of the memory cells 246 in the memory cell array 246 may be coupled via a channel (e.g., a physical communication channel). In an embodiment, the channel includes bit lines BL0 to BL2 and / or source lines SL0 to SL2.

[0064] Figure 3 An embodiment of a cross-sectional view of a 3D vertical memory structure or string 329 is shown. In one embodiment, the vertical column 332 is circular and includes four layers; however, in other embodiments, more or fewer than four layers may be included, and other shapes (e.g., a "U-shaped" shape instead of an "I-shaped" shape, etc.) may be used. In one embodiment, the vertical column 332 includes an inner core layer 370 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core or inner core layer 370 is a polysilicon channel 371. Materials other than polysilicon may also be used. It should be noted that the channel 371 is connected to the bit line. Surrounding the channel 371 is a tunneling dielectric 372. In one embodiment, the tunneling dielectric 372 has an ONO structure. Surrounding the tunneling dielectric 372 is a shared charge trapping layer 373, such as silicon nitride. Other materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0065] Figure 3Depict dielectric layers DLL49, DLL50, DLL51, DLL52, and DLL53 and word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each of the word line layers includes a word line region 376 surrounded by an alumina layer 377, and the alumina layer is surrounded by a blocking oxide (SiO2) layer 378. The physical interaction between the word line layer and the vertical column 332 forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 371, a tunneling dielectric 372, a charge trapping layer 373 (e.g., shared with other memory cells), a blocking oxide layer 378, an alumina layer 377, and a word line region 376. In some embodiments, the blocking oxide layer 378 and the alumina layer 377 can be replaced with a single layer material having insulating properties or replaced with more than two different materials having insulating properties. Additionally, the materials used are not limited to silicon dioxide (SiO2) or alumina. For example, a portion of the word line layer WLL47 and the vertical column 332 includes a memory cell MC1. A portion of the word line layer WLL46 and the vertical column 332 includes a memory cell MC2. A portion of the word line layer WLL45 and the vertical column 332 includes a memory cell MC3. A portion of the word line layer WLL44 and the vertical column 332 includes a memory cell MC4. A portion of the word line layer WLL43 and the vertical column 332 includes a memory cell MC5. In other architectures, the memory cell may have a different structure; however, the memory cell will still be a storage cell.

[0066] When programming the memory cell, electrons are stored in a portion of the charge trapping layer 373 associated with the memory cell. In response to an appropriate voltage on the word line region 376, these electrons are drawn from the channel 371 through the tunneling dielectric 372 into the charge trapping layer 373. The threshold voltage (Vt) of the memory cell increases proportionally to the amount of charge stored. In one embodiment, programming is achieved via Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons returned to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erase is achieved by injecting holes into the charge trapping layer via a physical mechanism such as gate-induced drain leakage (GIDL).

[0067] In some embodiments, memory cells in the same part or location in different memory structures 329 (e.g., different memory strings 329) on different bit lines may be on the same word line. Each word line may store one data page, e.g., when each cell stores 1 data bit (SLC); each word line may store two data pages, e.g., when each cell stores 2 data bits (MLC); each word line may store three data pages, e.g., when each cell stores 3 data bits (TLC); each word line may store four data pages, e.g., when each cell stores 4 data bits (QLC); or each word line may store another number of data pages.

[0068] In the depicted embodiment, the vertical 3D memory structure 329 includes a memory structure 329 in an "I" shape. In other embodiments, the vertical 3D memory structure 329 may include a structure in a "U" shape or may have another vertical and / or stacked architecture. In some embodiments, four sets of strings 329 (e.g., four sets of 48 word lines or another predefined number of word lines) may form an erase block, while in other embodiments, fewer or more than four sets of strings 329 may form an erase block. As can be appreciated, any suitable number of memory cells may be part of a single string 329. In one embodiment, a single string 329 contains forty-eight memory cells.

[0069] Figure 4 FIG. showing a top view of a 3D memory block 400 according to one embodiment. As shown, the 3D memory block 400 may include a series of memory holes or cells (represented by circles labeled "0o" to "7o" and "0e" to "7e" in Figure 4 . Each of these memory holes may be organized into strings (labeled "string 0" to "string 3" in Figure 4 and / or further organized into IO groups (in Figure 4Marked as "O", "I1", "I2", and "I3" in the figure). Each IO group is positioned between two different types of etching features formed in the 3D memory block 400. The two different types of etching features are shallow etching features 410 (e.g., referred to as SHE) and deep etching features 420 (e.g., referred to as ST). The IO group adjacent to the deep etching feature 420 is marked as the external IO group (O); the IO group adjacent to the shallow etching feature 410 is marked as the internal 3IO group (I3); the IO group adjacent to the external IO group is marked as the internal 1IO group (I1); the IO group adjacent to the internal 3IO group (I3) is marked as the internal 2IO group (I2). It should be noted that the procedures and methods disclosed herein can be implemented in conjunction with a wide variety of types of memories, such as NAND or NOR memories, 2D memories, 3D memories, or memories employing charge-based storage technologies or resistance-based storage technologies. In one example, the illustrated memory block 400 can include 16K memory cells, and these memory cells can be further separated into smaller memory cell groups each including 1K memory cells. These smaller groups can be arranged in layers. A layer can contain memory cells associated with holes specified by the same designated circle as in Figure 4 The memory cells marked as 2o are part of the same layer. The memory cells marked as 3e are part of another layer. The memory cells marked as 2e are part of the same layer. The memory cells marked as 3o are part of another layer. As explained herein, the controller can select the single layer when the programming verification level is unlikely to find an over-programmed state or when a single layer used for the programming verification operation represents other layers. At least one intermediate level for programming verification is a multi-layer verification operation.

[0070] Some manufacturing processes for 3D memories can include thin film deposition processes, which tend to be dominant compared to the etching processes performed during manufacturing. For these types of manufacturing processes, the programming speed of the external memory holes in the external IO group (O) is typically slower than that of the internal memory holes (I3). However, some manufacturing processes for 3D memories can include etching processes that tend to be dominant during manufacturing compared to the thin film deposition processes. For these types of manufacturing processes, the programming speed of the internal memory holes (I3) is typically slower than that of the external memory holes (O). However, it should be noted that due to this variation introduced during the manufacturing process, or due to wear induced by the use of the device, the physical location of the IO groups of the memory cells within the 3D memory structure does not always determine their relative programming speed. In addition, cyclic degradation can also cause the relative programming speeds of different memory cells or memory cell groups to change over time.

[0071] Continue Figure 4, each of the memory holes (0o to 7o and 0e to 7e) can be connected to a bit line 430 (labeled as bit lines 0 to 7 in Figure 4 ). The bit lines 430 extend above the memory holes and are connected to the selected memory holes via connection points (shown as small solid ellipses in Figure 4 ), and the connection points indicate the positions where the bit lines 430 are connected to the memory holes. For ease of illustration, Figure 4 only shows eight bit lines 430 (0 to 7). However, it should be understood that in Figure 4 , other bit lines (not shown in the figure) also extend above other memory holes.

[0072] Figure 5 shows an array of sense amplifier groups 500 for a 3D memory structure 400 according to an example for Figure 4 . As can be seen in Figure 5 , the bit lines 430 shown in Figure 4 extend to the array of sense amplifier groups 500. In this way, certain memory holes of the 3D memory structure 400 can be electrically coupled to one of the bit lines 430, and each bit line can then be electrically coupled to a bit line interface 510. In an embodiment, the bit line interface 510 can additionally use scrambling, as shown by the slanted / non-vertical lines between the bit lines 430 and the bit line interface 510 in Figure 5 . Thereafter, each bit line 430 can be electrically coupled to a sense amplifier group (labeled as Tier#0 to Tier#l5 in Figure 5 ). As shown in Figure 5 , each sense amplifier group extends horizontally across the page. Thus, each "layer" includes a group of memory holes that are in electrical communication with a specific sense amplifier group via the bit lines 430. A layer can also be referred to as a "subgroup of memory cells", or simply a "subgroup". A "subgroup of memory cells" can be any subset of memory cells formed from a larger group of memory cells. In this application, a subgroup of memory cells can be referred to as a layer, a group of layers, an IO group, a partition, etc.

[0073] Figure 6Schematic block diagram illustrating embodiments of a system 600 and apparatus 610 for memory cell sub - group identification and selection. The computing device 610 includes one or more identification circuits or layer selection circuits 650 for a memory medium 622 of a non - volatile and / or volatile memory device 620. As used herein, a "layer circuit" refers to a circuit that identifies a particular layer of memory cells (e.g., 2o layer memory cells) relative to at least one other sub - group or layer of memory cells and selects the identified layer of memory cells for at least one programming operation (e.g., programming verification). The layer selection circuit is operable to select a single layer for some programming verification levels and multiple layers for other programming verification levels in the same verification operation. At least one verification is a single - layer verification, such as A or a first programming verification level. The first programming verification level may be the lowest voltage. In an example embodiment, the last programming verification level is also a single - layer verification operation. In an example embodiment, at least one intermediate programming verification is performed on multiple layers.

[0074] The layer selection circuit 650 may be part of the non - volatile and / or volatile memory element 623 (e.g., disposed on the same integrated circuit device as the non - volatile memory medium 622). In some embodiments, the memory device 620 may operate at least partially on and / or communicate with the non - volatile and / or volatile memory system 602 of the computing device 610, which may include a processor 611, volatile memory 612, and a communication interface 613. The processor 611 may include one or more central processing units, one or more general - purpose processors, one or more special - purpose processors, one or more virtual processors (e.g., the computing device 610 may be a virtual machine operating within a host), one or more processor cores, etc. The communication interface 613 may include one or more network interfaces configured to communicatively couple the computing device 610 and / or the memory controller 626 to a communication network 615, such as an Internet Protocol (IP) network, a Storage Area Network (SAN), a wireless network, a wired network, etc.

[0075] In various embodiments, the memory device 620 may be positioned in one or more different locations relative to the computing device 610. In one embodiment, the memory device 620 includes one or more non-volatile and / or volatile memory elements 623, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, memory housings, and / or other mechanical and / or electrical support structures. For example, the memory device 620 may include one or more dual in-line memory module (DIMM) cards, one or more expansion cards and / or daughter cards, memory cards, universal serial bus (USB) drives, solid state drives (SSD) or other hard drive devices, and / or may have another memory and / or storage form factor. The memory device 620 may be integrated with and / or mounted on the motherboard of the computing device 610, mounted in a port and / or slot of the computing device 610, mounted on different computing devices 610 and / or dedicated storage devices on the network 615, and communicate with the computing device 610 via an external bus (e.g., an external hard drive), etc.

[0076] In one embodiment, the memory device 620 may be positioned on the memory bus of the processor 611 (e.g., on the same memory bus as the volatile memory 612, on a different memory bus than the volatile memory 612, instead of the volatile memory 612, etc.). In another embodiment, the memory device 620 may be positioned on the peripheral bus of the computing device 610, such as a peripheral component interconnect high speed (PCI high speed or PCIe) bus, a serial advanced technology attachment (SATA) bus, a parallel advanced technology attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a fiber channel connection, a universal serial bus (USB), a PCIe advanced switch (PCIe-AS) bus, etc. In another embodiment, the memory device 620 may be positioned on the data network 615, such as an Ethernet network, an Infiniband network, SCSI RDMA on the network 615, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 615, etc.

[0077] The computing device 610 may further include a non-transitory computer-readable storage medium 614. The computer-readable storage medium 614 may include executable instructions configured to cause the computing device 610 (e.g., the processor 611) to perform one or more of the steps of the methods disclosed herein. In one embodiment, the subgroup selection circuit 650 may include hardware of non-volatile and / or volatile memory elements 623, computer-executable program code of device drivers, firmware of the memory controller 626, and / or a memory media controller for the memory elements 623, another electrical component, etc. In one embodiment, the subgroup selection circuit 650 is integrated on the memory element 623 (e.g., an on-die subgroup selection circuit 650 and / or other integrated hardware).

[0078] According to various embodiments, the memory controller 626 may manage one or more memory devices 620 and / or memory elements 623, one or more of which may include an on-die subgroup selection circuit 650. The memory device 620 may include recording, memory, and / or storage devices, such as solid-state storage devices and / or semiconductor storage devices arranged and / or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any amount of physical storage media on the memory device 620). Memory cells and / or regions may include, but are not limited to: pages, memory partitions, blocks, sectors, a set or group of physical storage locations (e.g., logical pages, logical blocks), etc.

[0079] In certain embodiments, the device driver and / or the memory controller 626 may present a logical address space 634 to the storage client 616. As used herein, the logical address space 634 refers to a logical representation of memory resources. The logical address space 634 may include a plurality of (e.g., a series of) logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including but not limited to a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an inode, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a tag, an index entry, a range, an extent, etc.

[0080] A device driver for a memory device 620 may maintain metadata 635, such as a logical-to-physical address mapping structure, to map logical addresses of a logical address space 634 to media storage locations on the memory device 620. The device driver may be configured to provide storage services to one or more storage clients 616. The storage clients 616 may include a local storage client 616 operating on a computing device 610 and / or a remote storage client 616 accessible via a network 615 and / or a network interface 613. The storage clients 616 may include, but are not limited to: an operating system, a file system, a database application, a server application, a kernel-level process, a user-level process, an application, etc.

[0081] The device driver may be communicatively coupled to one or more memory devices 620. The one or more memory devices 620 may include different types of memory devices, including but not limited to: solid-state storage devices, semiconductor storage devices, SAN storage resources, volatile memory devices, non-volatile memory devices, etc. The one or more memory devices 620 may include one or more corresponding memory media controllers 626 and memory media 622. The device driver may provide access to the one or more memory devices 620 via a conventional block I / O interface 631. Additionally, the device driver may provide access to enhanced functionality through an SCM interface 632. The metadata 635 may be used to manage and / or track data operations performed through any of the block I / O interface 631, the SCM interface 632, the cache interface 633, or other relevant interfaces.

[0082] The cache interface 633 may expose cache-specific features accessible via the device driver for the memory device 620. And, in some embodiments, the SCM interface 632 presented to the storage client 616 provides access to data transformations implemented by the one or more memory devices 620 and / or the one or more memory media controllers 626.

[0083] The device driver may present the logical address space 634 to the storage client 616 through one or more interfaces. As discussed above, the logical address space 634 may include a plurality of logical addresses, each logical address corresponding to a respective media location on the one or more memory devices 620. The device driver may maintain metadata 635 that includes any mapping between logical addresses and media locations, etc.

[0084] The device driver may further include a memory device interface 639 and / or communicate with the memory device interface 639, which is configured to transfer data, commands, and / or queries to one or more memory devices 620 via a bus 625, including but not limited to: the memory bus of the processor 611, the Peripheral Component Interconnect High-Speed (PCI High-Speed or PCIe) bus, the Serial Advanced Technology Attachment (ATA) bus, the Parallel ATA bus, the Small Computer System Interface (SCSI), FireWire, Fibre Channel, the Universal Serial Bus (USB), the PCIe Advanced Switching (PCIe-AS) bus, the network 615, InfiniBand, SCSI RDMA, etc. The memory device interface 639 may communicate with one or more memory devices 620 using Input / Output Control (IO-CTL) commands, IO-CTL command extensions, Remote Direct Memory Access, etc.

[0085] The communication interface 613 may include one or more network interfaces configured to communicatively couple the computing device 610 and / or the memory controller 626 to the network 615 and / or to one or more remote network-accessible storage clients 616. The storage client 616 may include a local storage client 616 operating on the computing device 610 and / or a remote storage client 616 accessible via the network 615 and / or the network interface 613. The memory controller 626 is part of and / or communicates with one or more memory devices 620. Although Figure 6 a single memory device 620 is depicted, the present disclosure is not limited in this regard and may be adapted to incorporate any number of memory devices 620, a combination of one or more volatile memory devices 620 and one or more non-volatile memory devices 620, etc.

[0086] The memory device 620 may include one or more elements 623 of a memory medium 622. In one embodiment, the elements 623 of the memory medium 622 include volatile memory media 622 such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, static RAM (SRAM), thyristor RAM (T-RAM), zero capacitor RAM (Z-RAM), etc. In certain embodiments, the elements 623 of the memory medium 622 include non-volatile memory media 622 such as ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional universal memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano-RAM or NRAM), nanocrystal wire-based memory, silicon-oxide-based sub-10-nanometer process memory, graphene memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, programmable metallization cell (PMC) memory, conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, magnetic tape), optical storage media, etc. Thus, the memory device 620 may rely on, for example, a stored voltage level or a stored resistance level. In certain embodiments, one or more elements 623 of the memory medium 622 include storage class memory (SCM).

[0087] While traditional technologies such as NAND flash may be addressable in blocks and / or pages, in one embodiment, storage class memory is addressable in bytes. In other embodiments, storage class memory may be faster and / or have a longer lifespan (e.g., durability) than NAND flash; may have a lower cost, use less power, and / or have a higher storage density than DRAM; or may provide one or more other benefits or improvements when compared to other technologies. For example, storage class memory may include one or more of the following: non-volatile memory elements 623 of ReRAM, memristor memory, programmable metallization cell memory, phase change memory, nano-RAM, nanocrystal wire-based memory, silicon-oxide-based sub-10-nanometer process memory, graphene memory, SONOS memory, PMC memory, CBRAM, MRAM, and / or variations thereof.

[0088] Although the non-volatile memory medium 622 is referred to herein as a "memory medium", in various embodiments, the non-volatile memory medium 622 may more generally include one or more non-volatile recording media capable of recording data, which may be referred to as non-volatile memory media, non-volatile storage media, and the like. Additionally, in various embodiments, the non-volatile memory device 620 may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, and the like. Similarly, in various embodiments, the non-volatile memory element 623 may include a non-volatile recording element, a non-volatile memory element, a non-volatile storage element, and the like.

[0089] The non-volatile memory medium 622 may include one or more non-volatile memory elements 623, which may include, but are not limited to: chips, packages, planes, dies, etc. The non-volatile memory controller 626 may be configured to manage data operations on the non-volatile memory medium 622 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the non-volatile memory controller 626 is configured to store data on the non-volatile memory medium 622 and / or read data from the non-volatile memory medium 622 to transfer data to / from the non-volatile memory device 620, etc.

[0090] The non-volatile memory controller 626 may be communicatively coupled to the non-volatile memory medium 622 via a bus 627. The bus 627 may include an I / O bus for transferring data to / from the non-volatile memory element 623. The bus 627 may further include a control bus for transferring addressing and other command and control information to the non-volatile memory element 623. In some embodiments, the bus 627 may communicatively couple the non-volatile memory elements 623 to the non-volatile memory controller 626 in parallel. This parallel access may allow the non-volatile memory elements 623 to be managed as a group, thereby forming a logical memory element 629. The logical memory element may be divided into corresponding logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks). The logical memory units may be formed by logically combining the physical memory units of each of the non-volatile memory elements.

[0091] The non-volatile memory controller 626 may include, or communicate with, a device driver executing on the computing device 610. The device driver may provide storage services to the storage client 616 via one or more of the interfaces 631, 632, and / or 633. In some embodiments, the device driver provides a block device I / O interface 631 through which the storage client 616 performs block-level I / O operations. Alternatively or additionally, the device driver may provide a storage class memory (SCM) interface 632, which may provide other storage services to the storage client 616. In some embodiments, the SCM interface 632 may include an extension to the block device interface 631 (e.g., the storage client 616 may access the SCM interface 632 through an extension or addition to the block device interface 631). Alternatively or additionally, the SCM interface 632 may be provided as a separate API, service, and / or library. The device driver may be further configured to provide a cache interface 633 for caching data using the non-volatile memory system 602. The device driver may further include a non-volatile memory device interface 639, which is configured to transfer data, commands, and / or queries to the non-volatile memory controller 626 via the bus 625, as described above.

[0092] Figure 7 Schematic block diagram illustrating an embodiment of a non-volatile storage device 710 that can perform the programming and verification operations described herein. The non-volatile storage device 710 may include one or more memory dies or chips 712A, where a "memory die" includes a block of semiconductor material on which memory circuits are fabricated and, as used herein, also includes the memory circuits disposed thereon. The non-volatile storage device 710 may be generally similar to the computing device 610 described with reference to Figure 6 above.

[0093] In some embodiments, the memory die 712 includes a memory cell array 700 (e.g., two-dimensional or three-dimensional), an on-die controller 720, and read / write circuits 730A / 730B. In one embodiment, access to the memory array 700 by various peripheral circuits is implemented symmetrically on opposite sides of the memory array 700, such that the access lines and the density of the circuitry on each side are reduced by half. In another embodiment, the read / write circuits 730A / 730B include a plurality of sense blocks 751 that allow parallel reading or programming of memory cell pages.

[0094] In various embodiments, the memory array 700 may be addressed via word lines by row decoder circuits 740A / 740B and via bit lines by column decoder circuits 742A / 742B. In some embodiments, the controller 744 is included in the same memory device 710 (e.g., removable memory card or package) as one or more memory dies 712. Commands and data are transferred between the host and the controller 744 via line 732, and between the controller and one or more memory dies 712 via line 734. One implementation may include multiple chips 712.

[0095] In one embodiment, the on-die controller 720 (e.g., controller circuitry) cooperates with read / write circuits 730A / 730B to perform memory operations on the memory array 700. In certain embodiments, the on-die controller 720 includes a state machine 722, an on-chip address decoder 724, a power control circuit 726, and a sub-group selection circuit 750. In one embodiment, the on-chip address decoder 724 and / or the power control circuit 726 may be part of the controller 744 and / or controlled by the controller 744. The on-die controller 720 is operable to select a particular single layer for a particular programming verification level and multiple layers for other programming verification levels.

[0096] In one embodiment, the state machine 722 provides chip-level control of the memory operations. The on-chip address decoder 724 provides an address interface to convert the addresses used by the host or the memory controller into hardware addresses used by the decoder circuits 740A, 740B, 742A, 742B. The power control circuit 726 controls the power and voltage supplied to the word lines and bit lines during memory operations. In one embodiment, the power control circuit 726 includes one or more charge pumps that can generate a voltage greater than the supply voltage. The state machine may be used to count bit scans and compare the result with a threshold that may be stored in the state machine. When the bit scan count exceeds the threshold, the state machine may also trigger a programming verification operation to skip to the next memory level verification operation.

[0097] In an embodiment, the on-die controller 720, the state machine 722, the power control circuit 726, the on-chip address decoder 724, the decoder circuit 742A, the decoder circuit 742B, the decoder circuit 740A, the decoder circuit 740B, the read / write circuit 730A, the read / write circuit 730B, and / or the controller 744, individually or in any combination, may be referred to as one or more management circuits or generally referred to as controller circuitry.

[0098] Figure 8Schematic diagram of non-volatile memory 800 in a first state. For ease of explanation, the memory is simplified. The first state of memory 800 shows more programmed data from sense amplifier data latches (SADLs) 801-1, 801-2, 801-3, 801-4, each of which is connected to bit lines 807-1, 807-2, 807-3, 807-4 through access transistors (e.g., source-gate-drain SGD transistors) 803-1, 803-2, 803-3, 803-4. The bit select line 805 is connected to the gates of the access transistors. Memory cells are schematically shown at 816, 817, 818, and 819. Memory cells 816, 817, and 819 are being programmed, e.g., with multiple programming pulses, which are then verified with signals at a lower voltage than the programming pulses. In an example state of memory 800, a first circuit string connected to SADL 801-1 is set to a programmed state where bit line 807-1 is at the Vss voltage level. A second circuit string connected to SADL 801-2 is set to a programmed state where bit line 807-2 is at the Vss voltage level. A third circuit string connected to SADL 801-3 is set to a prohibited state where bit line 807-3 is at the VDDSA voltage level. A fourth circuit string connected to SADL 801-4 is set to a programmed state where bit line 807-4 is at the Vss voltage level. Bit lines 807-1, 807-2, 807-3, 807-4 are positioned close to each other and thus have parasitic capacitance, here capacitors 811 between bit line 807-1 and bit line 807-2, capacitor 812 between bit line 807-2 and bit line 807-3, and capacitor 813 between bit line 807-3 and bit line 807-4. In the first state, there is no capacitance at capacitor 811 because both bit lines 807-1 and 807-2 are at the same signal level, here Vss. There is capacitance at capacitors 812, 813 because both pairs of adjacent bit lines 807-2, 807-3 and bit lines 807-3, 807-4 have different voltages on those lines. The voltage VDDSA on bit line 803-3 is a prohibit signal. Vss is a programming signal. Thus, when EQVDDSA is applied to one or more of the non-adjacent bit lines, there is a capacitive load (parasitic capacitance between adjacent bit lines). In each programming pulse, the programmed bit line is at the Vss level, and the prohibit BL is at the VDDSA level. This will occur during the first programming pulse to program memory cells (e.g., SLC, TLC, or other multi-level non-volatile memory cells). This is because more memory cells are programmed at the start of the programming operation, e.g., there is more programmed data than prohibit data. This is especially true for earlier pulses in TLC or multi-level cell programming operations.In operation, the signal EQVDDSA shorts all bit lines, e.g., lines 803-1, 803-2, 803-3, 803-4, and then slowly charges the bit lines to the VDDSA level and then discharges them after the programming pulse. The signal EQVVDDSA can be sent from the SADL side of the memory 800. The equalization operation involves applying the VDDSA voltage to all bit lines 807-1, 807-2, 807-3, 807-4 via a common EQ2VDDSA transistor and via respective BLX transistors.

[0099] In the case where more BLs are at the Vss level, this operation and structure of the memory 800 creates more capacitive load. Due to more bit lines at Vss, the initial equalization level is lower, which can cause inhibit cell interference. In operation, the programming voltage (Vss) is less than the bit line voltage, and the bit line voltage is less than the inhibit voltage (VDDSA). VDDSA is the higher inhibit voltage from SADL and can be the sense amplifier data latch voltage for inhibit programming.

[0100] Figure 9 A schematic diagram of the non-volatile memory 800 in a second state (i.e., at a later stage in the programming cycle after at least one programming pulse or after multiple programming pulses) is shown. In the example, the programming pulse is at least half complete, i.e., the programming is roughly half done. Thus, there are more inhibit data signals VDDSA (bit lines 807-1, 807-3, 807-4) compared to the programming signal Vss (bit line 807-3). The second state of the memory 800 contains more inhibit data than programmed data and is on a later programming pulse of the programming operation. The capacitive load is less because most of the bit lines are already at the VDDSA level. Since there are more bit lines at the VDDSA level, the initial equalization level is higher. Also, programming of the memory cells 816, 818, and 819 is inhibited.

[0101] In the operation of the memory 800, depending on the programmed data, e.g., whether there are more programming states ( Figure 8 ) or more inhibit states ( Figure 9 ), the equalization of the bit lines is controlled. However, if the bit lines are equalized too early, inhibit cell interference can occur. When the bit lines are charged to VDDSA, the capacitance between the bit lines creates more load. Here, EQVDDSA is deactivated to save power current (Icc) and to prevent read errors that may occur when residual charge in the bit lines is not released before a read operation.

[0102] Figure 10A method 1000 for adjusting bit line discharge during a single-level cell programming operation in a non-volatile memory device is shown. When the programming operation starts, the data to be programmed is randomly distributed. Statistically, during SLC programming, half of the starting programming data (e.g., 50%) is zero and half (50%) is one. The controller circuitry can control the state (enabled or disabled) of EQVDDSA based on the number of SLC programming pulses. For the first programming pulse, the programming data matches the starting data with half being zero and half being one. Enabling EQVDDSA results in better discharge. However, for subsequent pulses, most of the memory cells are already locked (programming prohibited) because there are very few remaining zero states in the data to be programmed. Now, EQVDDSA is disabled to save power (Icc).

[0103] In the case of SLC partial page programming, EQVDDSA can be controlled to be enabled or disabled. The memory controller can call partial page programming only in a block of 4K data or a block of 8K data. Partial page programming with 4K data and a random pattern results in only about one-sixth of the memory cells being zero (12.5% of the cells at the 0 level). Here, the method should disable equalization. (EQVDDSA disabled). Partial page writing with 8K data and a random pattern contains about one-quarter (25%) of the cells being zero. Here, the method should enable equalization (EQVDDSA enabled).

[0104] At step 1001, a single-level cell programming operation starts. The programming operation can include a series of programming pulses, and the voltage of the programming pulses increases with each successive pulse. Verification operations and signals are interspersed among the programming pulses to read the programmed data in order to verify that the memory cells are programmed to the correct voltage level. If the SLC is at the correct level, e.g., above the threshold voltage, the bit line for the memory cell changes from programmed (VSS or zero) to prohibited (VDDSA or one).

[0105] At step 1003, the controller determines whether the programming is for a full page or a partial page. If for a full page, the method moves to step 1005. If for a partial page, the method moves to step 1009.

[0106] At step 1005, for example, during a verification operation, after programming, e.g., after a programming pulse, a first programming pulse is applied and the bit line is equalized to VDDSA.

[0107] At step 1007, for the second or subsequent programming pulses, EQVDDSA is disabled.

[0108] At step 1009, it is determined whether the data block to be written is one quarter or less of an entire page. If it is one quarter or less of an entire page, then at step 1011, the equalization of VDDSA (EQVDDSA) is deactivated. If it is greater than one quarter of a page, then the equalization of VDDSA is activated.

[0109] Figure 11 A method 1100 for adjusting bit line discharge during a three-level cell (TLC) programming operation in a non-volatile memory device is shown. In TLC full sequence programming, a cell is programmed to one of the Er, A, B, C, D, E, F, G states. Er is the erased state, and A-G are programmed memory states as the threshold voltage gradually increases. In the case of fully randomized user data, each state statistically has 12.5% of the total cell count. The decision to enable or disable EQVDDSA can be based on the TLC data done signal. For the first programming pulse, the bit line inhibit or program consists of 87.5% zeros (program) and 12.5% ones (inhibit). EQVDDSA should be deactivated to prevent early equalization, which can cause interference and high Icc consumption. In an example embodiment, after the programming pulse (or program loop for the C state) for the C state is completed, about half of the memory cells may be programmed to the correct state and about half may be programmed to a locked state. At this time, about half of the memory cells are ones and half are zeros. Now, EQVDDSA will give better discharge results and is enabled. In an example embodiment, after the F programming is completed, on the bit line, about five eighths (or 87.5%) are programmed to ones and one eighth (or 12.5%) are programmed to zeros. Here, EQVDDSA can be deactivated again to save ICC because equalization is not needed. In an example embodiment, more refined control can also be accomplished through a program loop-based option.

[0110] At step 1101, three-level cell programming begins. In TLC full sequence programming, a cell is programmed to the Er, A, B, C, D, E, F, and G states, where each state has an one-eighth probability of occurring in the case of random data.

[0111] At 1103, the control circuitry generates a control signal on the bit line using the TLC data state. The voltage level of the bit line signal depends on the number of pulses that have been executed for programming.

[0112] At 1105, after the first, second, and third programming pulses, the equalization of the bit line is deactivated, such as deactivating EQVDDSA.

[0113] At 1107, after the fourth programming pulse (e.g., after programming the C state), the equalization of the bit line voltage is activated, such as activating EQVDDSA.

[0114] At 1109, after the seventh programming pulse (e.g., after the F programming state), the equalization of the bit line voltage is deactivated, e.g., EQVDDSA is deactivated. This will save power, e.g., Icc.

[0115] Figure 12 A method 1200 for adjusting bit line discharge during a four-level cell (QLC) programming operation in a non-volatile memory device is shown. In an example, QLC programming may include fuzzy / fine sequence programming. In QLC fuzzy / fine sequence programming, cells are programmed to Er, S1 to S15 states. In the case where user data is completely randomized, each state has 6.25% of the total cell count. In this example method 1200, EQVDDSA may be enabled or disabled based on the QLC data completion signal. Starting from the first programming pulse, for a random data set, 93.75% of the bit line values are zero (programmed) and 6.25% are one (blocked). EQVDDSA should be deactivated to prevent interference caused by early equalization and high Icc. After the completion of the S7 programming pulse, approximately 50% of the cells are locked, and half are one (blocked) and half are zero (programmed). Equalizing the bit line signal to VDDSA (i.e., the EQVDDSA operation when EQVDDSA is enabled) will provide better discharge results. After the completion of S13, on the bit line, approximately seven-eighths are blocked (e.g., one) and one-eighth are programmed (e.g., zero). Here, EQVDDSA should be deactivated again to save ICC because equalization is not required. More fine control can also be achieved through operations based on program loops.

[0116] At step 1201, a QLC programming operation is started.

[0117] At step 1203, based on the completion of the programming pulse, the equalization of the voltage on the bit line is controlled between the enabled and disabled states.

[0118] At step 1205, from after the first programming pulse (e.g., for S0) to the end of the sixth programming pulse (e.g., S5), the equalization on the bit line (e.g., EQVDDSA) is deactivated.

[0119] At step 1207, after the seventh programming pulse, the equalization on the bit line (e.g., EQVDDSA) is enabled.

[0120] At step 1209, after the thirteenth programming pulse, the equalization of the bit line (e.g., EQVDDSA) is deactivated.

[0121] Figure 13Disclosed is a method 1300 for adjusting bit line discharge during a four-level cell (QLC) programming operation using multi-level cells / fine programming in a non-volatile memory device (1301). In the QLC MLC / fine sequence programming operation, the MLC levels should be considered separately, where the memory cells are in the Er state or are programmed to the A, B, and C states. In the case of completely randomized user data, each state has one-quarter of the total cell count. The enabling / disabling of bit line equalization (e.g., EQVDDSA) is based on the MLC data done signal.

[0122] At step 1305, after the first programming pulse, three-quarters of the memory cells are zero (bit line programmed) and one-quarter are one (bit line prohibited). EQVDDSA should be disabled to prevent early equalization, which can cause interference and high Icc usage.

[0123] At step 1307, after the completion of state A, half of the cells are locked, where half are prohibited (one) and half are programmed (zero), and bit line equalization (EQVDDSA enabled) is enabled, which results in better discharge results.

[0124] At step 1309, after the completion of the state C programming pulse, three-quarters of the memory cells are programmed (bit line prohibited) and one-quarter are not programmed (bit line programmed). Now, bit line equalization (e.g., EQVDDSA) should be disabled again to save power, such as Icc, because equalization is not required. More precise control can also be achieved through options based on program loops.

[0125] Figure 14 Disclosed is a method 1400 for controlling signals on a bit line during a programming operation. At step 1401, the programming pulse count is set to zero.

[0126] At step 1403, a programming pulse operation is performed using at least one bit line at a programming level, and the other bit lines can be at a prohibited level (Vss) or a programming level (VDDSA).

[0127] At step 1405, the programming pulse count is incremented.

[0128] At step 1407, it is determined whether the programming pulse count is at or above a first threshold (e.g., as discussed above, whether it changes from disabled to enabled). If it is not above the threshold, the method moves to step 1409. If the pulse count exceeds the first threshold, the process moves to step 1408, where it is checked whether the programming pulse count exceeds a second threshold. If it does not exceed the second threshold, at step 1410, bit line equalization is enabled, and the method goes to the next programming pulse at 1403.

[0129] At step 1409, the equalization of the bit lines is deactivated, and the process returns to step 1403.

[0130] At step 1411, the equalization at the bit lines is deactivated or the discharging of the bit lines is prohibited. Unless the programming pulse count is at its highest value, e.g., when all programming levels have been carried out, after the operation of the bit line equalization at step 1411 changes, the process may return to step 1403. If the programming count is at the maximum value, method 1400 ends.

[0131] Figure 15 A simplified timing diagram 1500 of some control signals is shown, particularly the bit lines (BL sel) selected for programming (referred to herein as zero or programming) and the unselected or prohibited bit lines. In an example embodiment, Vinhibit shown in FIG. 1500 may be the same as VDDSA used herein. The first signal group may be used and repeated until the first programming pulse threshold is reached. Thereafter, EQVDDSA is enabled, and the prohibited bit lines do not follow the same pattern as those for which EQVDDSA is deactivated. A complete timing diagram can be found in U.S. Patent Publication No. 2020 / 0321055, which is incorporated herein by reference in its entirety. However, if any part of U.S. Patent Publication No. 2020 / 0321055 conflicts with this disclosure, this disclosure shall prevail.

[0132] Figure 16 Seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 for reading data from TLC memory cells are shown. By testing whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages (e.g., performing a sensing operation), the system can determine which data state (i.e., S0, S1, S2, S3, …) the memory cell is in.

[0133] Figure 16Seven verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 are also shown. When programming a memory cell to data state S1, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv1. When programming a memory cell to data state S2, the system will test whether the memory cell has a threshold voltage greater than or equal to Vv2. When programming a memory cell to data state S3, the system will determine whether the memory cell has a threshold voltage greater than or equal to Vv3. When programming a memory cell to data state S4, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv4. When programming a memory cell to data state S5, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv5. When programming a memory cell to data state S6, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv6. When programming a memory cell to data state S7, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv7.

[0134] In an embodiment referred to as full sequence programming, a memory cell can be programmed directly from an erased data state S0 to any one of the programmed data states S1 - S7. For example, a group of memory cells to be programmed can first be erased so that all memory cells in the group are in the erased data state S0. Then, the memory cells are directly programmed to data states S1, S2, S3, S4, S5, S6, and / or S7 using a programming process. For example, when programming some memory cells from data state S0 to data state S1, other memory cells are programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. Figure 16 The arrows in represent full sequence programming. The techniques described herein can also be used with other types of programming other than full sequence programming, including but not limited to multi - level / multi - stage programming. In some embodiments, data states S1 - S7 can overlap, where the controller 122 uses an error correction code (ECC) to identify the correct data stored.

[0135] Figure 17 is a table depicting an example of the assignment of data values to data states. In Figure 17 the table, S0 = 111, S1 = 110, S2 = 200, S3 = 000, S4 = 010, S5 = 011, S6 = 001, and S7 = 101. Other data encodings can also be used. The techniques disclosed herein do not require a specific data encoding.

[0136] In an embodiment, when a block is erased, all memory cells are moved to the data state S0, i.e., the erased state. As further discussed below, when the memory structure allows sub-blocks, the selected sub-blocks of a physical block are erased, but the unselected sub-blocks are not erased. In Figure 17 the embodiment of, when a memory cell is erased (e.g., in the data state S0), all bits stored in the memory cell are 1.

[0137] Figure 18 is a flowchart depicting an embodiment of a programming process performed by a controller circuitry. In some embodiments, the host may perform the functions of the controller circuitry without having a dedicated controller. In step 1802, the controller circuitry sends instructions to program data to one or more memory dies. In step 1804, the controller circuitry sends one or more addresses to one or more memory dies. The one or more logical addresses indicate the location to program the data. In step 1806, the controller circuitry sends the data to be programmed to one or more memory dies. In step 1808, the controller circuitry receives the result of the programming from one or more memory dies. Example results include an indication that the data was successfully programmed, an indication that the programming operation failed, and an indication that the data was programmed but at a different location, or other results. In step 1810, in response to the result received in step 1808, the controller circuitry updates the system information it maintains. In an embodiment, the system maintains a data table indicating the status information of each block. This information may include the mapping of logical addresses to physical addresses, which blocks / word lines are open / closed (or partially open / closed), which blocks / word lines are bad, and so on.

[0138] In some embodiments, prior to step 1802, the controller circuitry will receive host data and programming instructions from the host, and the controller will run an error correction code engine to create codewords based on the host data, as known in the art and described in more detail below. These codewords are the data transmitted in step 1806. The controller circuitry may also scramble the data to achieve wear leveling of the memory cells.

[0139] Figure 19 is a flowchart depicting an embodiment of a programming process. Figure 19 The process of responds to Figure 18 the steps of (i.e., in response to instructions, data, and addresses from the controller circuitry) and is performed by the memory die. In an example embodiment, under the guidance of a state machine, the process of is performed on the memory die circuitry using one or more of the control circuits discussed above. Figure 19 the process. Figure 19The process can also be used to implement the full sequence programming discussed above, including enabling the equalization of the programming voltage (Vddsa) from the sense amplifier data latch on the bit line after at least the first programming pulse or the first programming cycle of SLC programming, and disabling the equalization of the programming voltage (Vddsa) after the first programming pulse or programming cycle. Figure 19 The process can also be used for multi-level cell programming as described herein and includes enabling the equalization of the programming voltage (Vddsa) until at least half or more than half of the bit lines enter the forbidden level, and then disabling the equalization of the programming voltage (Vddsa) on the bit line. Additionally, Figure 19 The process can be used to implement each phase in a multi-phase programming process.

[0140] Typically, during a programming operation, the programming voltage applied to the control gate (via a selected word line) is applied in the form of a series of programming pulses. Between the programming pulses, there is a set of verification pulses for performing verification. In many embodiments, the magnitude of the programming pulses increases by a predetermined step with each successive pulse.

[0141] At Figure 19 step 1870, the programming voltage (Vpgm) is initialized to a starting magnitude (e.g., about 12.0V to 16.0V or another suitable level), and the program counter (PC) maintained by the state machine is initialized to the value 1.

[0142] At step 1872, the programming pulse Vpgm of the programming signal is applied to the selected word line (the word line selected for programming). In one embodiment, all the memory cell groups to be programmed simultaneously are all connected to the same word line (the selected word line). The unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to perform a boost scheme. If a memory cell is to be programmed, the corresponding bit line is grounded. On the other hand, if a memory cell is to maintain its current threshold voltage, the corresponding bit line is connected to Vdd to inhibit programming. At step 1872, the programming pulses are applied simultaneously to all the memory cells connected to the selected word line, such that all the memory cells connected to the selected word line are programmed simultaneously. That is, the memory cells are programmed simultaneously or during an overlapping time period (both of which are considered simultaneous). In this way, unless all the memory cells connected to the selected word line have been locked against programming, the memory cells will change their threshold voltages simultaneously.

[0143] At step 1874, one or more verification operations are performed using a set of appropriate verification reference voltages to verify the appropriate memory cells. In an embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verification reference voltage.

[0144] At step 1876, it is determined whether all memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. At step 1878, a "pass" status is reported. At 1876, if it is determined that not all memory cells have reached their target threshold voltages (fail), the programming process continues to step 1880.

[0145] At step 1880, the system counts the number of memory cells that have not reached their corresponding target threshold voltage distributions. That is, the system counts the number of memory cells that have so far failed the verification process. This counting can be done by a state machine, a controller, or other logic. In one embodiment, each of the sense blocks will store the status (pass / fail) of its corresponding cells. In one example, there is an overall count that reflects the total number of memory cells that failed the previous verification step and are currently being programmed. In another example, the counts for each data state are saved separately.

[0146] At step 1882, it is determined whether the count from step 1880 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a memory cell page. If the number of failed memory cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported at step 1878. In this case, enough memory cells have been programmed correctly such that some of the remaining memory cells that are not fully programmed can be corrected using ECC during the read process. In some embodiments, step 1880 will count the number of failed cells for each sector, each target data state, or other unit, and those counts will be compared to the threshold at step 1882 either individually or jointly.

[0147] In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during the read process to allow for future errors. When programming fewer than all memory cells for a page or comparing the counts for only one data state (or fewer than all states), the predetermined limit can be a fraction (proportional or not) of the number of bits that can be corrected by ECC during the read process of a memory cell page. In some embodiments, the limit is not predetermined. Instead, the limit changes based on the number of errors that have been counted for the page, the number of program-erase cycles that have been performed, or other criteria.

[0148] If the number of unpassed memory cells is not less than a predetermined limit value, the programming process proceeds to step 1884: check the programming counter PC against a programming limit (PL). Examples of programming limits include 12, 20, and 30; however, other values may be used. If the programming counter PC is not less than the programming limit PL, the programming process is considered to have failed, and a failed status is reported in step 1888. This is an example of a programming error. If the programming counter PC is less than the programming limit PL, the process proceeds to step 1886, during which the programming counter PC is incremented by 1 and the programming voltage Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is one step larger than the previous pulse (e.g., the step size is from 0.1 volts to 0.5 volts). After step 1886, the process loops back to step 1872: apply another programming pulse to the selected word line, thereby performing Figure 19 another iteration of the programming process (steps 1872 to 1886).

[0149] Generally, during the verification operation and the read operation, the selected word line is connected to a voltage (an example of a reference signal), the level of which is specific for each read operation (e.g., see Figure 16 the read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or specific for each verification operation (e.g., see Figure 16 the verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7), in order to determine whether the threshold voltage of the memory cell has reached such levels. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell has turned on (conducted current) in response to the voltage applied to the word line. If the measured conduction current is greater than a specific value, the memory cell is considered to have turned on, and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current greater than the specific value is not measured, the memory cell is considered not to have turned on, and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, one or more read pass voltages are provided at the control gates of the unselected memory cells such that these memory cells will act as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0150] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current is measured by the rate at which the conduction current of the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string containing the memory cell to discharge to a corresponding bit line. The voltage on the bit line is measured after a period of time to determine whether the bit line has discharged. It should be noted that the techniques described herein can be used with different methods for verification / read known in the art. Other read and verification techniques known in the art can also be used.

[0151] In some embodiments, the controller circuitry receives a request from a host (or client, user, etc.) to program host data (data received from the host) into the memory system. In some embodiments, the controller circuitry arranges the host data to be programmed into data units. For example, the controller circuitry can arrange the host data into pages, word line units, blocks, super blocks, or other units. For the purposes of this document, a block is a physical grouping of memory cells. In one example, a block is an erase unit. However, in other examples, a block need not be an erase unit. In one example, a block includes a group of memory cells connected by uninterrupted word lines, such as a group of NAND strings connected to a group of common word lines. Other physical arrangements can also be used.

[0152] Figure 19 Step 1872 thereof includes applying a programming voltage pulse on a selected word line. Figure 19 Step 1874 thereof includes verification, which in some embodiments includes applying a verification reference voltage on the selected word line. Since steps 1872 and 1874 are part of an iterative loop, the programming voltage is applied as a series of voltage pulses that step in magnitude. Between the voltage pulses, a verification reference voltage is applied. This is depicted in Figure 20 which shows the programming voltage pulses 1892, 1894, and 1896 applied during three consecutive iterations of step 1872. Between the programming voltage pulses 1892, 1894, and 1896, a system such as the controller circuitry tests the memory cell by applying a verification reference voltage as a verification pulse to determine whether the threshold voltage of the memory cell is greater than the corresponding verification reference voltage.

[0153] In Figure 19Before applying the programming pulse at step 1872 as described herein, program the memory cells as described herein. If a memory cell is to be programmed, ground the corresponding bit line. On the other hand, if the memory cell is to remain at its current threshold voltage, connect the corresponding bit line to a programming inhibit level, such as Vdd. In many embodiments, the word lines of an erase block are programmed starting from the word line source end, such as word line WL0. Since the other memory cells in the columns between the selected word line and the bit line are erased, this allows the level on the bit line to be uniformly applied to the memory cells of the selected word line, and this pre-charging of the memory cells can be prevented if any of the intermediate memory cells are to be programmed. Then, the word lines of the block are written sequentially in order from the source side at the bottom to the bit line at the drain end of the NAND string.

[0154] The module can also be implemented at least in part in software for execution by various types of processors. The identification module of the executable code can include, for example, one or more physical or logical blocks of computer instructions, which can be organized, for example, as objects, programs, or functions. However, the executable files of the identification module do not have to be physically located together, but can include different instructions stored in different locations, which, when logically combined, include the module and achieve the purpose of the module.

[0155] In fact, the module of the executable code can contain a single instruction or many instructions, and can even be distributed in several different code segments, different programs, across several memory devices, etc. In the case where the module or a part of the module is implemented in software, the software part can be stored on one or more computer-readable and / or executable storage media. Any combination of one or more computer-readable storage media can be utilized. The computer-readable storage media can include, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination of the foregoing listed, but will not include propagating signals. In the context of this document, the computer-readable and / or executable storage media can be any tangible and / or non-transitory medium that can contain or store a program for use by or in conjunction with an instruction execution system, device, processor, or apparatus.

[0156] Computer program code for performing operations in aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Python, Java, Smalltalk, C++, C#, Objective C, etc., conventional program programming languages such as the "C" programming language, scripting programming languages, and / or other similar programming languages. The program code may be executed, in part or in whole, on one or more of a user's computers and / or on a remote computer or server via a data network or the like. As used herein, a component includes a tangible physical non-transitory device. For example, a component may be implemented as a hardware logic circuit, which includes custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A component may also be implemented in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, etc. A component may include one or more silicon integrated circuit devices (e.g., chips, dies, die flats, packages) or other discrete electrical devices that are electrically communicable with one or more other components via wires of a printed circuit board (PCB) or the like. In certain embodiments, each of the modules described herein may alternatively be embodied or implemented as a component.

[0157] As used herein, a circuit or circuitry includes a set of one or more electrical and / or electronic components that provide one or more paths for current. In certain embodiments, a circuit may include a return path for current such that the circuit is a closed loop. However, in another embodiment, a set of components that does not include a return path for current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for current). In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated circuits with or without integrated circuit devices, and / or electrical components, etc. In an embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, etc. (e.g., as firmware, a netlist, etc.). A circuit may include one or more silicon integrated circuit devices (e.g., chips, dies, die flats, packages) or other discrete electrical devices that are electrically communicable with one or more other components via wires of a printed circuit board (PCB) or the like. In certain embodiments, each of the modules described herein may be embodied or implemented as a circuit.

[0158] By way of introduction, the following provides brief definitions for various terms used in this application. Additional definitions will be provided in the context of the discussion of the figures herein. As used herein, "exemplary" may indicate an instance, embodiment, and / or aspect and should not be construed as limiting or indicating a preference or preferred embodiment. Further, it should be understood that specific ordinal terms (e.g., "first" or "second") may be provided for identification and ease of reference and may not necessarily imply a physical characteristic or order. Thus, as used herein, ordinal terms (e.g., "first", "second", "third") used to modify elements such as structures, components, operations, etc. do not necessarily indicate the priority or order of the element relative to another element, but merely distinguish the element from another element with the same name (but a different ordinal term used). Additionally, as used herein, the indefinite article ("a / an") may indicate "one or more" rather than "one". As used herein, a structure or operation that "comprises" or "includes" an element may include one or more other elements not explicitly recited. Thus, unless otherwise expressly specified, the terms "comprising", "including", "having" and variations thereof mean "including but not limited to". Unless otherwise expressly specified, the terms "a / an", "and", "the" also refer to "one or more". Further, an operation performed "based on" a condition or situation may also be performed based on one or more other conditions or situations not explicitly recited. As used in this application, the terms "example", "one example", "another example" or similar language do not refer to a single variation of the disclosed subject matter; instead, this language refers to variations of the disclosed subject matter that may be applied and used with several different embodiments of the disclosed subject matter. Unless otherwise expressly specified, a list of recited items does not imply that any or all of the items are mutually exclusive and / or mutually inclusive.

[0159] Aspects of the present disclosure are described below with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the present disclosure. It should be understood that each block of the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor or other programmable data processing apparatus create means for implementing the functions and / or actions specified in one or more blocks of the schematic flowcharts and / or schematic block diagrams.

[0160] It should also be noted that in some alternative implementations, the functions labeled in the blocks may not occur in the order labeled in the figures. For example, depending on the functionality involved, two consecutively presented blocks may actually be performed substantially simultaneously, or these blocks may sometimes be performed in the reverse order. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks or portions thereof shown in the figures. Although various arrow types and line types may be employed in the flowcharts and / or block diagrams, it should be understood that they do not limit the scope of the corresponding embodiments. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between the listed steps of the depicted embodiment.

[0161] As used herein, a "memory cell" includes a hardware component that can store a single state. A memory cell may include a volatile or non-volatile memory cell. The state stored in a memory cell may represent one of various types of values, e.g., a unit value or a multi-bit value.

[0162] In the foregoing detailed description, reference has been made to the accompanying drawings, which form a part of the description. The foregoing summary is merely illustrative and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, additional aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of the elements in each figure may refer to the elements of the foregoing figures. Like reference numerals in the figures may refer to like elements, including alternative embodiments containing the same elements.

[0163] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications suited to the particular use contemplated. It is intended that the scope of the invention be defined by the appended claims.

Claims

1. An apparatus, comprising: a plurality of memory cells configured to store a plurality of states; a memory controller operatively connected to the plurality of memory cells to control data storage therein and configured to: apply a programming control signal to a selected bit line to program a selected one of the plurality of memory cells, thereby programming the selected memory cell, and apply a prohibit control signal to unselected ones of the plurality of memory cells to prevent programming of the unselected memory cells, after applying an initial programming pulse to the selected memory cell, deactivate an equalization signal applied to the selected bit line, and immediately activate the equalization signal applied to the selected bit line after a threshold number of programming pulses is reached.

2. The apparatus according to claim 1, wherein the memory controller is configured to set the threshold of the programming pulse to a value at which at least half of the plurality of memory cells are programmed to corresponding final memory states.

3. The apparatus according to claim 2, wherein the memory controller is further configured to deactivate the equalization signal to reduce power consumption and reduce prohibit memory cell interference.

4. The apparatus according to claim 1, wherein the memory controller is configured to control programming of single-level cells and deactivate the equalization signal for a first programming pulse.

5. The apparatus according to claim 4, wherein the memory controller is configured to activate bit line equalization after a second programming pulse or a later programming pulse.

6. The apparatus according to claim 1, wherein the memory controller is configured to control programming of single-level cells on a partial page by selectively activating and deactivating the equalization signal for a predetermined programming pulse.

7. The apparatus according to claim 1, wherein the memory controller is configured to control programming of triple-level cells and deactivate the equalization signal for the first three programming pulses.

8. The apparatus according to claim 7, wherein the memory controller is configured to activate the equalization after completion of C-level programming.

9. The apparatus according to claim 8, wherein the memory controller is configured to deactivate the equalization after completion of F-level programming.

10. The apparatus according to claim 1, wherein the memory controller is configured to control programming of quad-level cells, deactivate the equalization signal for at least a first programming pulse, activate the equalization signal after completion of S7 programming, and deactivate the equalization signal after completion of S13 programming.

11. The apparatus according to claim 1, wherein the memory controller is configured to control programming of quad-level cells using MLS / fine programming, deactivate the equalization signal for at least a first programming pulse, activate the equalization signal after completion of A programming, and deactivate the equalization signal after completion of C programming.

12. A non-volatile memory control method, comprising: applying a selection control signal to a selected bit line to address a selected one of a plurality of memory cells, thereby programming the selected memory cell; Apply a prohibit control signal to the unselected memory cells among the multiple memory cells to prevent programming of the unselected memory cells; Deactivate the discharge of the selected bit line until an initial programming pulse is applied to the selected memory; And Immediately enable the discharge of the selected bit line after reaching the threshold of the programming pulse.

13. The method according to claim 12, wherein the step of enabling the discharge of the selected bit line includes equalizing the bit line to VDDSA before discharging the bit line.

14. The method according to claim 12, further comprising setting the threshold of the programming pulse to a value at which at least half of the memory cells are programmed to the corresponding final memory state.

15. The method according to claim 12, further comprising controlling the programming of single-level cells, and wherein deactivating the discharge of the selected bit line includes deactivating the discharge for the first programming pulse.

16. The method according to claim 12, further comprising the step of controlling the programming of three-level cells, and wherein deactivating the discharge of the selected bit line includes deactivating the discharge of the bit line for the first three programming pulses.

17. The method according to claim 16, wherein the step of enabling the discharge of the selected bit line further includes enabling the deactivated bit line to discharge after completing C programming.

18. The method according to claim 17, wherein the step of deactivating the discharge of the selected bit line further includes deactivating the previously enabled bit line after completing F programming.

19. A non-volatile memory control method, comprising: Set the programming pulse count to zero; Execute programming pulses using a bit line at a programming level; Increment the programming pulse count; When the programming pulse count is below a first threshold, deactivate the discharge of the bit line between programming pulses, and Then execute subsequent programming pulses by returning to execute programming pulses using a bit line at a programming level; When the programming pulse count is at or above the first threshold, enable the discharge of the bit line between programming pulses, and then return to execute programming pulses using a bit line at a programming level and increment the programming pulse count; And When the programming pulse count is above a second threshold, deactivate the discharge of the bit line between programming pulses.

20. The method according to claim 19, wherein executing the programming pulse includes executing programming pulses for a QLC memory, setting the first threshold at an S7 programming pulse level, and setting the second threshold at an S13 programming pulse level.

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