System and method for adjusting threshold voltage distribution due to semi- circular SGD

Abstract

The following disclosure relates to mitigating issues related to semi-circular drain side gate (SC-SGD) memory holes in a memory structure. When a memory hole is cut, the channel and charge trapping layer of the memory hole are cut. In addition, the outer dielectric layer (used to shield the channel and the charge trapping layer) is cut and partially removed. When a selected SC-SGD is selected for operation (e.g., programming), the channel and the charge trapping layer are exposed to an adjacent electric field from a bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electric field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, the present disclosure relates to a self-compensation technique for SC-SGDs. For example, the memory structure can utilize the adjacent electric field during verify, program, and read operations regardless of whether the adjacent electric field is relatively strong or weak.

Description

Technical Field

[0001] This application relates to defining a semi-circular memory hole by utilizing a memory hole with its edges cut / altered. Specifically, this application relates to optimizing the threshold voltage of a semi-circular memory hole. The optimized threshold voltage of the semi-circular memory hole better matches the threshold voltage of a full-circular memory hole. Background Technology

[0002] Semicircular drain-side selected gate (“SC-SGD”) memory technology offers several advantages, including reduced die size. To produce an SC-SGD, etching techniques are used to cut memory holes, thus giving them a semicircular shape and separating blocks or rows into strings. Depending on the process used to form the SC-SGD, certain problems can occur. For example, cutting memory holes removes at least some portion of the SC-SGD, such as removing metal layers that otherwise shield against electric fields from the channel and / or charge trapping layers. As a result, the SC-SGD can be affected by “adjacent” electric fields, causing parasitic transistors to leak along the SC-SGD transistor. In some cases, this causes the sense amplifier to improperly determine that the SC-SGD is positively conducting, which can affect certain sensing operations. Additionally, it is known that adjacent electric fields distort the threshold voltage of the SC-SGD (e.g., shift it downwards), and thus change the overall threshold voltage of the memory structure. Summary of the Invention

[0003] One aspect of this disclosure relates to a method for accessing a memory device. The method includes biasing a first semi-circular drain-side selected gate (SC-SGD) using a first voltage. The first SC-SGD is located on a first edge of an etched region. The method further includes biasing a second SC-SGD using a second voltage less than the first voltage. The second SC-SGD is located on a second edge of the etched region opposite the first edge. A controller, including but not limited to an SSD controller, is used to perform the steps.

[0004] In an embodiment, the second voltage includes a negative voltage.

[0005] In this embodiment, the negative voltage is less than zero volts.

[0006] In one embodiment, the etched area includes a shallow hole etching (SHE) cut.

[0007] In this embodiment, the selected negative voltage is based on the width of the SHE cut portion.

[0008] In one embodiment, during the programming operation, the method continues to provide program pulses to the data word lines of the memory device. The method continues to use a verification voltage to bias the first SC-SGD. The first SC-SGD is programmed during the programming operation. The method continues to use a negative verification voltage to bias the second SC-SGD.

[0009] In one embodiment, during the read operation, the method continues to use the first SC-SGD to select the string to be read. The method continues to use a read voltage to bias the first SC-SGD. The method continues to use a negative read voltage to bias the second SC-SGD.

[0010] According to another aspect of this disclosure, a memory system includes a memory device. The memory system includes a controller operatively coupled to the memory device. The controller is configured to bias a first semi-circular drain-side selected gate (SC-SGD) using a first voltage. The first SC-SGD is located on a first edge of an etched region. The controller is further configured to bias a second SC-SGD using a second voltage less than the first voltage. The second SC-SGD is located on a second edge of the etched region opposite the first edge.

[0011] In an embodiment, the second voltage includes a negative voltage.

[0012] In this embodiment, the negative voltage is less than zero volts.

[0013] In one embodiment, the etched area includes a shallow hole etching (SHE) cut.

[0014] In this embodiment, the selected negative voltage is based on the width of the SHE cut portion.

[0015] In one embodiment, during programming operations, the controller is further configured to provide program pulses to the data word lines of the memory device. The controller is further configured to bias the first SC-SGD using a verification voltage. The first SC-SGD is programmed during the programming operation. The controller is further configured to bias the second SC-SGD using a negative verification voltage.

[0016] In one embodiment, during a read operation, the controller is further configured to use the first SC-SGD to select the string to be read. The controller is further configured to bias the first SC-SGD using a read voltage. The controller is further configured to bias the second SC-SGD using a negative read voltage.

[0017] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is configured to store instructions that, when executed by a processor of a controller comprising a memory system, cause the memory system to perform the following steps: biasing a first semi-circular drain-side selected gate (SC-SGD) using a first voltage. The first SC-SGD is located on a first edge of an etched region. The instructions further cause the memory system to perform the following step: biasing a second SC-SGD using a second voltage less than the first voltage. The second SC-SGD is located on a second edge of the etched region opposite the first edge.

[0018] In an embodiment, the second voltage includes a negative voltage.

[0019] In this embodiment, the negative voltage is less than zero volts.

[0020] In one embodiment, the etched area includes a shallow hole etching (SHE) cut.

[0021] In this embodiment, the selected negative voltage is based on the width of the SHE cut portion.

[0022] In an embodiment, the instructions further cause the memory system to perform the following steps: providing program pulses to the data word lines of the memory device. The instructions further cause the memory system to perform the following steps: biasing the first SC-SGD using a verification voltage. The first SC-SGD is programmed during a programming operation. The instructions further cause the memory system to perform the following steps: biasing the second SC-SGD using a negative verification voltage.

[0023] In an embodiment, during a read operation, the instructions further cause the memory system to perform the following steps: using a first SC-SGD to select the string to be read. The instructions further cause the memory system to perform the following steps: biasing the first SC-SGD with a read voltage. The instructions further cause the memory system to perform the following steps: biasing the second SC-SGD with a negative read voltage. Attached Figure Description

[0024] A more detailed description is set forth below with reference to exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings merely depict exemplary embodiments of this disclosure and are therefore not to be considered as limiting its scope. This disclosure is described and explained with additional specificity and detail using the accompanying drawings, in which:

[0025] Figure 1A A block diagram of an example memory device;

[0026] Figure 1B A block diagram of an example control circuit that includes programming circuitry, counting circuitry, and determining circuitry;

[0027] Figure 2 The diagram illustrates three types of memory architectures that utilize interleaved memory strings.

[0028] Figure 3A A cross-sectional view of an example floating gate memory cell in a NAND string is shown;

[0029] Figure 3B Show along Figure 3A The cross-sectional view of the contact line shown in the image;

[0030] Figure 4A and 4B A non-volatile memory is shown, in which the charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner;

[0031] Figure 5 An example block diagram of the sensing block in Figure 1 is shown;

[0032] Figure 6A This is a perspective view of the block set in an example three-dimensional configuration of the memory array in Figure 1;

[0033] Figure 6B Show Figure 6A An example cross-sectional view of a portion of one of the blocks;

[0034] Figure 6C Show Figure 6B A plot of the diameter of the memory holes in the stack;

[0035] Figure 6D Show Figure 6B A close-up view of the stacking area;

[0036] Figure 7A A schematic plan view of a memory array with multiple memory holes is shown;

[0037] Figure 7B A cross-sectional view of the memory array is shown;

[0038] Figure 8A and 8B An alternative memory structure without dummy holes is shown;

[0039] Figure 9 An embodiment of a memory array having memory holes of different sizes cut based on a SHE cutting operation is shown;

[0040] Figure 10 The illustration shows a memory structure with several memory holes cut by a SHE according to some of the described embodiments;

[0041] Figure 11 A graph showing the Vt distribution of a memory structure with memory holes according to some of the described embodiments is shown.

[0042] Figure 12 A circuit diagram showing transistors with selected and unselected gates is shown;

[0043] Figure 13 The illustration shows a memory structure with several memory holes cut by a SHE according to some described embodiments, which further illustrates process variations in the SHE;

[0044] Figure 14 A graph showing the difference in Vt of the memory aperture based on NSI values ​​according to some of the described embodiments is shown;

[0045] Figure 15A The SC-SGD memory aperture exposed to NSI during the verification operation is shown.

[0046] Figure 15B The SC-SGD memory aperture exposed to NSI during programming operations is shown.

[0047] Figure 15C The SC-SGD memory hole is shown during a read operation;

[0048] Figure 16 A flowchart illustrating a method for programming a memory structure according to some described embodiments is shown;

[0049] Figure 17 A flowchart illustrating a method for reading from a memory structure according to some described embodiments is shown;

[0050] Figure 18 A flowchart illustrating alternative methods for programming a memory structure according to some of the described embodiments is shown; and

[0051] Figure 19 A flowchart illustrating alternative methods for reading from a memory structure, according to some of the described embodiments, is shown. Detailed Implementation

[0052] The following description relates to various exemplary embodiments of this disclosure. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and that detailed explanations of any particular embodiment are merely illustrative and not intended to indicate that the scope of this disclosure, including the claims, is limited to that particular embodiment.

[0053] The following disclosure relates to mitigating problems associated with semi-circular drain-side selected gate (SC-SGD) memory vias in memory structures. Specifically, this disclosure relates to a method of managing the threshold voltage (Vt) of the SC-SGD, since the Vt of the SC-SGD is altered and therefore differs from the Vt of a full-circular drain-side selected gate (“FC-SGD”) memory via. When creating various rows and strings for memory structures, cutting operations (e.g., shallow hole etching or SHE) can be used. However, this operation removes portions of the memory vias in some rows, resulting in SC-SGDs. When the SC-SGD memory vias are being programmed, both the selected and unselected SGDs require bias voltages. Depending on the bias voltage on the unselected SGD, the selected SGD may be exposed to bias voltages that cause interference known as adjacent selected gate interference (“NSI”) and turn on parasitic transistors, resulting in leakage current. To mitigate or prevent bias voltage problems, the bias voltage on the unselected SGD may be reduced to 0 volts (“V”) or a negative voltage (e.g., -2V). By reducing the bias voltage in this way, unwanted current leakage through the parasitic transistor is prevented, and current flow through a selected SGD transistor is controlled, which can be properly monitored by a sense amplifier.

[0054] Furthermore, a self-compensating gate-selective programming method is proposed to address the adjacent SGD interference (“NSI”) effect. This method utilizes an adjacent electric field (which biases an unselected SGD) that “attacks” or interferes with the selected SGD during the verification / programming operation to activate a semi-circular SGD cell, or at least a portion thereof. Following a subsequent program pulse, the adjacent electric field is utilized and used for several purposes. First, the adjacent electric field generates additional trapped charge compensation within an SC-SGD with larger adjacent coupling. And, the adjacent electric field generates less additional trapped charge compensation within an SC-SGD with less adjacent coupling. Furthermore, no additional trapped charge compensation exists within a full-circular drain-side selected gate (“FC-SGD”). The additional trapped charge is adaptive to the adjacent electric field and therefore automatically provides NSI compensation. All these self-compensations occur simultaneously without sacrificing performance and without a significant increase in design cost.

[0055] Several aspects of this disclosure may be embodied in the form of an apparatus, system, method, or computer program process. Therefore, aspects of this disclosure may be entirely in the form of a hardware embodiment or a software embodiment (including but not limited to firmware, resident software, microcode, etc.), or may be a combination of both hardware and software components, generally referred to collectively as a "circuit," "module," "device," or "system." Furthermore, various aspects of this disclosure may be in the form of a computer program process, for example embodied in one or more non-transitory computer-readable storage media storing computer-readable and / or executable program code.

[0056] Furthermore, various terms are used herein to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this specification is not intended to distinguish between components with different names but the same function. With regard to the use of the term "module" for the various functional units described in the following disclosure, such a designation is intended not to unduly limit the scope of potential implementers. For example, a "module" may be implemented as hardware circuitry containing custom-designed very large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors containing logic chips, transistors, or other discrete components. In another instance, a module may also be implemented as a programmable hardware device, such as a field-programmable gate array (FPGA), programmable array logic, programmable logic device, etc. Furthermore, modules may be implemented at least in part by software executed by various types of processors. For example, a module may include a piece of executable code constituting one or more physical or logical blocks of computer instructions that translate into objectives, processes, or functions. And, it is not necessary for the executable portions of such modules to be physically located together, but rather they may include different instructions stored in different locations and, when executed together, include the identified module and achieve the stated purpose of the module. Executable code may consist of a single instruction or a set of multiple instructions, and may be distributed across different code segments, different programs, or across several memory devices, etc. In software or partial software module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, said media including, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may include any tangible and / or non-transitory medium capable of containing and / or storing programs for use by or in conjunction with an instruction execution system, device, processor, or apparatus.

[0057] Similarly, for the purposes of this disclosure, the term "component" may include any tangible, physical, and non-transitory device. For example, a component may take the form of hardware logic circuitry, including custom VLSI circuitry, gate arrays, or other integrated circuits, or include off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic device. Additionally, a component may be implemented in programmable hardware devices, such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Furthermore, a component may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, which are electrically connected to one or more other components via electrical conductors, such as printed circuit boards (PCBs). Therefore, modules as defined above may be embodied or implemented as components in some embodiments, and in some cases, the terms module and component are used interchangeably.

[0058] As used herein, a "circuit" comprises one or more electrical and / or electronic components that form one or more conductive paths allowing current to flow. A circuit can be in the form of a closed-loop or open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for current. Conversely, in an open-loop configuration, the circuit components may still be considered to form a circuit, even though no return path for current is provided. For example, an integrated circuit is referred to as a circuit regardless of whether it is coupled to ground (as a return path for current). In some exemplary embodiments, a circuit may include a set of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuitry, gate arrays, logic circuitry, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may include one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, which are electrically connected to one or more other components via electrical conductors, such as a printed circuit board (PCB). The circuit may also be implemented as a composite circuit relative to programmable hardware devices, such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Thus, in some embodiments, modules as defined above may be embodied in or implemented as circuits.

[0059] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specific stored computer program instructions that control the one or more microprocessors to implement some, most, or all of the functions disclosed herein in combination with certain non-processor circuitry and other components. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or implemented in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein each function or some combination of functions is implemented as custom logic. Combinations of these methods may also be used. Furthermore, the reference to “controller” below should be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or processors with control software, or combinations thereof.

[0060] Furthermore, as may be used herein, the terms “program,” “software,” “software application,” etc., refer to a sequence of instructions designed to be executed on a computer-implemented system. Therefore, a “program,” “software,” “application,” “computer program,” or “software application” may include subroutines, functions, programs, target methods, target implementations, executable applications, applets, server applets, source code, object code, shared libraries / load libraries, and / or other specific sequences of instructions designed to be executed on a computer system.

[0061] Additionally, the term "coupled" as used herein refers to a direct connection or an indirect connection. Therefore, if a first device couples to or is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices (or components) and connections.

[0062] Regarding the use of terms such as “embodiment,” “one embodiment,” “exemplary embodiment,” “specific embodiment,” or other similar terms in this document, these terms are intended to indicate a particular feature, structure, function, operation, or characteristic described in connection with an embodiment found in at least one embodiment of this disclosure. Therefore, unless explicitly stated otherwise, the appearance of phrases such as “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” etc., may, but not necessarily, refer to the same embodiment, but rather means “one or more, but not all, embodiments.” Furthermore, the terms “comprising,” “having,” “including,” and variations thereof are used in an open-ended manner and, therefore, unless explicitly stated otherwise, should be interpreted as meaning “including but not limited to….” And, without further limitations, an element beginning with “comprising…” does not exclude the presence of additional identical elements in the individual processes, methods, systems, articles, or apparatuses that include said element.

[0063] Unless otherwise expressly stated, the terms "a / an" and "the" also mean "one or more". Additionally, the phrase "at least one of A and B" as used herein and / or in the appended claims is similar to the phrase "and / or" indicating a choice of A or B, or both A and B, where A and B are variables indicating a particular object or property. Where there are more than two variables in this phrase, the phrase is defined herein as containing only one variable, any one variable, any combination (or subcombination) of any variables, and all variables.

[0064] Furthermore, the terms “about” or “approximately” as used herein apply to all numerical values, whether explicitly stated or not. These terms generally refer to the range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(i.e., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0065] Furthermore, unless otherwise expressly stated, any enumeration of items described herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive. Additionally, the term “set” as used herein should be interpreted as meaning “one or more,” and unless otherwise expressly stated, in the case of “set,” it should be interpreted according to set theory as meaning a multiple (or many) of “one or more, ones or more, and / or ones or mores.”

[0066] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. It should be understood that the foregoing overview is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, exemplary embodiments, and features described above, further aspects, exemplary embodiments, and features will become more apparent from the accompanying drawings and the detailed description below. The description of elements in each figure may refer to elements of the aforementioned figures. The same reference numerals in the figures may refer to the same elements, and alternative exemplary embodiments containing the same elements are also included.

[0067] Figure 1AThis is a block diagram of an example memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 (e.g., a memory cell array), a control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuitry 128 includes multiple sensing blocks SB1, SB2, ..., SBp (sensing circuitry) and allows parallel reading or programming of memory cell pages. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via line 118.

[0068] Memory structure 126 may be two-dimensional or three-dimensional. Memory structure 126 may include one or more memory cell arrays, including three-dimensional arrays. Memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory layers are formed on (but not within) a single substrate, such as a wafer, without intermediate substrates. Memory structure 126 may include any type of non-volatile memory, which is monolithically formed in one or more physical layers of a memory cell array having active regions disposed on a silicon substrate. Memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is on or within the substrate.

[0069] The control circuitry 110 works in conjunction with the read / write circuitry 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

[0070] For example, a storage area 113 may be provided for programming parameters. Programming parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, etc. Location parameters may indicate the location of the memory cell within the entire array of NAND strings, the location of the memory cell within a specific group of NAND strings, the location of the memory cell on a specific plane, etc. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material included with the contact connector, etc.

[0071] On-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operation. The power control module may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0072] In some embodiments, some components may be combined. In various designs, one or more of the components other than memory structure 126 (individually or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any one or a combination of the following: control circuit system 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0073] The control circuitry may include programming circuitry configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuitry performs programming on a word line, after which the programming circuitry applies a verification signal to the word line. The control circuitry may also include a counting circuit configured to obtain a count of memory cells that have passed a verification test for one data state. The control circuitry may also include a determining circuit configured to determine a specific programming and verification iteration among the plurality of programming and verification iterations based on an amount by which the count exceeds a threshold, in which a verification test for another data state is performed on the memory cells assigned to represent another data state.

[0074] For example, Figure 1B This is a block diagram of an example control circuit 150, which includes a programming circuit 151, a counting circuit 152, and a determining circuit 153.

[0075] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct several read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may exist. The techniques presented herein reduce the likelihood of uncorrectable errors.

[0076] Storage devices 122a and 122b include code, such as an instruction set, and processor 122c can be used to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c can access the code from storage device 126a of memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. For example, controller 122 can use the code to access memory structure 126, for example, for programming, reading, and erasing operations. The code may include startup code and control code (e.g., an instruction set). Startup code is software that initializes controller 122 during a startup or boot process and enables controller 122 to access memory structure 126. Controller 122 can use the code to control one or more memory structures 126. Upon power-up, processor 122c retrieves startup code from ROM 122a or storage device 126a for execution, and the startup code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by processor 122c. The control code contains drivers for performing basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0077] Generally, control code may contain instructions for performing the functions described herein, including steps with flowcharts discussed further below, and provide voltage waveforms with flowcharts discussed further below.

[0078] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices for communicating with the one or more processors.

[0079] Other types of non-volatile memory besides NAND flash memory can also be used.

[0080] Semiconductor memory devices include: volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”); non-volatile memory devices, such as resistive random access memory (“ReRAM”); electrically erasable programmable read-only memory (“EEPROM”); flash memory (which can also be considered a subset of EEPROM); ferroelectric random access memory (“FRAM”) and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices can be configured in NAND or NOR configurations.

[0081] Memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting examples, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optionally steering elements, such as diodes or transistors. Additionally, by way of non-limiting examples, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0082] Multiple memory elements can be configured such that they are connected in series or that each element is individually accessible. By way of a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a series-connected collection of transistors including memory cells and SG transistors.

[0083] NAND memory arrays can be configured such that the array consists of multiple memory strings, where each string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0084] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device layer. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends generally parallel to the main surface of the substrate supporting the memory elements (e.g., in an xy-direction plane). The substrate may be a wafer on which the memory element layer is formed, or it may be a carrier substrate attached to the memory elements after the memory elements are formed. As a non-limiting example, the substrate may contain a semiconductor such as silicon.

[0085] Memory elements can be arranged in an ordered array, such as multiple rows and / or columns, within a single memory device hierarchy. However, memory elements can be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0086] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device layers, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the z direction is generally perpendicular to the main surface of the substrate, and the x and y directions are generally parallel to the main surface of the substrate).

[0087] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device layers. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending generally perpendicular to the main surface of the substrate, i.e., columns extending along the y-direction), each column having multiple memory elements. These columns can be arranged, for example, in a two-dimensional configuration in the xy-plane, thereby producing a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of memory elements in three-dimensional form can also constitute a three-dimensional memory array.

[0088] With the aid of non-limiting examples, in a three-dimensional NAND string array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR configuration and ReRAM configuration.

[0089] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may comprise a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared, or intercalation layers may be present between memory device levels.

[0090] Next, the two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory device layers before stacking, but since the memory device layers are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Alternatively, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip memory device.

[0091] Figure 2 Schematic diagrams illustrating three types of memory architectures utilizing interleaved memory strings are shown. For example, reference numeral 201 illustrates a schematic diagram of a first example memory architecture, reference numeral 203 illustrates a schematic diagram of a second example memory architecture, and reference numeral 205 illustrates a schematic diagram of a third example memory architecture. In some embodiments, as shown, the memory architecture may comprise an array of interleaved NAND strings.

[0092] Figure 2 Blocks 200 and 210 of memory cells are shown in an example two-dimensional configuration of the memory array 126 of Figure 1. The memory array 126 may contain a plurality of such blocks 200 and 210. Each example block 200, 210 contains several NAND strings and corresponding bit lines, such as BL0, BL1, ..., which are shared within the block. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The NAND string is connected at its other end to a source-side select gate (SGS), which is then connected to a common source line 220. Sixteen word lines, for example, WL0 to WL15, extend between the SGS and the SGD. In some cases, dummy word lines without user data may also be used in the memory array adjacent to the select gate transistor. Such dummy word lines can protect edge data word lines from certain edge effects.

[0093] One type of non-volatile memory that can be configured in a memory array is, for example... Figure 3A and 3B The floating gate memory shown is of this type. However, other types of non-volatile memory can also be used. This will be discussed in further detail below. Figure 4A and 4B In another example shown, the charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric, formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”), is sandwiched between a conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are trapped and stored in a finite region. This stored charge then detectably alters a threshold voltage (“Vt”) of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. Similar cells can be configured in a discrete gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0094] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain. The charge of one data bit is located in the dielectric layer near the drain, and the charges of the other data bits are located in the dielectric layer near the source. Multi-state data storage is obtained by separately reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0095] Figure 3A Cross-sectional views of example floating-gate memory cells 300, 310, and 320 in a NAND string are shown. In this figure, bit lines or NAND string directions enter the page, and word line directions are from left to right. As an example, word line 324 extends across the NAND string containing corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different corresponding NAND string. An inter-silicon dielectric (IPD) layer 328 is also shown. Control gates 302, 312, and 322 are portions of word lines. Figure 3B The image shows a cross-sectional view along the contact line connector 329.

[0096] Control gates 302, 312, and 322 surround floating gates 304, 314, and 321, thereby increasing the surface contact area between control gates 302, 312, and 322 and floating gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio that makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is almost no space between two adjacent floating gates 302, 312, and 322 for control gates 302, 312, and 322 and the IPD layer 328.

[0097] As an alternative, such as Figure 4A and 4B As shown, planar or flat memory cells 400, 410, and 420 have been developed, wherein control gates 402, 412, and 422 are planar or flat; that is, the control gates do not surround the floating gate and the control gates only contact the charge storage layer 428 above them. In this case, there is no advantage in having a high floating gate. In fact, the floating gate becomes thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0098] Figure 4A A cross-sectional view depicting example charge-trapping memory cells 400, 410, and 420 in a NAND string is shown. The view is taken in the word line direction of the memory cells 400, 410, and 420, which are two-dimensional examples of memory cells 400, 410, and 420 in the memory cell array 126 of FIG. 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator, such as a SiN film, to store electrons, compared to floating-gate MOSFET technology, which uses a conductor such as doped polysilicon to store electrons. As an example, word line 424 extends across a NAND string containing corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are an IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer 404, 414, 421 extends continuously within its respective NAND string. The flat configuration of the control gate can be thinner than a floating gate. Furthermore, memory cells can be placed closer together.

[0099] Figure 4B Show Figure 4AThe structure is shown in a cross-sectional view along the contact connector 429. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... 435, and an SGD transistor 436. Passages in the IPD layer 428 of the SGS and SGD transistors 431, 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be, for example, a stack of nitride (N) and oxide (O) in a NONON configuration.

[0100] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0101] Figure 5 An example block diagram of the sensing block SB1 in Figure 1 is shown. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and handled by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with the collection of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible approach, the voltage is provided to each sensing circuit independently, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include: reading latches 550b, 551b, 552b, and 553b associated with sensing circuits 550a, 551a, 552a, and 553a; setting bit values ​​in the latches; and providing voltage to set the precharge level in the sensing nodes of sensing circuits 550a, 551a, 552a, and 553a. Further example details of the sensing circuit controller 560 and sensing circuits 550a, 551a, 552a, and 553a are provided below.

[0102] In some embodiments, a memory cell may include a flag register containing a set of latches storing flag bits. In some embodiments, the value of the flag register may correspond to a value of data state. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the flag bits may modify associated logic of the device, such as an address decoding circuitry, to select a specific cell block. Batch operations (e.g., erase operations, etc.) may be performed using flags set in the flag register or a combination of the flag register and the address register, as in implicit addressing, or alternatively by direct addressing using the address register alone.

[0103] Figure 6A This is a perspective view of an assembly of blocks 600 in an example three-dimensional configuration of the memory array 126 of FIG1. ​​The substrate contains example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include voltage drivers 605 that can be connected to control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, control gate layers at a common height are driven in blocks BLK0, BLK1, BLK2, and BLK3. The substrate 601 may also carry the circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned along conductive paths to carry signals of the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in an intermediate region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned along conductive paths to carry signals of the circuitry. Each BLK0, BLK1, BLK2, BLK3 comprises a stacked region of memory cells, where alternating stacked levels represent word lines. In one possible approach, each BLK0, BLK1, BLK2, BLK3 has opposing layered sides, with vertical direct contacts extending upwards from said layered sides to the upper metal layer to form connections to conductive paths. While four BLK0, BLK1, BLK2, BLK3 blocks are shown as an example, two or more blocks extending in the x and / or y directions may be used.

[0104] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0105] Figure 6B Show Figure 6A An example cross-sectional view of a portion of one of blocks BLK0, BLK1, BLK2, and BLK3 is shown. The blocks comprise a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, a region of the stack 610 comprising NAND strings NS1 and NS2 is shown. Each NAND string encompasses memory vias 618 and 619, which are filled with material forming memory cells adjacent to the word lines. Region 622 of the stack 610 is shown... Figure 6D This will be shown in more detail below and discussed further in detail.

[0106] Stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of the source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be provided periodically across stack 610 as interconnects extending through stack 610 to connect source lines to specific contact lines above stack 610. Contact line connectors 617, 620 may be used during word line formation and subsequently filled with metal. A portion of bit line BL0 is also shown. Conductive via 621 connects drain terminal 615 to BL0.

[0107] Figure 6C Show Figure 6B A plot of the diameter of the memory holes in the stack. The vertical axis is perpendicular to... Figure 6B The stack alignment is shown and the width (wMH) of memory holes 618 and 619 is shown, for example, the diameter. Figure 6A Word line layers WLL0 to WLL10 are repeated as examples and are located at corresponding heights z0 to z10 in the stack. In this memory device, the memory vias etched through the stack have extremely high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, making the diameter slightly wider before gradually decreasing from the top to the bottom of the memory via.

[0108] Due to the non-uniformity of memory via width, the programming speed, which includes the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via, for example, based on the height of the memory cell in the stack. Using smaller diameter memory vias results in a relatively stronger electric field across the tunnel oxide, leading to relatively higher programming and erase speeds. One approach is to define a group of adjacent word lines with similar memory via diameters (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line within the group. Different groups can have different optimized verification schemes.

[0109] Figure 6D Show Figure 6B A close-up view of region 622 of stack 610. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cells MC. Several layers may be deposited, for example, along the sidewalls (SW) of memory via 630 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a pillar formed by material within memory via 630) may include a charge trapping layer or film 663 such as SiN or other nitrides, a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a barrier oxide / bulk high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are disposed within memory via 630. In other methods, some layers may be located within the control gate layer. Additional pillars are similarly formed within different memory vias. The pillars may form pillar-shaped active regions (AA) of the NAND string.

[0110] When the data memory cell MC is programmed, electrons are stored in a portion of the charge trapping layer 663 associated with the memory cell MC. These electrons are attracted from channel 665 into the charge trapping layer 663 and pass through the tunneling layer 664. The Vth of the memory cell MC increases proportionally to the amount of charge stored. During an erase operation, the electrons return to channel 665.

[0111] Each of the memory vias 630 may be filled with a plurality of annular layers, the annular layers including a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer 665. The core region of each of the memory vias 630 is filled with a host material, and the plurality of annular layers are located between the core region and the word line in each of the memory vias 630.

[0112] NAND strings can be viewed as having a floating body channel 665, since the length of channel 665 is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0113] Figure 7A A schematic plan view of a memory array 700 showing multiple memory vias 722 (which may be vertical memory cell strands as described herein) and multiple dummy vias 705 (which do not require a complete memory structure). Shallow trench etch or shallow etch feature (SHE) 710 extends through multiple word lines (e.g., five), but not completely through the chip to electrically isolate adjacent strings from each other. The SHE extends directly through the group of aligned dummy vias 705, thereby preventing those dummy vias 705 from storing data or otherwise functioning as memory cells.

[0114] For reference Figure 8A and 8B There are no fictitious holes. Unlike... Figure 7A and 7B In the memory structure 700, SHE810 is located in the gap between two adjacent rows of memory cell 825 and overlaps with memory hole 825, thereby creating a working strand with a trench etched down into at least one side of the SGD switch at the top of the working memory strand, shown here as memory hole 825. This configuration substantially improves yield and memory density because all memory holes 822, 825 are functional, i.e., fewer memory holes are wasted.

[0115] Unlike the fully circular memory hole 822, the memory hole 825 and SGD switch, which are partially cut by the SHE 810, have a semi-circular shape, which may be semi-circular or larger or smaller than a semi-circle. In some cases, the memory hole 825 and SGD switch may be smaller than a semi-circle on one side of the SHE 810 and larger than a semi-circle on the other side of the SHE 810.

[0116] Memory holes 822, 825 and multiple bit lines 830 (in Figure 8A The connections are marked as bit lines 0 to 7. For ease of illustration, only eight bit lines 830 are shown. Bit lines 830 extend above the memory holes and connect to the select memory holes via connection points. The memory holes in each string region also connect to the SGD switch at one end and to the SGS switch at the other end. The SHE trench 810 can be etched into a portion of the SGD switch.

[0117] For reference Figure 9Due to variations and defects in the manufacturing process, the SHE (Self-Electrical Helicopter) can be non-centered between adjacent rows of memory holes. When this occurs, the semi-circular SGD on one side of the SHE trench can be larger in size than the semi-circular SGD on the other side of the SHE trench. Memory holes containing larger SGDs are referred to below as "under-displaced SGDs," and memory holes containing smaller SGDs are referred to below as "over-displaced memory holes." As shown, each string has one row of under-displaced semi-circular SGDs, two rows of full-circular SGDs, and one row of over-displaced semi-circular SGDs. Referring to string 1, row 0 contains over-displaced semi-circular SGD 925b; rows 1 and 2 contain full-circular SGD 922; and row 3 contains under-displaced semi-circular SGD 925a.

[0118] Figure 10 A memory structure 1000, according to some described embodiments, is shown, exhibiting a plurality of memory holes cut by an SHE 1010. The memory structure 1000 includes a plurality of FC-SGD memory holes 1022 (representing a plurality of additional FC-SGDs) and a plurality of SC-SGD memory holes 1025a and 1025b (representing a plurality of additional SC-SGDs), wherein the SC-SGD memory holes 1025a and 1025b are cut by the SHE 1010. Additionally, the memory holes of the memory structure 1000 are surrounded by a metal layer 1032, such as a tungsten metal layer. During certain operations (e.g., a read operation), a bias voltage is applied to two regions (divided by the SHE 1010). For example, during a read option, a bias voltage is applied to region 1030a of the memory holes, making it possible to read the memory string connected to the memory holes in region 1030a. This region 1030a may be referred to as the selected SGD. However, at the same time, a bias voltage is applied to the unselected area 1030b of the memory hole. This area 1030b may be referred to as the unselected SGD.

[0119] SHE 1010 provides electrical isolation, thus separating regions 1030a and 1030b from each other. However, as shown in the enlarged view, SHE 1010 cuts out and removes portions of the SC-SGD, such as memory hole 1025b. For example, memory hole 1025b includes channel 1034 (used as a channel for electrons), charge trapping layer 1036 (used to store electrons and determine Vt), and dielectric layer 1038, such as aluminum oxide (used to block external electric fields). Additionally, oxide layer 1040 extends into memory hole 1025b, separating channel 1034 from charge trapping layer 1036, and also separating charge trapping layer 1036 from dielectric layer 1038. These aforementioned features—channel 1034, charge trapping layer 1036, and dielectric layer 1038—are found in both FC-SGD and SC-SGD.

[0120] In a fully circular memory via, the corresponding channel, charge trapping layer, and metal layer each resemble a ring. However, due to SHE 1010, portions of channel 1034, charge trapping layer 1036, and dielectric layer 1038 are partially removed. While the memory 1025b with this partially removed feature remains functional, it introduces certain problems. For example, due to the partial removal of dielectric layer 1038, both channel 1034 and charge trapping layer 1036 are exposed to electric field 1042 (indicated by arrows) due to the bias voltage placed on region 1030b (unselected SGD) during read operations. As a result, the end regions 1044a and 1044b (or tips) of channel 1034 can be substantially turned on during read operations, making end regions 1044a and 1044b conductive. A diagram of transistors (unlabeled) shows the gates of the turnable end regions 1044a and 1044b. This, in turn, effectively reduces the Vt of memory via 1025b required to turn on channel 1034. This illustrates an issue with NSI. Furthermore, it should be noted that memory hole 1025b typically indicates... Figure 10 Other SC-SGD memory holes in the SHE 1010. However, the degree to which each memory hole is cut by the SHE 1010 can vary.

[0121] Figure 11 A graph 1100 illustrates the Vt distribution of a memory structure with memory holes according to some of the described embodiments. The graph shows the count (program-erase cycle) versus Vt. Curve 1110a represents the Vt distribution for all SGD memory holes. Curve 1110b represents the Vt distribution for all FC-SGD memory holes, and curve 1110c represents the Vt distribution for all SC-SGD memory holes. In this respect, curves 1110b and 1110c represent components of curve 1110a. Curve 1110c shows that the Vt distribution will "shift down" or decrease the overall Vt distribution. Furthermore, the effect of SC-SGD widens curve 1110a (the overall curve), making the Vt distribution less predictable. Several modifications shown and described below are intended to overcome these challenges of using SC-SGD.

[0122] Figure 12 A circuit diagram 1200 is shown illustrating transistors for selected and unselected gates. As shown, transistor 1250a represents a selected SC-SGD memory hole, such as memory hole 1025b (shown in...). Figure 10 (in Chinese). To be precise, transistor 1250a refers to end regions 1044a and 1044b (shown in...). Figure 10 (Middle). Transistor 1250a is designed based on a predetermined gate selection voltage V. SELAnd it is turned on. Furthermore, transistor 1250b represents an unselected SC-SGD memory hole, such as memory hole 1025a (shown in...). Figure 10 (Middle). Additionally, transistor 1250c (parasitic transistor) is connected in parallel with transistor 1250a. Ideally, when V... SEL When the bias voltage is sufficiently high on transistor 1250a, the circuit carries current. However, when a bias voltage is applied to transistor 1250b (e.g., during a read operation), an electric field 1242, known as NSI, can turn on transistor 1250c. When this occurs, leakage current is passed to the source, causing the sense amplifier 1260 to determine that transistor 1250a is positively conducting when transistor 1250a is not turned on, while transistor 1250c, acting as a parasitic transistor, is positively conducting.

[0123] The equation determining whether electric field 1242 is sufficient to turn on transistor 1250c can be determined by the following:

[0124] V oD =α*V ATTACKER -V SELSRC Equation (1)

[0125] Where V OD The overdrive voltage is given by α, the coupling factor (based on the width of the SHE, which will be further described below), and V. ATTACKER The "attack" or interference voltage caused by NSI, and V SELSRC This is the source line voltage. V ATTACKER It is also based on the voltage obtained attributable to the bias voltage applied to the unselected gate. Therefore, V OD Similar to traditional transistor formulas, such as gate-source voltage (“V”). GS Furthermore, it can be seen that V OD Depends on V ATTACKER And it is proportional to it (assuming α is greater than 0). Therefore, when V OD When the voltage is high enough, transistor 1250c will turn on, which corresponds to V. ATTACKER High enough.

[0126] In order to fully reduce V OD Turning on the transistor allows control of V. ATTACKER To sufficiently reduce the electric field 1242. For example, by placing a negative bias of, for instance, -2V on an unselected gate, the voltage induced on transistor 1250c by the electric field can be sufficiently reduced (in some cases, reduced to 0V). As a result, transistor 1250c does not turn on unintentionally, and only turns on at V SEL Sufficiently high voltages allow current to flow through the 1250A transistor. To provide negative voltages, additional modifications, such as a tri-well transistor, can be used.

[0127] Figure 13 A memory structure 1300, illustrated according to some described embodiments, is shown with a plurality of memory holes cut by an SHE 1310, further illustrating process variations within the SHE 1310. As shown, the SHE 1310 is divided into different segments representing different process variations. For example, segment 1320a represents a portion of the SHE 1310. Segment 1320a is generally similar to the previous embodiments shown and described with respect to the SHE, and may also represent a target or ideal cut portion in terms of width 1312 and the location desired by the fabrication of the memory structure 1300. However, other segments may unintentionally have variations, partly due to the operations that form the SHE 1310. For example, segment 1320b of the SHE 1310 contains a width similar to or generally similar to the width 1312 in segment 1320a, but offset or shifted relative to segment 1320a. Furthermore, segment 1320c of SHE 1310 is aligned or substantially aligned with segment 1320a, but includes a width greater than 1312. Although not shown, other segments may include a width less than 1312.

[0128] Due to process variations, NSI will change. For example, the SHE 1310 providing electrical isolation may provide relatively less isolation at the location corresponding to segment 1320a compared to segment 1320c. Referring to equation (1), the coupling factor α may be inversely proportional to the width of the SHE. Furthermore, since the width 1312 is smaller than the width of segment 1320c, the coupling factor α at segment 1320a may be larger than that at segment 1320c. Therefore, V... OD The offset can be larger at segment 1320a. Furthermore, the offset relationship between segment 1320a and segment 1320b can result in varying degrees of cutting of the corresponding SC-SGD memory apertures at locations corresponding to segments 1320a and 1320b. In this respect, the amount of material removed from certain features of the memory aperture (e.g., channels, charge trapping layers, and dielectric layers) can be varied, and therefore the NSI can be altered.

[0129] Figure 14A graph 1400 illustrates the differences in Vt of memory holes based on NSI magnitudes according to some of the described embodiments. As shown, curve 1410a represents the Vt distribution for all FC-SGD memory holes, and curve 1410b represents the Vt distribution for all SC-SGD memory holes. Additionally, several arrows are shown and indicate the relative degree to which the Vt of the memory holes will shift downward based on NSI. For example, arrow 1414a represents the downward shift of Vt for SC-SGDs exposed to a relatively low level of NSI, while arrow 1414b represents the downward shift of Vt for SC-SGDs exposed to a relatively high level of NSI. However, by providing a negative bias on an unselected gate of the memory structure (described above), the downward shift can be managed, and curve 1410b can better resemble (i.e., overlap) curve 1410a. While negative bias provides some improvement, other techniques can be combined and will be discussed below.

[0130] Figures 15A to 15C The SC-SGD memory aperture exposed to NSI is shown and described, along with additional modifications to mitigate the associated effects of NSI. Furthermore, Figures 15A to 15C The document demonstrates and describes memory ports accessed for various purposes (e.g., verification, programming, and reading). Furthermore, Figures 15A to 15C The techniques shown and described herein can be used with NSI for various purposes. The SC-SGD memory port 1525 may include several features shown and described for SC-SGD memory ports (see, for example, [example]). Figure 10 Examples include channel 1534 (containing end regions 1544a and 1544b or tips), charge trapping layer 1536, and dielectric layer 1538.

[0131] Figure 15A The SC-SGD memory hole 1525 exposed to NSI during verification operation is shown. As shown, the SC-SGD memory hole 1525 is exposed to an electric field 1542 (indicated by the arrow), thereby generating NSI. During verification operation, verification pulses (periodically) are sent to the SC-SGD memory hole 1525 to determine whether the SC-SGD memory hole 1525 is programmed to the desired Vt. The extent to which end regions 1544a and 1544b can be opened during verification operation can be controlled by modifying (i.e., increasing) the electric field 1542, which can be attributed in part to the SHE width 1512 or other characteristics. Conversely, when the electric field 1542 is relatively weak (i.e., lower), the verification operation can determine that the SC-SGD memory hole 1525 is programmed to the desired Vt because the electric field 1542 (when weaker) does not lower Vt. As a result, the SC-SGD memory hole 1525 can "self-compensate" and react in the desired manner based on NSI.

[0132] Figure 15BThe SC-SGD memory hole 1525 exposed to NSI during programming operations is shown. Due to the Vt shift of the SC-SGD memory hole 1525 (described above generally with respect to the memory hole), the verification operation can initially fail, thereby affecting the controller of the memory structure ( Figure 15B (Not shown) provides one or more additional program pulses, thereby providing more electrons to the charge trapping layer 1536 and programming the SC-SGD memory hole 1525 to a higher Vt. This higher programmed Vt of the SC-SGD memory hole 1525 can more closely resemble the Vt distribution of the FC-SGD (e.g., Figure 14 (Curve 1410a in the figure). As a result, the SC-SGD memory hole 1525 can be "self-compensated" and programmed to the desired Vt, such as the Vt of the FC-SGD.

[0133] Figure 15C The SC-SGD memory aperture 1525 is shown during a read operation. After the programming operation, the charge trapping layer 1536 carries a sufficient number of electrons for self-compensation. For example, during sensing, when the electric field 1542 is relatively weak or even negative, the SC-SGD memory aperture 1525 will remain off due to the additional electrons (i.e., no current leakage attributable to parasitic transistors).

[0134] Figure 16 A flowchart 1600 illustrating a method for programming a memory structure according to some of the described embodiments is shown. At step 1602, the data word line (“WL”) procedure begins. At step 1604, a bias voltage (V) is applied to the selected SGD. SGD In some embodiments, V SGD Approximately 3V. At step 1606, the negative bias voltage (V) is... NEG_PGM A program pulse is applied to the unselected SGD. At step 1608, a program pulse is applied to the data WL. The selected SGD can then be used to access the data WL. At step 1610, a bias voltage (V) is applied to the selected SGD. SG_PVFY At step 1612, the negative bias voltage (V) is applied. NEG_PGM An additional or ramped programming voltage (ΔV) is applied to the unselected SGD. At step 1614, a verification operation occurs. At step 1616, a decision is made regarding whether to verify the threshold voltage Vt. If the threshold voltage Vt is verified to be at the desired Vt, the verification operation completes and the flowchart proceeds to step 1618. If the threshold voltage Vt is not verified to be at the desired Vt, the flowchart proceeds to step 1620. At step 1620, an additional or ramped programming voltage (ΔV) is applied. PGM Add to the previously programmed voltage (V) PGM The flowchart proceeds to step 1604, where an increased bias voltage (V) can be applied to the selected SGD.SGD ).

[0135] Figure 17 A flowchart 1700 illustrating a method for reading from a memory structure according to some described embodiments is shown. At step 1702, a read command is initiated. At step 1704, a bias voltage (V) is applied... SGD_READ A negative bias voltage (V) is applied to the selected SGD. At step 1706, the negative bias voltage (V) is applied. NEG_READ An unselected SGD is applied. At step 1708, the memory structure is sensed. This may include, for example, reading data from a memory string controlled by a selected SGD.

[0136] Figure 18 A flowchart 1800 illustrates an alternative method for programming a memory structure according to some of the described embodiments. At step 1802, the SGD program begins. At step 1804, a programming voltage (V) is applied to the selected SGD. PGM At step 1806, the positive bias voltage (V) is applied. NSI_PVFY A positive bias voltage (V) is applied to an unselected SGD. NSI_PVFY V can be formed by applying it to a selected SGD. ATTACKER (As discussed above). At step 1808, a verification bias is applied to the selected SGD. At step 1810, a decision is made as to whether to verify the threshold voltage Vt. If the threshold voltage Vt is verified to be at the desired Vt, the verification operation is complete and the flowchart proceeds to step 1812. If the threshold voltage Vt is not verified to be at the desired Vt, the flowchart proceeds to step 1814. At step 1814, the passed (verified) cells (SC-SGDs) are suppressed on the bit line (“BL”), and the remaining cells (SC-SGDs) are programmed at 0V on BL. At step 1816, an additional or ramped programming voltage (ΔV) is applied. PGM Add to the previously programmed voltage (V) PGM The flowchart proceeds to step 1804, where the programming voltage (V) is... PGM Increase and apply to the selected SGD.

[0137] Figure 19 A flowchart 1900 illustrates an alternative method for reading from a memory structure according to some of the described embodiments. At step 1902, the voltage (V) is... NSI_READ The voltage applied during the read operation (V) is applied to an unselected SGD. NSI_READ The applied voltage during read operations or other operations can be 0V or a negative voltage (e.g., -2V). Consequently, the applied voltage (V) during read operations... NSI_READ The applied voltage during (or other operations) is less than that in step 1806 (in Figure 18 The positive bias voltage (V) of the middle) NSI_PVFY At step 1904, the bias voltage (V) will be verified. CG Apply to the selected SGD.

[0138] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once fully understanding the above disclosure, those skilled in the art will recognize many variations and modifications that can be made without departing from the scope of this disclosure, subject only to any practical limitations relating to the materials and physical principles of the described apparatus. It is intended that the appended claims be construed as covering all such variations and modifications.

Claims

1. A method for accessing a memory device, the method comprising: During sensing operation, a first voltage is used to bias a first semi-circular drain-side selected gate (SC-SGD), wherein the first SC-SGD is located on a first edge of the etched region; and During the sensing operation, a second SC-SGD is biased using a second voltage less than the first voltage, wherein the second SC-SGD is located on a second edge of the etched area opposite to the first edge.

2. The method of claim 1, wherein the second voltage includes a negative voltage.

3. The method according to claim 2, wherein the negative voltage is less than zero volts.

4. The method of claim 2, wherein the etched area includes a shallow hole etching (SHE) cut.

5. The method of claim 4, wherein the selected negative voltage is based on the width of the SHE cut portion.

6. The method of claim 1, wherein, During the programming operation, the method further includes: The program pulses are supplied to the data word lines of the memory device; The first SC-SGD is biased using a verification voltage, wherein the first SC-SGD is programmed during the programming operation; and The second SC-SGD is biased using a negative verification voltage.

7. The method according to claim 1, wherein, During the read operation, the method further includes: Use the first SC-SGD to select the string to be read; The first SC-SGD is biased using the read voltage; and The second SC-SGD is biased using a negative read voltage.

8. A memory system comprising: Memory devices; as well as A controller, operably coupled to the memory device, is configured to: During sensing operation, a first voltage is used to bias a first semi-circular drain-side selected gate (SC-SGD), wherein the first SC-SGD is located on a first edge of the etched region; and During the sensing operation, a second SC-SGD is biased using a second voltage less than the first voltage, wherein the second SC-SGD is located on a second edge of the etched area opposite to the first edge.

9. The memory system of claim 8, wherein the second voltage includes a negative voltage.

10. The memory system of claim 9, wherein the negative voltage is less than zero volts.

11. The memory system of claim 9, wherein the etched area includes a shallow hole etch (SHE) cut.

12. The memory system of claim 11, wherein the selected negative voltage is based on the width of the SHE cut portion.

13. The memory system according to claim 8, wherein, During programming operations, the controller is further configured to: The program pulses are supplied to the data word lines of the memory device; The first SC-SGD is biased using a verification voltage, wherein the first SC-SGD is programmed during the programming operation; as well as The second SC-SGD is biased using a negative verification voltage.

14. The memory system according to claim 8, wherein, During the read operation, the controller is further configured to: Use the first SC-SGD to select the string to be read; The first SC-SGD is biased using the read voltage; and The second SC-SGD is biased using a negative read voltage.

15. A non-transitory computer-readable storage medium configured to store instructions that, when executed by a processor comprising a controller of a memory system, cause the memory system to perform the following steps: During sensing operation, a first voltage is used to bias a first semi-circular drain-side selected gate (SC-SGD), wherein the first SC-SGD is located on a first edge of the etched region; and During the sensing operation, a second SC-SGD is biased using a second voltage less than the first voltage, wherein the second SC-SGD is located on a second edge of the etched area opposite to the first edge.

16. The non-transitory computer-readable storage medium of claim 15, wherein the second voltage comprises a negative voltage of less than zero volts.

17. The non-transitory computer-readable storage medium of claim 16, wherein the etched area includes a shallow hole etch (SHE) cut.

18. The non-transitory computer-readable storage medium of claim 17, wherein the selected negative voltage is based on the width of the SHE cut portion.

19. The non-transitory computer-readable storage medium of claim 15, wherein the controller is further configured to perform the following steps: Provide program pulses to the data word lines of the memory device; The first SC-SGD is biased using a verification voltage, wherein the first SC-SGD is programmed during a programming operation; and The second SC-SGD is biased using a negative verification voltage.

20. The non-transitory computer-readable storage medium of claim 15, wherein the controller is further configured to perform the following steps: Use the first SC-SGD to select the string to be read; The first SC-SGD is biased using the read voltage; and The second SC-SGD is biased using a negative read voltage.

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