Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The semiconductor structure includes a substrate, a gate structure on the substrate, the gate structure extending along a first direction, and a plurality of support patterns in the gate structure, the plurality of support patterns being separated from each other and arranged along a second direction, the second direction being perpendicular to the first direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing processes, and in particular to a gate comprising a support pattern and a method thereof, which can avoid the dishing phenomenon during gate manufacturing. Background Technology

[0002] In semiconductor manufacturing processes, planarization is frequently used to remove portions of the material layer, resulting in a planar surface for the device. However, when there is a significant density difference between the device area and its surrounding area, planarization steps (such as chemical mechanical polishing, CMP) can lead to a situation where the removal rates of densely packed areas (often called dense regions) and loosely packed areas (often called iso regions) differ. This can result in more polishing being applied to the top of a specific area or device (usually a region with lower device density), creating a concave profile. This phenomenon is known as dishing.

[0003] The aforementioned dish-shaped depression phenomenon may adversely affect the quality of components, therefore, solutions need to be found to overcome this problem. Summary of the Invention

[0004] The present invention provides a semiconductor structure comprising a substrate, a gate structure located on the substrate and extending along a first direction, and a plurality of support patterns located within the gate structure, wherein the plurality of support patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction.

[0005] The present invention also provides a method for forming a semiconductor structure, comprising providing a substrate, forming a gate structure on the substrate and the gate structure extending along a first direction, and forming a plurality of support patterns within the gate structure, wherein the plurality of support patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction.

[0006] The present invention is characterized by forming multiple support patterns in the gate to avoid the problem of a depression at the top of the gate during the gate planarization step. Furthermore, the arrangement direction of the support patterns in the present invention is parallel to the current direction (i.e., the direction from the source to the drain), thus minimizing obstruction to the current flow path and resulting in better gate electrical performance. Attached Figure Description

[0007] Figures 1 to 2 This is a top view schematic diagram of a semiconductor element according to an embodiment of the present invention;

[0008] Figures 3 to 4 This is a top view schematic diagram of a semiconductor element according to another embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 10: Base

[0011] 12: Sacrificial Gate

[0012] 14: Supporting pattern

[0013] 14A: Supporting Pattern

[0014] 15: Supporting pattern dotted lines

[0015] 16: Metal gate

[0016] 18: Contact Structure

[0017] I: Current direction

[0018] G: Gate

[0019] D: Drain electrode

[0020] S: Source

[0021] D1: First Direction

[0022] D2: Second Direction Detailed Implementation

[0023] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.

[0024] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0025] Figures 1 to 2 A top view schematic diagram illustrating a semiconductor device according to an embodiment of the present invention is shown. Figure 1 As shown, firstly, a substrate 10 is provided, such as a silicon substrate, and a sacrificial gate 12 (or gate G) is formed on the substrate 10. The sacrificial gate 12 is, for example, made of polysilicon. In subsequent steps, source / drain regions and dielectric layers (not shown) are formed on both sides of the sacrificial gate 12. Then, planarization and etching steps are performed sequentially. After removing the sacrificial gate 12, it is replaced with a gate made of metal or other materials. This will be described in more detail in the next paragraph.

[0026] After sacrificing gate 12 is completed, then as follows Figure 2As shown, the source S and drain D are defined on both sides of the sacrificial gate 12 by means such as ion implantation. A first direction D1 and a second direction D2 are defined here, wherein the first direction D1 is parallel to the extension direction of the sacrificial gate 12, and the second direction D2 is perpendicular to the first direction. The gate G, source S and drain D can form a transistor, wherein the current direction I of the transistor flows from the source S to the drain D, and the second direction D2 is parallel to the current direction I.

[0027] In subsequent steps, a dielectric layer (not shown) is first formed around the sacrificial gate 12 to cover it. Then, a planarization step (e.g., chemical mechanical polishing, CMP) is performed to remove excess dielectric layer, aligning the top surface of the dielectric layer with the top surface of the sacrificial gate 12 and exposing the top surface of the sacrificial gate 12. Next, an etching step is performed to remove the sacrificial gate 12, and then another material layer (e.g., a high-k metal layer) is filled in to form a new metal gate (not shown) at the original location of the sacrificial gate 12. However, during the planarization step, the top surface of the gate may experience a dishing phenomenon as described in the prior art. Therefore, to avoid this problem, this invention includes forming multiple support patterns 14 within the sacrificial gate 12 after its completion. The material of the support patterns 14 is, for example, an insulating material such as silicon oxide. The method of forming the support pattern 14 includes, for example, performing a patterning etching step after the sacrificial gate 12 is completed to form some grooves in the sacrificial gate (corresponding to the shape of the final support pattern), and then filling the grooves at the same time as filling the dielectric layer around the sacrificial gate 12, so that the dielectric layer (not shown) around the sacrificial gate 12 and the support pattern 14 located in the sacrificial gate 12 can be formed at the same time.

[0028] In this embodiment, the support pattern 14 presents a grid-like shape, meaning that the support pattern 14 contains multiple lines, some of which extend along the first direction D1 and others along the second direction D2. However, the applicant's experimental results show that although forming the support pattern 14 can indeed reduce the probability of dish-shaped depressions, if the support pattern 14 contains line patterns parallel to the first direction D1 (that is, perpendicular to the current direction I), it will hinder the current transmission effect within the gate. In other words, this will significantly reduce the current conduction efficiency of the gate, which is detrimental to the electrical performance of the gate.

[0029] Figures 3 to 4 A top view schematic diagram illustrating a semiconductor element according to another embodiment of the present invention is shown. To further improve the above problems, in another embodiment of the present invention, as... Figure 3 and Figure 4As shown, in this embodiment, the shape of the support pattern is changed, and the original support pattern 14 is replaced by support pattern 14A. The main difference between support pattern 14A and support pattern 14 is that the pattern arranged in support pattern 14A does not obstruct the current direction I. More specifically, support pattern 14A constitutes multiple support pattern dashed lines 15 arranged along the second direction D2, and in the gaps between adjacent support pattern dashed lines 15, gate material remains and no support pattern 14A is formed. Therefore, multiple support patterns 14A do not block the main current flow path (current direction I) of the transistor. Thus, compared to the above embodiment, this embodiment has a smaller impact on the electrical properties of the gate even if support pattern 14A is formed inside the gate.

[0030] Subsequently, such as Figure 4 As shown, the sacrificial gate 12 is removed by an etching step (not shown), leaving each support pattern 14A. Then, a metal layer, such as a high-k metal layer, is refilled into the groove of the original sacrificial gate 12 to form a metal gate 16. This step is also known as a replacement metalgate (RMG) fabrication process, which is prior art and will not be described in detail here. Furthermore, after the metal gate 16 is completed, multiple contact structures 18 can be formed on the metal gate 12 and the source (S) / drain (D). The contact structures 18 can electrically connect the transistor to other electronic components. The fabrication process of the contact structures 18 is also prior art and will not be described in detail here.

[0031] Based on the above description and figures, the present invention provides a semiconductor structure comprising a substrate 10, a metal gate 16 located on the substrate 10 and extending along a first direction D1, and a plurality of support patterns 14A located within the metal gate 16, wherein the plurality of support patterns 14A are separated from each other and arranged along a second direction D2, wherein the second direction D2 is perpendicular to the first direction D1.

[0032] In some embodiments of the present invention, a source S and a drain D are respectively located on both sides of the metal gate 16.

[0033] In some embodiments of the present invention, the line connecting the source S and the drain D is parallel to the second direction D2.

[0034] In some embodiments of the present invention, a plurality of support patterns 14A form a plurality of support pattern dashed lines 15, wherein each support pattern dashed line 15 extends along a second direction D2.

[0035] In some embodiments of the present invention, the material of the support pattern 14A comprises silicon oxide.

[0036] In some embodiments of the present invention, the metal gate 16 is made of a metal with a high dielectric constant.

[0037] The present invention also provides a method for forming a semiconductor structure, comprising providing a substrate 10, forming a metal gate 16 on the substrate 10, wherein the metal gate 16 extends along a first direction D1, and forming a plurality of support patterns 14A within the metal gate 16, wherein the plurality of support patterns 14A are separated from each other and arranged along a second direction D2, wherein the second direction D2 is perpendicular to the first direction.

[0038] In some embodiments of the present invention, the method of forming a support pattern 14A in a metal gate 16 includes: forming a sacrificial gate 12 on a substrate 10; performing an etching step on the sacrificial gate 12 to form a plurality of holes in the sacrificial gate 12; filling an insulating layer next to the sacrificial gate and filling the holes; performing a planarization step to remove part of the insulating layer and expose the surface of the sacrificial gate 12; removing the sacrificial gate layer and leaving the insulating layers; defining a gate trench; and forming a high dielectric constant metal layer in the gate trench.

[0039] The present invention is characterized by forming multiple support patterns in the gate to avoid the problem of a depression at the top of the gate during the gate planarization step. Furthermore, the arrangement direction of the support patterns in the present invention is parallel to the current direction (i.e., the direction from the source to the drain), thus minimizing obstruction to the current flow path and resulting in better gate electrical performance.

[0040] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising: Base; A gate structure is located on the substrate and extends along a first direction; Multiple support patterns, located within the gate structure and not extending beyond the gate structure, wherein the multiple support patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction; and The source and drain are located on opposite sides of the gate structure, and the line connecting the source and drain is parallel to the second direction.

2. The semiconductor structure of claim 1, wherein the plurality of support patterns form a plurality of support pattern dashed lines, wherein each support pattern dashed line extends along the second direction.

3. The semiconductor structure of claim 1, wherein the material of the support pattern comprises silicon oxide.

4. The semiconductor structure of claim 1, wherein the gate structure is made of a metal with a high dielectric constant.

5. A method for forming a semiconductor structure, comprising: Provide a base; A gate structure is formed on the substrate, and the gate structure extends along a first direction; as well as Multiple support patterns are formed within the gate structure and do not extend out of the gate structure, wherein the multiple support patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction; A source and a drain are formed, located on opposite sides of the gate structure, wherein the line connecting the source and the drain is parallel to the second direction.

6. The forming method of claim 5, wherein the method of forming the support pattern in the gate structure comprises: A sacrificial gate is formed on the substrate; An etching step is performed on the sacrificial gate to form multiple holes in it; An insulating layer is filled around the sacrificial gate and into the holes; A planarization step is performed to remove part of the insulating layer and expose the surface of the sacrificial gate; Remove the sacrificial gate layer, leaving the insulating layers, and define the gate slots; as well as A high dielectric constant metal layer is formed in the gate slot.

7. The forming method of claim 5, wherein the plurality of support patterns constitute a plurality of support pattern dashed lines, wherein each support pattern dashed line extends along the second direction.

8. The forming method of claim 5, wherein the material of the support pattern comprises silicon oxide.

9. The forming method of claim 5, wherein the gate structure is made of a metal with a high dielectric constant.

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