Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present invention provides a semiconductor structure and a manufacturing method thereof, which are applied to the field of semiconductor technology. Specifically, in the manufacturing method provided by the present invention, by increasing the etching time of the active region, the depth of the local oxidation of silicon (LOCOS) isolation structure in the semiconductor substrate is deepened. Therefore, when forming the trench for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will occur. Thus, the obtained LOCOS structure can have a greater depth, and it is required that the formed LOCOS depth is greater than the junction depth of N+ and P+ of the NPN, and at the same time, the impact on the manufacturing process of the NPN device structure is small. That is, without increasing the production cost, the problem of unstable beta parameter of the NPN device structure caused by metal plug etching fluctuations can be avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The BCD process is a monolithic integrated process technology, which was successfully developed by STMicroelectronics (ST) in 1986. This technology can produce bipolar junction transistors (Bipolar Junction Transistor), CMOS and DMOS devices on the same chip. The BCD process not only combines the advantages of high transconductance and strong load driving capability of bipolar devices and high integration and low power consumption of CMOS, but also integrates DMOS power devices with fast switching speed. Since DMOS has the characteristics of high speed and high current capability at the same time, the withstand voltage is usually high. Therefore, the power management chip manufactured by the BCD process can work under high frequency, high voltage and high current, which is an ideal process for manufacturing high-performance power chips. The monolithic integrated chip manufactured by the BCD process can also improve system performance, save circuit packaging costs, and have better reliability. The main application areas of the BCD process are power management (power and battery control), display drive, automotive electronics, industrial control and other fields. As the application field of the BCD process continues to expand, the requirements for the BCD process are getting higher and higher. Recently, the BCD process has mainly developed in the direction of high voltage, high power and high density.

[0003] Figure 1 This is a schematic diagram of the structure of the NPN device (bipolar transistor) in the current BCD process. Figure 1 It can be seen that beta of the NPN device structure is Ic / Ib, and the Ib current path is mainly Figure 1 In the actual process, the depth of CT etching will have normal fluctuations or in-plane distribution. When the CT etching depth is shallower, most of the Ib current is the A path current. When the CT etching depth is deeper, CT is closer to the bottom of the Emitter junction, and most of the Ib current is the D path current. Because the PW concentration flowing through D is lighter than that flowing through A, the beta dominated by the D path is larger than the beta dominated by the A path, which leads to the instability of the beta of the NPN device structure. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem of beta instability of the NPN device structure caused by the fluctuation of CT etching depth in the NPN device structure in the prior art.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, comprising at least the following steps:

[0006] Providing a semiconductor substrate, wherein a first deep well is formed in the semiconductor substrate, and an oxide layer, a nitride layer and a hard mask layer stacked in sequence are formed on the surface of the semiconductor substrate;

[0007] Using the hard mask layer as a mask, etching the nitride layer, the oxide layer and a portion of the thickness of the semiconductor substrate, so as to form a plurality of discrete stacked structures consisting of the etched nitride layer and the oxide layer, and at the same time, forming a plurality of trenches in the semiconductor substrate between adjacent stacked structures;

[0008] Forming a field oxygen isolation structure in each of the trenches, and performing ion implantation on the semiconductor substrate between two adjacent field oxygen isolation structures to form a collector, a base and an emitter of an NPN structure;

[0009] Metal plugs are formed respectively for electrically connecting the collector, base and emitter of the NPN structure, wherein the depth of the metal plugs inserted into the semiconductor substrate corresponding to the collector, base and emitter is less than the depth of the field oxygen isolation structure in the semiconductor substrate.

[0010] Furthermore, the oxide layer may be silicon dioxide, and the nitride layer may be silicon nitride.

[0011] Furthermore, the depth range of the groove can be

[0012] Furthermore, the depth range of the field oxygen isolation structure in the direction perpendicular to the semiconductor substrate can be

[0013] Furthermore, after forming the field oxygen isolation structure and before forming the collector, base and emitter of the NPN structure, the method may further include:

[0014] forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers a portion of the top surface of the semiconductor substrate corresponding to the first deep well;

[0015] Using the sacrificial oxide layer as a mask, an ion implantation process is performed on the semiconductor substrate not covered by the sacrificial oxide layer to form a second deep well in the first deep well.

[0016] Further, the first deep well may be an N-type well, and the second deep well may be a P-type well.

[0017] Furthermore, after forming the second deep well, the method may further include: performing a rapid thermal annealing process on the semiconductor substrate, and removing the sacrificial oxide layer by a wet etching process.

[0018] Furthermore, the thickness of the sacrificial oxide layer can be

[0019] Furthermore, the steps of forming the collector, base and emitter of the NPN structure may include:

[0020] Performing N-type ion implantation on the surface of the portion of the semiconductor substrate corresponding to the second deep well to form an emitter of an NPN structure in the portion of the semiconductor substrate corresponding to the second deep well;

[0021] Performing P-type ion implantation again on the surface of the remaining semiconductor substrate corresponding to the second deep well to form a base of an NPN structure located on both sides of the emitter in the remaining semiconductor substrate corresponding to the second deep well; and

[0022] N-type ion implantation is further performed on the semiconductor substrate of the first deep well except the second deep well, so as to form a collector of the NPN structure in the semiconductor substrate corresponding to the first deep well.

[0023] Furthermore, the junction depth of the ion implantation region corresponding to the emitter and the base of the NPN structure formed in the semiconductor substrate needs to be smaller than the depth of the field oxygen isolation structure in the direction perpendicular to the semiconductor substrate.

[0024] In a second aspect, based on the same inventive concept, the present invention further provides an NPN device structure, which can be specifically prepared by the manufacturing method of the semiconductor structure as described above.

[0025] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0026] In the manufacturing method of the semiconductor structure provided by the present invention, the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure are separated by a field oxygen isolation structure LOCOS, and the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is required to be deeper than the depth of the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure in the semiconductor substrate. In this way, the current path of path A can be eliminated, that is, a larger beta can be obtained, and the change of the beta parameter of the NPN structure caused by the change of the etching depth of the metal plug can be avoided, that is, the beta parameter of the NPN structure is stabilized.

[0027] Furthermore, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active area. Therefore, when forming the groove for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of N+ and P+ of NPN, and at the same time, the impact on the manufacturing process of the NPN device structure is small, that is, while not increasing the production cost, the problem of unstable beta parameters of the NPN device structure caused by metal plug etching fluctuations is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of the NPN device structure (bipolar transistor) in the current BCD process;

[0029] Figure 2 is a flow chart of a method for manufacturing a semiconductor structure in one embodiment of the present invention;

[0030] Figure 3a to Figure 3d A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided in an embodiment of the present invention;

[0031] The reference numerals are as follows:

[0032] 100-semiconductor substrate; 110-oxide layer;

[0033] 120-nitride layer; 130-hard mask layer;

[0034] 140-metal plug; NDW-first deep well;

[0035] Pwell- The second deepest well. DETAILED DESCRIPTION

[0036] As described in the background technology, currently, in the actual process, the depth of CT etching will have normal fluctuations or in-plane distribution. When the CT etching depth is shallower, most of the Ib current is the A path current. When the CT etching depth is deeper, CT is closer to the bottom of the Emitter junction, and most of the Ib current is the D path current. Because the PW concentration flowing through D is weaker than the PW concentration flowing through A, the beta dominated by the D path is larger than the beta dominated by the A path, which leads to the problem of unstable beta of the NPN device structure.

[0037] Based on this, the present invention provides a semiconductor structure and a manufacturing method thereof to solve the problem of beta instability of the NPN device structure caused by CT etching depth fluctuation in the NPN device structure in the prior art.

[0038] For example, reference Figure 2 As shown, the method for manufacturing a semiconductor structure provided by the present invention at least comprises the following steps:

[0039] Step S100, providing a semiconductor substrate, wherein a first deep well is formed in the semiconductor substrate, and an oxide layer, a nitride layer and a hard mask layer stacked in sequence are formed on the surface of the semiconductor substrate;

[0040] Step S200, using the hard mask layer as a mask, etching the nitride layer, the oxide layer and a portion of the thickness of the semiconductor substrate, so as to form a plurality of discrete stacked structures consisting of the etched nitride layer and the oxide layer, and at the same time, forming a plurality of trenches in the semiconductor substrate between adjacent stacked structures;

[0041] Step S300, forming a field oxygen isolation structure in each of the trenches, and performing ion implantation on the semiconductor substrate between two adjacent field oxygen isolation structures to form a collector, a base and an emitter of an NPN structure;

[0042] Step S400, forming metal plugs for electrically connecting the collector, base and emitter of the NPN structure respectively, wherein the depth of the metal plugs inserted into the semiconductor substrate corresponding to the collector, base and emitter is less than the depth of the field oxygen isolation structure in the semiconductor substrate.

[0043] That is, in the manufacturing method of the semiconductor structure provided by the present invention, the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure are separated by the field oxygen isolation structure LOCOS, and the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is required to be deeper than the depth of the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure in the semiconductor substrate. In this way, the current path of path A can be eliminated, that is, a larger beta can be obtained, and the change of the beta parameter of the NPN structure caused by the change of the etching depth of the metal plug can be avoided, that is, the beta parameter of the NPN structure is stabilized. Furthermore, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active area. Therefore, when forming the groove for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of N+ and P+ of NPN, and at the same time, the impact on the manufacturing process of the NPN device structure is small, that is, while not increasing the production cost, the problem of unstable beta parameters of the NPN device structure caused by metal plug etching fluctuations is avoided.

[0044] The semiconductor structure and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0045] As shown in this application and the claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional spatial dimensions of length, width and depth should be included.

[0046] Figure 3a to Figure 3d Schematic diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0047] In step S100, refer to Figure 3a As shown, a semiconductor substrate 100 is provided, wherein a first deep well DNW is formed in the semiconductor substrate 100, and an oxide layer 110, a nitride layer 120 and a hard mask layer 130 are stacked in sequence on the surface of the semiconductor substrate 100. The semiconductor substrate 100 may be a silicon-on-insulator substrate SOI, which has a bottom semiconductor layer (not shown), an insulating buried layer (not shown) and a top semiconductor layer (not shown) stacked in sequence from bottom to top, and the materials of the bottom semiconductor layer and the top semiconductor layer may be silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or at least one of other III / V compound semiconductors, and the material of the insulating buried layer may include silicon dioxide. Exemplarily, in an embodiment of the present invention, the semiconductor substrate 100 is a conductive silicon substrate. The oxide layer 110 may be silicon dioxide, the nitride layer 120 may be silicon nitride, and the hard mask layer 130 may be a photoresist layer.

[0048] In this embodiment, a semiconductor substrate 100 whose substrate material is a silicon substrate can be provided first, and P-type ion implantation can be performed on the semiconductor substrate 100 to form a P-type doped silicon substrate 100; then, a photoresist layer (not shown) is formed on both sides of the silicon substrate 100 (or referred to as the semiconductor substrate 100) to expose the surface of the middle part of the silicon P-type doped silicon substrate 100, and then N-type ion implantation is performed on the middle part of the P-type doped silicon substrate 100 by using an ion implantation process, and then after high-temperature well driving, an N-high resistance region is formed, that is, as shown in FIG. Figure 3a The first deep well DNW is shown.

[0049] In step S200, refer to Figure 3b As shown, the nitride layer 110, the oxide layer 120 and a partial thickness of the semiconductor substrate 100 are etched using the hard mask layer 130 as a mask, so as to form a plurality of discrete stacked structures 251 composed of the etched nitride layer 110 and the oxide layer 120, and at the same time, a plurality of grooves 101 are formed in the semiconductor substrate 100 between adjacent stacked structures 251.

[0050] In this embodiment, after performing the above step S100, a silicon dioxide layer, a silicon nitride layer and a photoresist layer may be sequentially deposited on the surface of the semiconductor substrate 100, and then the photoresist layer is used as a mask to perform vertical etching downward in a direction perpendicular to the surface of the semiconductor substrate 100, for example, by a wet etching process, so as to form a silicon dioxide layer, a silicon nitride layer and a photoresist layer. Figure 3b At the same time as the stacking structure 251 is formed, a trench 101 having a certain depth is formed inside the semiconductor substrate 100. The depth range of the trench 101 can be exemplarily Specifically, it can be and

[0051] It should be noted that in the present invention, the process of etching the hard mask layer 130 to form a plurality of discrete stacked structures 251 composed of the etched nitride layer 110 and the oxide layer 120 is to define the active area of ​​the NPN device structure, and the area between two adjacent discrete stacked structures 251 is the area for forming the LOCOS field oxygen isolation structure. In addition, in this process, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate (i.e., the trench 101) is deepened by increasing the etching time of the active area (i.e., the process of forming the stacked structure 251 in step S200), so when forming the trench for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will be formed, so the depth of the LOCOS structure obtained in this way can be deepened, and the impact on the manufacturing process of the NPN device structure is small. Furthermore, the junction depth of the ion implantation region corresponding to the emitter and base of the NPN structure formed in subsequent steps in the semiconductor substrate 100 needs to be smaller than the depth of the field oxygen isolation structure LOCOS in a direction perpendicular to the semiconductor substrate 100 .

[0052] In step S300, refer to Figure 3c As shown, a field oxygen isolation structure LOCOS is formed in each of the trenches 101 , and ion implantation is performed on the semiconductor substrate 100 between two adjacent field oxygen isolation structures LOCOS to form a collector C, a base B and an emitter E of an NPN structure.

[0053] In this embodiment, the existing field oxygen isolation structure formation process can be used to form the Figure 3c Then, in step S301, a sacrificial oxide layer (not shown) is formed, and the sacrificial oxide layer covers a portion of the top surface of the semiconductor substrate 100 corresponding to the first deep well DNM; wherein the thickness of the sacrificial oxide layer is in the range of Then, step S302 is performed, and the sacrificial oxide layer is used as a mask to perform an ion implantation process on the semiconductor substrate 100 not covered by the sacrificial oxide layer to form a second deep well Pwell in the first deep well. Then, in step S303, the semiconductor substrate 100 is subjected to a rapid thermal annealing process, and the sacrificial oxide layer is removed by a wet etching process. Finally, a collector C, a base B, and an emitter E of an NPN structure are formed respectively by a multi-step ion implantation process.

[0054] Exemplarily, in an embodiment of the present invention, there is provided a specific step of forming the collector C, the base B and the emitter E of the NPN structure, including:

[0055] Performing N-type ion implantation on the surface of a portion of the semiconductor substrate 100 corresponding to the second deep well Pwell, so as to form an emitter E of an NPN structure in the portion of the semiconductor substrate 100 corresponding to the second deep well Pwell;

[0056] Performing P-type ion implantation again on the surface of the remaining semiconductor substrate 100 corresponding to the second deep well Pwell to form a base B of an NPN structure located on both sides of the emitter E in the remaining semiconductor substrate 100 corresponding to the second deep well Pwell; and

[0057] N-type ion implantation is further performed on the semiconductor substrate 100 of the first deep well DNW except the second deep well Pwell, so as to form a collector C of the NPN structure in the semiconductor substrate 100 corresponding to the first deep well DNW.

[0058] It should be noted that, in the embodiment of the present invention, the depth range of the field oxygen isolation structure LOCOS in the direction perpendicular to the semiconductor substrate 100 can be Exemplary examples thereof may include: and

[0059] In step S400, refer to Figure 3d As shown, metal plugs 140 are formed respectively for electrically connecting the collector C, base B and emitter E of the NPN structure, wherein the depth of the metal plugs 140 inserted into the semiconductor substrate 100 corresponding to the collector C, base B and emitter E is less than the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate 100.

[0060] In this embodiment, BPSG (interlayer insulating film) can be first deposited on the surface of the semiconductor substrate 100, and then the film layer can be smoothed using a chemical mechanical polishing process CMP, and then a metal plug for electrically connecting the collector C, base B and emitter E of the NPN structure can be formed using an etching process, that is, a CT area is defined by CT lithography, etching is performed, W is filled, metal is deposited, a metal wiring area is defined by metal lithography, etching is performed, and connection of each terminal of the BJT is completed.

[0061] To sum up, in the manufacturing method of the semiconductor structure provided by the present invention, the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure are separated by the field oxygen isolation structure LOCOS, and the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is required to be deeper than the depth of the lead-out ends of the metal plugs at the emitter and base ends of the NPN structure in the semiconductor substrate. In this way, the current path of path A can be eliminated, that is, a larger beta can be obtained, and the change of the beta parameter of the NPN structure caused by the change of the etching depth of the metal plug can be avoided, that is, the beta parameter of the NPN structure is stabilized.

[0062] Furthermore, in the manufacturing method provided by the present invention, the depth of the field oxygen isolation structure LOCOS in the semiconductor substrate is deepened by increasing the etching time of the active area. Therefore, when forming the groove for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will be formed. Therefore, the depth of the LOCOS structure obtained in this way can be deepened, and the depth of the formed LOCOS is required to be greater than the junction depth of N+ and P+ of NPN, and at the same time, the impact on the manufacturing process of the NPN device structure is small, that is, while not increasing the production cost, the problem of unstable beta parameters of the NPN device structure caused by metal plug etching fluctuations is avoided.

[0063] Afterwards, based on the same concept as the inventive concept of the semiconductor structure manufacturing method described above, the present invention further provides an NPN device structure. Specifically, the depth of the field oxygen isolation structure LOCOS of the NPN device structure provided in the embodiment of the present invention in the semiconductor substrate is deeper than the depth of the field oxygen isolation structure LOCOS of other NPN device structures in the prior art.

[0064] It should be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

[0065] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0066] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, comprising: providing a semiconductor substrate, in which a first deep well is formed, and an oxide layer, a nitride layer and a hard mask layer are sequentially stacked on the surface of the semiconductor substrate; using the hard mask layer as a mask to etch the nitride layer, the oxide layer and a part of the thickness of the semiconductor substrate, so as to form a plurality of discrete stacked structures composed of the etched nitride layer and oxide layer, and at the same time form a plurality of trenches in the semiconductor substrate between adjacent stacked structures; forming a field oxide isolation structure in each trench, and performing ion implantation on the semiconductor substrate between two adjacent field oxide isolation structures to form a collector, a base and an emitter of an NPN structure; respectively forming metal plugs for electrically connecting to the collector, the base and the emitter of the NPN structure, wherein the depth of the metal plugs inserted into the semiconductor substrate corresponding to the collector, the base and the emitter is less than the depth of the field oxide isolation structure in the semiconductor substrate.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the oxide layer is silicon dioxide, and the nitride layer is silicon nitride.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The depth range of the groove is 4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The depth range of the field oxide isolation structure in the direction perpendicular to the semiconductor substrate is 5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, after forming the field oxide isolation structure and before forming the collector, the base and the emitter of the NPN structure, the method further comprises: forming a sacrificial oxide layer, the sacrificial oxide layer covering the top surface of a part of the semiconductor substrate corresponding to the first deep well; using the sacrificial oxide layer as a mask to perform an ion implantation process on the semiconductor substrate not covered by the sacrificial oxide layer to form a second deep well in the first deep well.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, the first deep well is an N-type well, and the second deep well is a P-type well.

7. The manufacturing method of the semiconductor structure according to claim 6, characterized in that, after forming the second deep well, the method further comprises: performing a rapid thermal annealing process on the semiconductor substrate and removing the sacrificial oxide layer by a wet etching process.

8. The manufacturing method of the semiconductor structure according to claim 7, characterized in that, The thickness range of the sacrificial oxide layer is 9. The manufacturing method of the semiconductor structure according to claim 8, characterized in that, the steps of forming the collector, the base and the emitter of the NPN structure include: performing N-type ion implantation on the surface of a part of the semiconductor substrate corresponding to the second deep well to form an emitter of the NPN structure in the part of the semiconductor substrate corresponding to the second deep well; performing P-type ion implantation again on the surface of the remaining semiconductor substrate corresponding to the second deep well to form bases of the NPN structure on both sides of the emitter in the remaining semiconductor substrate corresponding to the second deep well; and, Further perform N-type ion implantation on the semiconductor substrate of the first deep well except for the second deep well to form the collector of the NPN structure in the semiconductor substrate corresponding to the first deep well.

10. The manufacturing method of the semiconductor structure according to claim 9, characterized in that the junction depth of the ion implantation regions correspondingly formed in the semiconductor substrate where the emitter and base of the NPN structure are located is less than the depth of the field oxide isolation structure in the direction perpendicular to the semiconductor substrate.

11. An NPN device structure, characterized in that it is prepared by using the manufacturing method of the semiconductor structure according to any one of claims 1 to 10.

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