Self - aligned double - trench IGBT structure and its manufacturing method

Abstract

The present invention discloses a self - aligned double - trench IGBT structure and a manufacturing method thereof. After forming a body region layer of a second conductivity type and a source region layer of a first conductivity type on the front surface of a substrate, by using different etching selectivity ratios between the first hard mask to the fourth hard mask and combining with the sidewall process, an array of multiple self - aligned gate trenches and source trenches is formed in the substrate in an alternating manner. A gate oxide layer and a gate electrode are formed in the gate trenches, a semiconductor layer of the second conductivity type is formed in the source trenches, a sidewall structure is formed on the front surface of the substrate between the gate trenches and the source trenches, a bonding layer is formed between the sidewalls, and a collector region layer and a buffer region layer are further formed on the back surface of the substrate. The present invention can save photomasks, reduce the device area, further reduce the resistance, increase the current amount and the switching speed, and improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a self-aligned double-groove IGBT (Insulated Gate Bipolar Transistor) structure and a manufacturing method thereof. Background Art

[0002] Compared with a planar MOSFET structure, a trench MOSFET can provide a shorter current path between the source and the drain, thereby reducing the on-resistance, allowing more current to flow through the switch, and significantly reducing the power loss. Using the trench MOSFET structure, a trench-type IGBT device can be further formed. Reducing the spacing between structures in the IGBT device and making the IGBT device have a smaller die area can further reduce the resistance per unit area and increase the current density. However, as the device area continues to shrink, it also brings an increase in the number of processing steps and the number of photomasks in the manufacturing process, which undoubtedly increases the manufacturing cost. In addition, due to the existence of the overlay error, the short-circuit resistance also increases. Summary of the Invention

[0003] The object of the present invention is to overcome the above-mentioned defects existing in the prior art, and provide a self-aligned double-groove IGBT structure and a manufacturing method thereof.

[0004] To achieve the above object, the technical solution of the present invention is as follows:

[0005] The present invention provides a self-aligned double-groove IGBT structure, including:

[0006] A first-conductivity-type source region layer formed on the front surface of a first-conductivity-type substrate, and a second-conductivity-type body region layer located under the source region layer;

[0007] An array of a plurality of gate trenches and source trenches that enter the substrate side by side from the front surface of the substrate and are formed in an alternating manner, a gate electrode and a gate oxide layer located between the gate electrode and the inner wall of the gate trench are formed in the gate trench, and a second-conductivity-type semiconductor layer is formed in the source trench;

[0008] A plurality of sidewall structures protruding from the front surface of the substrate and located between every two adjacent gate trenches and source trenches, and an adhesive layer formed between the sidewalls;

[0009] A second-conductivity-type collector region layer formed on the back surface of the substrate, and a first-conductivity-type buffer layer located under the collector region layer;

[0010] Wherein, the source trench is self-alignedly formed between every two adjacent gate trenches through an opening between every two adjacent sidewalls.

[0011] Further, the bottom end of the gate trench is located in the substrate below the body region layer, and the bottom end of the source trench is flush or non-flush with the bottom end of the gate trench.

[0012] Further, the top end of the gate protrudes above the front surface of the substrate and is located between the sidewalls.

[0013] Further, the sidewalls include a first sidewall and a second sidewall connected to each other; wherein, the first sidewall is disposed adjacent to both sides of the gate trench, the second sidewall is formed outside the first sidewall and is disposed adjacent to both sides of the source trench, and the horizontal width of the source region layer between the source trench and the gate trench is determined by the horizontal width of the second sidewall.

[0014] Further, it further includes: a collector layer formed on the upper surface of the collector region layer.

[0015] The present invention further provides a manufacturing method of a self-aligned double-groove IGBT structure, including:

[0016] Providing a substrate of a first conductivity type, forming a source region layer of the first conductivity type within the front surface of the substrate on the front surface of the substrate, and forming a body region layer of a second conductivity type below the source region layer;

[0017] Forming a plurality of first hard mask layer patterns on the front surface of the substrate;

[0018] Conformally forming a second hard mask layer on the first hard mask layer pattern and performing etch-back to form second hard mask layer patterns on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the front surface of the substrate between two adjacent second hard mask layer patterns on the adjacent side;

[0019] Covering and forming a third hard mask layer on the exposed front surface of the substrate and performing etch-back to form a third hard mask layer pattern between two adjacent second hard mask layer patterns on the adjacent side;

[0020] Removing the second hard mask layer patterns, and then forming first sidewall structures on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern respectively;

[0021] Using the first sidewall as a mask, forming a gate trench downward on the exposed front surface of the substrate, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate electrode in the gate trench within the gate oxide layer;

[0022] A fourth hard mask layer is formed to cover the gate trench, and etch-back is performed to form a fourth hard mask layer pattern between two adjacent first sidewalls on the adjacent side;

[0023] The first hard mask layer pattern and the third hard mask layer pattern are removed, and then source trenches self-aligned between the gate trenches are formed downward on the front surface of the exposed substrate, and a semiconductor layer of a second conductivity type is formed in the source trenches;

[0024] The fourth hard mask layer pattern is removed, and an adhesion layer between the first sidewalls is formed to cover the exposed gate trenches and source trenches;

[0025] The back surface of the substrate is thinned, and a collector region layer of a second conductivity type is formed on the back surface of the thinned substrate, and a buffer layer of a first conductivity type is formed under the collector region layer.

[0026] Further, taking the first sidewall as a mask, gate trenches are formed downward on the front surface of the exposed substrate, a gate oxide layer is formed on the inner wall of the gate trenches, and a gate is formed in the gate trenches inside the gate oxide layer, specifically including:

[0027] Taking the first sidewall, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, the gate trenches are etched downward on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the gate trenches is located in the substrate under the body region layer;

[0028] A gate oxide layer material is deposited on the inner wall of the gate trenches, and a gate material is filled in the gate trenches inside the gate oxide layer, and etch-back is performed on the gate material to form a gate oxide layer on the inner wall of the gate trenches, and a gate is formed in the gate trenches inside the gate oxide layer, and the top end of the gate protrudes above the front surface of the substrate and is located between the first sidewalls.

[0029] Further, the first hard mask layer pattern and the third hard mask layer pattern are removed, and then source trenches self-aligned between the gate trenches are formed downward on the front surface of the exposed substrate, and a semiconductor layer of a second conductivity type is formed in the source trenches, specifically including:

[0030] By etch-back, the first hard mask layer pattern and the third hard mask layer pattern are removed, and then, taking the first sidewall and the fourth hard mask layer pattern as a common mask, source trenches self-aligned between the gate trenches are formed downward on the front surface of the substrate exposed between the first sidewalls, and the bottom end of the source trenches is flush or not flush with the bottom end of the gate trenches;

[0031] Thereafter, a semiconductor layer material is filled in the source trench, and etch-back is performed to form a semiconductor layer of a second conductivity type in the source trench, and the top end of the semiconductor layer is flush with the front surface of the substrate.

[0032] Further, removing the first hard mask layer pattern and the third hard mask layer pattern, and then forming, downward on the exposed front surface of the substrate, source trenches self-aligned between the gate trenches, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically includes:

[0033] By means of etch-back, removing the first hard mask layer pattern and the third hard mask layer pattern, and forming a second sidewall structure on the outer sides of the first sidewalls located on both sides of the fourth hard mask layer pattern;

[0034] Then, using the second sidewalls, the first sidewalls, and the fourth hard mask layer pattern as a common mask, forming, downward on the exposed front surface of the substrate between the second sidewalls, source trenches self-aligned between the gate trenches, and making the bottom end of the source trenches flush or non-flush with the bottom end of the gate trenches;

[0035] Thereafter, a semiconductor layer material is filled in the source trenches, and etch-back is performed to form a semiconductor layer of a second conductivity type in the source trenches, and the top end of the semiconductor layer is flush with the front surface of the substrate;

[0036] Wherein, when forming the second sidewalls, by adjusting the horizontal width of the second sidewalls, the horizontal width of the source region layer located between the source trenches and the gate trenches is adjusted.

[0037] Further, it further includes: forming a collector layer on the upper surface of the collector region layer.

[0038] As can be seen from the above technical solution, in the present invention, a second hard mask layer is conformally formed on the first hard mask layer pattern, and the second hard mask layer pattern is formed on both sides of the first hard mask layer pattern by etch-back. The third hard mask layer pattern can be self-aligned between the second hard mask layer patterns. Without using an additional photomask, the pitch is reduced, the IGBT device has a smaller die area, the resistance per unit area is further reduced, the current density is increased, and the cost is significantly reduced. At the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced. In this way, by stepwise removing the second hard mask layer pattern, the first hard mask layer pattern, and the third hard mask layer pattern, the source trenches can be accurately self-aligned between the gate trenches, effectively reducing the resistance and increasing the switching speed. In addition, when forming the source trenches, a second sidewall with an adjustable width can be formed on the outside of the first sidewall to adjust the width of the formed source trenches, so as to adjust the horizontal width of the source region layer located between the source trenches and the gate trenches, thereby further improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 FIG. is a schematic diagram of a self-aligned dual trench IGBT structure according to a preferred embodiment of the present invention;

[0040] Figure 2 FIG. is a flowchart of a manufacturing method of a self-aligned dual trench IGBT structure according to a preferred embodiment of the present invention;

[0041] Figures 3 - 9 According to a preferred embodiment of the present invention Figure 2 FIG. is a schematic diagram of process steps when manufacturing a self-aligned dual trench IGBT structure according to the method. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art in the technical field to which the present invention belongs. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0043] Unless otherwise specified below, the various parts of the IGBT device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the aforementioned conductive materials. The gate dielectric can be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, and the like. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0044] The first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of N-type and P-type. N-type can be formed by implanting an N-type dopant (e.g., P, As, etc.) into a semiconductor material. P-type can be formed by implanting a P-type dopant (e.g., B, etc.) into a semiconductor material. The above description can be understood with reference to known techniques.

[0045] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0046] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a self-aligned dual-trench IGBT structure according to a preferred embodiment of the present invention. Figure 1 As shown, a self-aligned double-trench IGBT structure of the present invention includes:

[0047] A source region layer 14 of the first conductivity type formed on the front surface 111 of a substrate 11 of the first conductivity type, and a body region layer 13 of the second conductivity type located below the source region layer 14; an array of a plurality of gate trenches 12 and source trenches 19 that enter the substrate 11 side by side from the front surface 111 of the substrate 11 and are formed in an alternating manner, a gate 122 is formed in the gate trench 12, and a gate oxide layer 121 is located between the gate 122 and the inner wall of the gate trench 12, a semiconductor layer 191 of the second conductivity type is formed in the source trench 19; a plurality of sidewall 15 structures protruding and formed on the front surface 111 of the substrate 11 and located between every two adjacent gate trenches 12 and source trenches 19, and an adhesive layer 18 formed between the sidewalls 15; and a collector region layer 21 of the second conductivity type formed on the back surface 112 of the substrate 11, and a buffer region layer 20 of the first conductivity type located below the collector region layer 21.

[0048] Wherein, the source trench 19 is formed between every two adjacent gate trenches 12 by an opening between every two adjacent sidewalls 15 in a self-aligned manner.

[0049] Please refer to Figure 1 . In a preferred embodiment, the substrate 11 can be a lightly doped N-type silicon substrate 11 (N-substrate) of the first conductivity type.

[0050] The body region layer 13 can be a P-type lightly doped body region layer 13 (P-body) of the second conductivity type in the front of the substrate 11.

[0051] The source region layer 14 is located inside the front surface 111 of the substrate 11 and above the body region layer 13; the source region layer 14 can be a source region layer 14 of the first conductivity type that is N+-type heavily doped in the substrate 11 by implantation.

[0052] In a preferred embodiment, the gate 122 can be a polysilicon gate 122 (poly 1) of the first conductivity type that is N+-type heavily doped.

[0053] The semiconductor layer 191 serves as a source contact conductor and can be a semiconductor layer 191 of the second conductivity type doped with P type.

[0054] In a preferred embodiment, the semiconductor layer 191 can be an epitaxial single-crystalline silicon layer grown in the source trench 19 and doped with P type, that is, the semiconductor layer 191 can be a P-type doped epitaxial single-crystalline silicon layer (P EPI).

[0055] In a preferred embodiment, the adhesive layer 18 can be prepared from at least one material such as Ti, TiN, and TaN.

[0056] The sidewall 15 can be prepared from conventional materials used in the sidewall process.

[0057] The buffer layer 20 can be a buffer layer 20 of the first conduction type with N+ type heavy doping in the back surface of the substrate 11. For example, the buffer layer 20 can be a buffer layer 20 (N+H) of the first conduction type with N+ type heavy doping formed by H implantation in the back surface of the substrate 11.

[0058] The collector region layer 21 is located within the back surface 112 of the substrate 11 and above the buffer layer 20; the collector region layer 21 can be a collector region layer 21 of the second conduction type with P+ type heavy doping implanted in the substrate 11. For example, the collector region layer 21 can be a collector region layer 21 of the second conduction type with P+ type heavy doping formed by B implantation.

[0059] In a preferred embodiment, a collector electrode layer 22 is further formed on the upper surface of the collector region layer 21. The collector electrode layer 22 can be prepared from at least one of Al, Ti, NiV, Ag, etc., for example.

[0060] In a preferred embodiment, other structures of the device can also be formed on the front surface of the sidewall 15 and the adhesive layer 18, which can be understood by referring to the prior art.

[0061] Please refer to Figure 1 . In a preferred embodiment, the bottom ends of the gate trench 12 and the source trench 19 are disposed in the substrate 11 below the body region layer 13. Among them, the bottom end of the source trench 19 and the bottom end of the gate trench 12 can be flush in the horizontal direction. Or, the bottom end of the source trench 19 and the bottom end of the gate trench 12 may not be flush in the horizontal direction.

[0062] The gate 122 is isolated by the gate oxide layer 121, and the semiconductor layer 191 of the second conduction type serving as the source contact conductor is connected to the substrate 11 to promote the reduction of resistance. The above structure of the present invention can reduce the device area, provide a shorter current path between the source and the drain, further reduce the resistance per unit area, and increase the current density, thereby reducing the on-resistance, allowing more current to pass through the switch, and significantly reducing the power loss.

[0063] In a preferred embodiment, the top end of the gate 122 can protrude above the front surface 111 of the substrate 11 and be located between the sidewalls 15.

[0064] In a preferred embodiment, the sidewall 15 may include a first sidewall 16 and a second sidewall 17 connected in the horizontal direction. Among them, the first sidewall 16 is disposed on both sides of the gate trench 12; the second sidewall 17 is located outside the first sidewall 16 and is disposed on both sides of the source trench 19. Thus, the horizontal width of the source region layer 14 between the source trench 19 and the gate trench 12 can be determined by the horizontal width of the second sidewall 17. Whether to provide the second sidewall 17 structure and the width of the second sidewall 17 can be determined according to design requirements.

[0065] Next, with reference to the accompanying drawings, a manufacturing method of a self-aligned double trench IGBT structure of the present invention will be described in detail.

[0066] A manufacturing method of a self-aligned double trench IGBT structure of the present invention can be used to manufacture the above Figure 1 self-aligned double trench IGBT structure, and the method may include the following steps:

[0067] Step S1: Provide a substrate of a first conductivity type, form a source region layer of the first conductivity type within the front surface of the substrate on the front surface of the substrate, and form a body region layer of the second conductivity type below the source region layer.

[0068] Please refer to Figure 3 . In a preferred embodiment, an N-type lightly doped silicon substrate 11 of the first conductivity type can be used. The silicon substrate 11 can be N-type lightly doped, for example, by an ion implantation process.

[0069] In a preferred embodiment, an ion implantation process can be used to perform P-type light doping from the front surface 111 of the substrate 11 into the substrate 11 to form a body region layer 13 of the second conductivity type.

[0070] Then, an ion implantation process can be used to perform N+ type heavy doping from the front surface 111 of the substrate 11 into the substrate 11 to form a source region layer 14 of the first conductivity type on the front surface 111 of the substrate 11 above the body region layer 13.

[0071] Step S2: Form a plurality of first hard mask layer patterns on the front surface of the substrate.

[0072] Please refer to Figure 3 . In a preferred embodiment, a first hard mask layer material is deposited on the front surface 111 of the substrate 11. Then, a photoresist layer is formed on the first hard mask layer. Next, through photolithography and etching, a plurality of first hard mask layer patterns 23 (HM1) are formed on the front surface 111 of the substrate 11. After that, the photoresist remaining on the first hard mask layer patterns 23 is removed.

[0073] The first hard mask layer material can be a conventional hard mask layer material. For example, the first hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, etc.

[0074] Step S3: Conformally form a second hard mask layer on the first hard mask layer pattern and perform etch-back to form second hard mask layer patterns on both sides of the first hard mask layer pattern, and expose the top of the first hard mask layer pattern and the front surface of the substrate between two second hard mask layer patterns on the adjacent sides.

[0075] Please refer to Figure 4 . In a preferred embodiment, a conformal CVD process can be used to conformally deposit a second hard mask layer material on the first hard mask layer pattern 23 and the exposed front surface 111 of the substrate 11. Then, etch-back is performed on the second hard mask layer to form second hard mask layer patterns 24 (HM2) on both sides of each first hard mask layer pattern 23, and expose the top of the first hard mask layer pattern 23 and the front surface 111 of the substrate 11 between two second hard mask layer patterns 24 on the adjacent sides, that is, between two second hard mask layer patterns 24 inside two adjacent first hard mask layer patterns 23.

[0076] When depositing the second hard mask layer, the width required for depositing the third hard mask layer later can be reserved through thickness control during deposition.

[0077] The second hard mask layer material can be a conventional hard mask layer material. For example, the second hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, etc.

[0078] Step S4: Cover and form a third hard mask layer on the exposed front surface of the substrate and perform etch-back to form a third hard mask layer pattern between two second hard mask layer patterns on the adjacent sides.

[0079] Please refer to Figure 4。In a preferred embodiment, a conventional process can be adopted to deposit a third hard mask layer material over the entire front surface 111 of the exposed substrate 11 between two second hard mask layer patterns 24 on adjacent sides, completely filling the gap between the two second hard mask layer patterns 24 on adjacent sides, and forming a third hard mask layer covering the first hard mask layer pattern 23, the second hard mask layer pattern 24, and the front surface 111 of the substrate 11. Then, by etching back the third hard mask layer material, a third hard mask layer pattern 25 (HM3) can be formed between the two second hard mask layer patterns 24 on adjacent sides. By conformally forming the second hard mask layer on the first hard mask layer pattern 23 and forming the second hard mask layer patterns 24 on both sides of the first hard mask layer pattern 23 by etching back, the third hard mask layer pattern 25 can be self-aligned between the second hard mask layer patterns 24, achieving a pitch reduction while saving one photomask.

[0080] The third hard mask layer material can be a conventional hard mask layer material. For example, the third hard mask layer material can be one or more of silicon nitride, silicon carbide, silicon oxynitride, and silicon carbonitride.

[0081] Step S5: Remove the second hard mask layer pattern, and then, form first sidewall structures on both sides of the first hard mask layer pattern and on both sides of the third hard mask layer pattern respectively.

[0082] Please refer to Figure 5 。In a preferred embodiment, by utilizing the different etching selectivity ratios between the second hard mask layer material and the first hard mask layer material and the third hard mask layer material, the second hard mask layer pattern 24 located between the first hard mask layer pattern 23 and the third hard mask layer pattern 25 can be removed, exposing the front surface 111 of the substrate 11 located between the first hard mask layer pattern 23 and the third hard mask layer pattern 25.

[0083] Then, a sidewall process can be adopted to deposit sidewall material over the entire first hard mask layer pattern 23, the third hard mask layer pattern 25, and the exposed front surface 111 of the substrate 11, and perform etching back to form first sidewall 16 structures on both sides of each first hard mask layer pattern 23 and on both sides of each third hard mask layer pattern 25 respectively.

[0084] When forming the first sidewall 16, the horizontal width of the first sidewall 16 formed by etching back can be adjusted by controlling the deposition thickness of the first sidewall material, so as to adjust the spacing between the two first sidewalls 16 inside two adjacent first hard mask layer patterns 23 and third hard mask layer patterns 25, thereby enabling adjustment of the horizontal width of the gate trench 12 formed by subsequent etching.

[0085] The material of the sidewall 15 can be a conventional sidewall material that has a different etching selectivity from the materials of the first hard mask layer and the third hard mask layer.

[0086] Step S6: Using the first sidewall as a mask, form a gate trench downward on the front surface of the exposed substrate, form a gate oxide layer on the inner wall of the gate trench, and form a gate electrode in the gate trench within the gate oxide layer.

[0087] Please refer to Figure 5 In a preferred embodiment, after forming the first sidewall 16, the first sidewall 16 can be used as a mask, that is, using the combined pattern of the first sidewall 16 and the first hard mask layer pattern 23 and the combined pattern of the first sidewall 16 and the third hard mask layer pattern 25 as a common mask, etch downward on the front surface 111 of the substrate 11 exposed between every two adjacent first sidewalls 16, form a plurality of parallel deep trenches as the gate trenches 12 in the substrate 11, and make the bottom end of the gate trench 12 located in the substrate 11 below the body region layer 13.

[0088] Then, deposit a gate oxide layer material on the inner wall surface of the gate trench 12 and on the surfaces of the first sidewall 16 and the first hard mask layer pattern 23 and the third hard mask layer pattern 25 structure, and further fill the gate electrode material in the gate trench 12 within the gate oxide layer material, which can fill the gaps between the first sidewalls 16 all the time, so that the gate electrode material covers the gate oxide layer material.

[0089] Next, by back-etching the gate electrode material, a gate oxide layer 121 can be formed on the inner wall of the gate trench 12, and a gate electrode 122 (poly 1) can be formed in the gate trench 12 within the gate oxide layer 121.

[0090] When back-etching the gate electrode material, by controlling the back-etching time, the top ends of the gate electrode 122 and the gate oxide layer 121 can protrude above the front surface 111 of the substrate 11 and be located between the first sidewalls 16, that is, the top ends of the gate electrode 122 and the gate oxide layer 121 are located at a position below the upper ends of the first sidewalls 16. For example, the top ends of the gate electrode 122 and the gate oxide layer 121 can be located at the middle position of the height of the first sidewalls 16. But it is not limited to this.

[0091] The material of the gate electrode 122 can be, for example, N+-heavily doped polysilicon.

[0092] Step S7: Cover and form a fourth hard mask layer on the gate trench, and perform back-etching to form a fourth hard mask layer pattern between two first sidewalls on adjacent sides.

[0093] Please refer to Figure 6。In a preferred embodiment, a fourth hard mask layer material is deposited comprehensively on the surface of the device structure formed in the previous step to fill the gap between two adjacent first sidewalls 16 above the gate trench 12, thereby completely covering the top of the gate 122 and the gate oxide layer 121 exposed on the gate trench 12.

[0094] Then, the fourth hard mask layer material is etched back to form a fourth hard mask layer pattern 26 (HM4) between two first sidewalls 16 on adjacent sides, that is, between two first sidewalls 16 inside two adjacent first hard mask layer patterns 23 and third hard mask layer patterns 25.

[0095] The fourth hard mask layer material can be TEOS oxide (tetraethoxysilane oxide).

[0096] Step S8: Remove the first hard mask layer pattern and the third hard mask layer pattern, and then form source trenches self-aligned between the gate trenches downward on the front surface of the exposed substrate, and form a semiconductor layer of a second conductivity type in the source trenches.

[0097] Please refer to Figure 7 。In a preferred embodiment, the first hard mask layer pattern 23 and the third hard mask layer pattern 25 can be removed by etching back by utilizing the different etching selectivity ratios between the first hard mask layer material and the third hard mask layer material and the first sidewall 16 and the fourth hard mask layer material.

[0098] Then, a sidewall process can be adopted to further form a second sidewall 17 structure on the outer sides of two first sidewalls 16 on both sides of each fourth hard mask layer pattern 26, that is, on both sides of each gate trench 12. The first sidewall 16 and the second sidewall 17 together form a sidewall 15 structure.

[0099] Next, with the second sidewall 17, the first sidewall 16 and the fourth hard mask layer pattern 26 as a common mask, a plurality of deep trenches self-aligned between the gate trenches are formed downward on the front surface 111 of the substrate 11 exposed between every two adjacent second sidewalls 17 to form source trenches 19, and the bottom end of the source trench 19 is flush or not flush with the bottom end of the gate trench 12.

[0100] After that, a semiconductor layer material is filled in the source trench 19. Then, the semiconductor layer material is etched back to form a semiconductor layer 191 in the source trench 19, and the top end of the semiconductor layer 191 is flush or substantially flush with the front surface 111 of the substrate 11.

[0101] In a preferred embodiment, the semiconductor layer 191 can be filled by growing an epitaxial single crystal silicon layer in the source trench 19 and performing P-type doping to have a second conductivity type.

[0102] After forming the substrate 11 of the first conductivity type, the body region layer 13 of the second conductivity type, and the source region layer 14 of the first conductivity type, by utilizing the different etching selectivity ratios between the first hard mask to the fourth hard mask and combining with the sidewall process, an array of multiple self-aligned gate trenches 12 and source trenches 19 is formed in the substrate 11 in an alternating manner. The present invention not only saves photomasks, reduces the processing steps in the manufacturing process, significantly reduces the manufacturing cost, but also reduces the device area and eliminates the overlay error, thereby bringing about a reduction in the on-resistance, allowing more current to travel through the switch, and thus significantly reducing the power loss.

[0103] Among them, when forming the second sidewall 17, by controlling the deposition thickness of the second sidewall material, the horizontal width of the second sidewall 17 formed by etch-back is adjusted to adjust the spacing between the two second sidewalls 17 located inside two adjacent first sidewalls 16, so as to realize the adjustment of the horizontal width of the source region layer 14 located between the source trench 19 and the gate trench 12. At the same time, fine adjustment of the device area can also be realized.

[0104] As another specific embodiment, according to the design requirements, the step of forming the second sidewall 17 can also be omitted, and only the width adjustment of the first sidewall 16 is used as a means for adjusting the device structure. In this case, after removing the first hard mask layer pattern 23 and the third hard mask layer pattern 25, the first sidewall 16 and the fourth hard mask layer pattern 26 are used as a common mask, and self-aligned source trenches 19 are formed downward on the front surface 111 of the substrate 11 exposed between the first sidewalls 16.

[0105] Step S9: Remove the fourth hard mask layer pattern, and cover the exposed gate trenches and source trenches with a bonding layer formed between the first sidewalls.

[0106] Please refer to Figure 7 ... In a preferred embodiment, by utilizing the different etching selectivity ratios between the fourth hard mask layer material and the first sidewall material and the second sidewall material, the fourth hard mask layer pattern 26 is removed by etch-back to expose the top of the gate 122.

[0107] Please refer to Figure 8 ... Then, a bonding layer material is deposited comprehensively on the surface of the above-mentioned formed device structure to fill the gaps between the second sidewalls 17, and after etch-back, a bonding layer 18 is formed to cover the gate 122 of the exposed gate trench 12 and the conductive semiconductor layer 191 of the source trench 19 between the first sidewalls 16.

[0108] Among them, the bonding layer 18 located above the gate trench 12 is in direct contact with the first sidewall 16, and the bonding layer 18 located above the source trench 19 is in direct contact with the second sidewall 17.

[0109] The bonding layer 18 can be prepared from at least one of Ti, TiN, and TaN.

[0110] Step S10: Thinning the back surface of the substrate, forming a collector region layer of the second conductivity type on the back surface of the thinned substrate, and forming a buffer layer of the first conductivity type under the collector region layer.

[0111] Please refer to Figure 9 . In a preferred embodiment, the front surface of the substrate 11 can be inverted so that the back surface of the substrate 11 faces up and the front surface faces down. Then, the front surface of the substrate 11 can be fixed using the prior art. For example, the Bluetape fixing method can be used to fix the front surface of the substrate 11.

[0112] Next, the back surface of the substrate 11 can be thinned using the prior art. For example, a combination of chemical etching and mechanical polishing can be used to thin the back surface of the substrate 11.

[0113] In a preferred embodiment, the back surface of the substrate 11 can be thinned to a degree that the substrate 11 retains a thickness of 60 - 190 μm.

[0114] Then, a P+-type heavily doped collector region layer 21 of the second conductivity type can be formed by implantation on the back surface 112 of the substrate 11 using a conventional implantation method. For example, a P+-type heavily doped collector region layer 21 (P+ imp) can be formed by B implantation on the back surface of the substrate 11.

[0115] Next, a buffer layer 20 of the first conductivity type with N+-type heavy doping from deep to shallow can be formed in the back surface of the substrate 11 under the collector region layer 21 using a conventional implantation method. For example, a multi-step implantation of H deep implantation (Himp deep) and H shallow implantation (H imp shallow) can be used in the back surface of the substrate 11 to form a buffer layer 20 (N+ H imp) of the first conductivity type with N+-type heavy doping. Then, annealing is performed. For example, furnace annealing (Furnace anneal) etc. can be used.

[0116] Finally, a collector layer 22 can be further formed on the upper surface of the collector region layer 21 on the back surface of the substrate 11.

[0117] In a preferred embodiment, a collector layer 22 can be formed by depositing and patterning electrode metal on the collector region layer 21 using a conventional metal electrode manufacturing process. For example, the collector layer 22 can be prepared from at least one of Al, Ti, NiV, Ag, etc. The finally formed IGBT device structure is as Figure 1 shown.

[0118] In summary, in the present invention, a second hard mask layer is conformally formed on the first hard mask layer pattern 23, and second hard mask layer patterns 24 are formed on both sides of the first hard mask layer pattern 23 by etch-back. A third hard mask layer pattern 25 can be self-alignedly formed between the second hard mask layer patterns 24. Without using an additional photomask, the pitch is reduced, enabling the IGBT device to have a smaller die area, thereby further reducing the resistance per unit area, increasing the current density, and significantly reducing the cost. At the same time, since there is no overlay error, the short-circuit resistance can be effectively reduced. Thus, by stepwise removing the second hard mask layer patterns 24, the first hard mask layer pattern 23, and the third hard mask layer pattern 25, source trenches 19 can be precisely self-alignedly formed between the gate trenches 12, effectively reducing the resistance and increasing the switching speed. Additionally, when forming the source trenches 19, a second sidewall 17 with an adjustable width can be additionally formed outside the first sidewall 16 to adjust the formation width of the source trenches 19, thereby adjusting the horizontal width of the source region layer 14 located between the source trenches 19 and the gate trenches 12, further improving the device performance.

[0119] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention as defined in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A manufacturing method of a self-aligned double-groove IGBT structure, characterized in that Including: Providing a substrate of a first conductivity type, forming a source region layer of the first conductivity type within the front surface of the substrate on the front surface of the substrate, and forming a body region layer of a second conductivity type underlying the source region layer; Forming a plurality of first hard mask layer patterns on the front surface of the substrate; Conformally forming a second hard mask layer on the first hard mask layer pattern and performing etch-back to form second hard mask layer patterns on both sides of the first hard mask layer pattern, and exposing the top of the first hard mask layer pattern and the front surface of the substrate between two adjacent second hard mask layer patterns on the adjacent side; Covering and forming a third hard mask layer on the exposed front surface of the substrate and performing etch-back to form a third hard mask layer pattern between two adjacent second hard mask layer patterns on the adjacent side; Removing the second hard mask layer patterns, and then forming first sidewall structures on both sides of the first hard mask layer pattern and both sides of the third hard mask layer pattern respectively; Using the first sidewall as a mask, forming a gate trench downward on the exposed front surface of the substrate, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate within the gate trench inside the gate oxide layer; Covering and forming a fourth hard mask layer on the gate trench and performing etch-back to form a fourth hard mask layer pattern between two adjacent first sidewalls; Removing the first hard mask layer pattern and the third hard mask layer pattern, and then forming source trenches self-aligned between the gate trenches downward on the exposed front surface of the substrate, and forming a semiconductor layer of the second conductivity type in the source trenches; Removing the fourth hard mask layer pattern, and covering and forming an adhesive layer between the first sidewalls on the exposed gate trenches and source trenches; Thinning the back surface of the substrate, and forming a collector region layer of the second conductivity type on the back surface of the thinned substrate, and forming a buffer region layer of the first conductivity type underlying the collector region layer.

2. The manufacturing method of the self-aligned double-groove IGBT structure according to claim 1, wherein, The step of using the first sidewall as a mask, forming a gate trench downward on the exposed front surface of the substrate, forming a gate oxide layer on the inner wall of the gate trench, and forming a gate within the gate trench inside the gate oxide layer specifically includes: Using the first sidewall, the first hard mask layer pattern, and the third hard mask layer pattern as a common mask, etching downward to form a gate trench on the front surface of the substrate exposed between the first sidewalls, and making the bottom end of the gate trench located in the substrate below the body region layer; Depositing a gate oxide layer material on the inner wall of the gate trench, filling a gate material within the gate trench inside the gate oxide layer, and performing etch-back on the gate material to form a gate oxide layer on the inner wall of the gate trench, and forming a gate within the gate trench inside the gate oxide layer, and making the top end of the gate protrude above the front surface of the substrate and located between the first sidewalls.

3. The manufacturing method of the self-aligned double-groove IGBT structure according to claim 1, characterized in that, Removing the patterns of the first hard mask layer and the third hard mask layer, and then forming source trenches self-aligned between the gate trenches downward on the front surface of the exposed substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically including: Removing the patterns of the first hard mask layer and the third hard mask layer by etch-back. Then, using the first sidewall and the pattern of the fourth hard mask layer as a common mask, forming source trenches self-aligned between the gate trenches downward on the front surface of the substrate exposed between the first sidewalls, and making the bottom end of the source trenches flush or non-flush with the bottom end of the gate trenches; After that, filling the source trenches with a semiconductor layer material and performing etch-back to form a semiconductor layer of a second conductivity type in the source trenches, and making the top end of the semiconductor layer flush with the front surface of the substrate.

4. The manufacturing method of the self-aligned double-groove IGBT structure according to claim 1, characterized in that, Removing the patterns of the first hard mask layer and the third hard mask layer, and then forming source trenches self-aligned between the gate trenches downward on the front surface of the exposed substrate, and forming a semiconductor layer of a second conductivity type in the source trenches, specifically including: Removing the patterns of the first hard mask layer and the third hard mask layer by etch-back, and forming second sidewall structures on the outer sides of the first sidewalls located on both sides of the pattern of the fourth hard mask layer; Then, using the second sidewalls, the first sidewalls and the pattern of the fourth hard mask layer as a common mask, forming source trenches self-aligned between the gate trenches downward on the front surface of the substrate exposed between the second sidewalls, and making the bottom end of the source trenches flush or non-flush with the bottom end of the gate trenches; After that, filling the source trenches with a semiconductor layer material and performing etch-back to form a semiconductor layer of a second conductivity type in the source trenches, and making the top end of the semiconductor layer flush with the front surface of the substrate; Wherein, when forming the second sidewalls, the horizontal width of the source region layer located between the source trenches and the gate trenches is adjusted by adjusting the horizontal width of the second sidewalls.

5. The manufacturing method of the self-aligned double-groove IGBT structure according to claim 1, wherein, Further including: Forming a collector layer on the upper surface of the collector region layer.

6. A self-aligned double-groove IGBT structure, characterized in that The IGBT structure is obtained by the manufacturing method according to any one of the preceding claims 1-5, and includes: A source region layer of a first conductivity type formed on the front surface of a substrate of a first conductivity type, and a body region layer of a second conductivity type located under the source region layer; An array of a plurality of gate trenches and source trenches entering the substrate side by side from the front surface of the substrate and formed in an alternating manner, a gate and a gate oxide layer located between the gate and the inner wall of the gate trench are formed in the gate trenches, and a semiconductor layer of a second conductivity type is formed in the source trenches; A plurality of sidewall structures protruding from the front surface of the substrate and located between every two adjacent gate trenches and source trenches, and an adhesion layer formed between the sidewalls; A collector region layer of a second conductivity type formed on the back surface of the substrate, and a buffer layer of a first conductivity type located under the collector region layer; Wherein, the source trench is formed self-alignedly between every two adjacent gate trenches through an opening between every two adjacent sidewalls.

7. The self-aligned double-groove IGBT structure according to claim 6, characterized in that, The bottom end of the gate trench is located in the substrate under the body region layer, and the bottom end of the source trench is flush or non-flush with the bottom end of the gate trench.

8. The self-aligned double-groove IGBT structure according to claim 6, characterized in that, The top end of the gate protrudes on the front surface of the substrate and is located between the sidewalls.

9. The self-aligned double-groove IGBT structure according to claim 6, wherein The sidewall includes a connected first sidewall and a second sidewall; wherein, the first sidewall is disposed adjacent to both sides of the gate trench, the second sidewall is formed outside the first sidewall and is disposed adjacent to both sides of the source trench, and the horizontal width of the source region layer between the source trench and the gate trench is determined by the horizontal width of the second sidewall.

10. The self-aligned double-groove IGBT structure according to claim 6, wherein Further comprising: A collector layer formed on the upper surface of the collector region layer.

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