Field effect transistor and preparation method thereof
By arranging a first buffer layer with different doping types and concentrations in the epitaxial layer of the field effect transistor, the depletion region width is increased, the problem of insufficient pressure resistance of the MOSFET device is solved, and the reliability of the device is improved.
Patent Information
- Application Number
- CN202410396295.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-02
- Publication Date
- 2025-10-17
AI Technical Summary
Improving the voltage resistance of existing MOSFET devices remains an important research direction, especially how to improve their voltage resistance to increase reliability.
A first buffer layer is set in the epitaxial layer of the field effect transistor. The doping type and concentration are different from those of the well region. By increasing the width of the depletion region, the movement of free electrons toward the drain is slowed down, thereby reducing the risk of oxide layer breakdown.
The voltage resistance of the field effect transistor is improved, its reliability is increased, and the risk of oxide layer breakdown is reduced, especially the performance is better under reverse bias voltage.
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Figure CN120812987A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a field effect transistor and a method for manufacturing a field effect transistor. BACKGROUND
[0002] A field effect transistor (FET) is a semiconductor device that controls the current flow in the output circuit by using the electric field effect of the control input circuit. The field effect transistor is a device with three terminals: gate, source and drain, and the current flow is controlled by applying a voltage to the gate, thereby changing the conductivity between the drain and the source. The MOS structure (Metal-Oxide-Semiconductor) is an electronic device structure based on semiconductor materials, which is composed of metal electrodes, oxide layers and semiconductors. The MOS structure has a wide range of application scenarios, including but not limited to the following fields: integrated circuits such as logic gates, memories and amplifiers; high-frequency electronic devices; communication fields such as radio frequency amplifiers, signal mixers and other high-frequency electronic devices; power management such as DC-DC converters, power inverters and other power management devices. The characteristics of the MOS structure include high input impedance, low power consumption, large dynamic range, and strong integrability. In MOSFET devices, the breakdown field of silicon carbide MOSFET can be 10 times that of silicon MOSFET, so it can achieve high voltage resistance with low impedance and thin thickness. Even so, the continuous improvement of the voltage resistance performance of MOSFET devices is still an important research and technical development direction for those skilled in the art. SUMMARY
[0003] Therefore, in order to overcome at least part of the defects and deficiencies existing in the prior art, the embodiments of the present application provide a field effect transistor and a method for manufacturing a field effect transistor.
[0004] Specifically, in one aspect, the field effect transistor provided by the embodiments of the present application comprises: an epitaxial layer; an oxide layer arranged on the epitaxial layer, and the epitaxial layer has a gate oxide under region under the oxide layer; a polysilicon layer arranged on a side of the oxide layer away from the epitaxial layer, and the polysilicon layer is provided with a gate electrode; a first source region and a second source region arranged on two sides of the gate oxide under region along a first direction respectively; a well region arranged outside the first source region and the second source region, and the first source region and the second source region are exposed to the well region near an upper surface of the oxide layer; and a first buffer layer arranged in the epitaxial layer, and the first buffer layer is arranged on a side of the well region away from the oxide layer, and the first buffer layer extends along the first direction; wherein the epitaxial layer, the first source region and the second source region are of a first doping type, the first buffer layer and the well region are of a second doping type, and the doping concentration of the first buffer layer is different from the doping concentration of the well region.
[0005] In one specific embodiment of the present application, the first buffer layer comprises a plurality of first buffer layers, and the plurality of first buffer layers are arranged at intervals along a second direction.
[0006] In one specific embodiment of the present application, the first buffer layer is connected with the well region.
[0007] In one specific embodiment of the present application, the field effect transistor further comprises: a second buffer layer arranged in the epitaxial layer, and the second buffer layer is arranged on a side of the well region away from the oxide layer, and the second buffer layer extends along the second direction, the second buffer layer is of the second doping type, and the doping concentration of the second buffer layer is different from the doping concentration of the well region.
[0008] In one specific embodiment of the present application, in a third direction, the distance between the first buffer layer and the well region is the same as the distance between the second buffer layer and the well region.
[0009] In one specific embodiment of the present application, the second buffer layer comprises a plurality of second buffer layers, and the plurality of second buffer layers are arranged at intervals along the first direction.
[0010] In one specific embodiment of the present application, the field effect transistor further comprises: a third buffer layer arranged between the plurality of first buffer layers, the third buffer layer is of the second doping type, the doping concentration of the third buffer layer is different from the doping concentration of the well region, and the doping concentration of the third buffer layer is different from the doping concentration of the first buffer layer.
[0011] In one specific embodiment of the present application, the second buffer layer includes two, and the two second buffer layers are arranged at opposite ends of the first buffer layer along the first direction, and the first buffer layer connects the two second buffer layers.
[0012] In one specific embodiment of the present application, the thickness of the first buffer layer ranges from 0.5 to 5 μm; and / or, the doping concentration of the first buffer layer is less than the doping concentration of the well region.
[0013] In one specific embodiment of the present application, the method for manufacturing a field effect transistor further includes: generating a first buffer layer in the epitaxial layer along a first direction; generating two well regions arranged at intervals on the epitaxial layer, and forming a gate oxide under region between the two well regions, and the doping concentration of the first buffer layer is different from the doping concentration of the well region; generating a first source region and a second source region on the well region; forming an oxide layer on the side of the gate oxide under region away from the epitaxial layer; and forming a polysilicon layer on the side of the oxide layer away from the epitaxial layer.
[0014] In one specific embodiment of the present application, when the first buffer layer is generated in the epitaxial layer along the first direction, the method further includes: generating a second buffer layer in the epitaxial layer along a second direction, and the doping concentration of the second buffer layer is different from the doping concentration of the well region.
[0015] As can be seen from the above, the field effect transistor provided by the embodiments of the present application includes an epitaxial layer, an oxide layer, a polysilicon layer, a first source region and a second source region, and a well region, and a first buffer layer is arranged in the epitaxial layer, the first buffer layer is arranged on the side of the well region away from the oxide layer, and the first buffer layer extends along a first direction, and the doping concentration of the first buffer layer is different from the doping concentration of the well region; by arranging the first buffer layer in the epitaxial layer of the field effect transistor, when the field effect transistor is subjected to a reverse bias voltage, the movement of free electrons in the gate oxide under region to the drain direction can be slowed down, so as to reduce the risk of breakdown of the oxide layer, and the field effect transistor has better pressure resistance, thereby increasing the reliability of the field effect transistor. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 A structural schematic diagram of a field effect transistor provided by the embodiments of the present application is shown in the figure.
[0018] Figure 2 As shown in the XZ plane structure diagram of the field effect transistor. Figure 1 As shown in the XZ plane structure diagram of the field effect transistor.
[0019] Figure 3 As shown in the XZ plane structure diagram of the field effect transistor. Figure 4A As shown in the XZ plane structure diagram of the field effect transistor. Figure 1 As shown in the XY plane structure diagram of the first buffer layer.
[0020] Figure 4B As shown in the XY plane structure diagram of the first buffer layer and the third buffer layer.
[0021] Figure 5 As shown in the structure diagram of another field effect transistor provided by the embodiment of the application.
[0022] Figure 6 As shown in the structure diagram of another field effect transistor provided by the embodiment of the application.
[0023] Figure 7 As shown in the XZ plane structure diagram of the field effect transistor. Figure 6 As shown in the XZ plane structure diagram of the field effect transistor.
[0024] Figure 8 As shown in the XZ plane structure diagram of the field effect transistor. Figure 9 As shown in the XZ plane structure diagram of the field effect transistor. Figure 10 As shown in the XY plane structure diagram of the first buffer layer and the second buffer layer. Figure 6 As shown in the XY plane structure diagram of the first buffer layer and the second buffer layer.
[0025] Figure 11 As shown in the flowchart of the preparation method of the field effect transistor provided by the embodiment of the application.
[0026] Figures 12A to 12F As shown in the structure generation diagram of the preparation method of the field effect transistor.
[0027]
Explanation of reference numerals
[0028] 100, field effect transistor; 00, substrate; 10, epitaxial layer; 101, gate oxide under region; 20, oxide layer; 30, polysilicon layer; 41, first source region; 42, second source region; 50, well region; 60, first buffer layer; 70, second buffer layer; 80, third buffer layer. DETAILED DESCRIPTION
[0029] In order to make the objects, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments described in the application, all other embodiments obtained by those skilled in the art without creative effort fall within the protection scope of the application.
[0030] It should be noted that all the direction indications (such as up, down, left, right, front, back, top, bottom) in the embodiments of the present application are only used to explain the relative position relationship, movement condition and the like between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the direction indications will also change accordingly. In addition, the term "vertical" referred to in the embodiments of the present application and the claims refers to an included angle of 90° or a deviation of -5° to +5° between two elements, and the term "parallel" refers to an included angle of 0° or a deviation of -5° to +5° between two elements.
[0031] In the embodiments of the present application, the description such as "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features.
[0032] Referring to Figure 1 and Figure 2 , the embodiments of the present application provide a field effect transistor 100, which can for example include an epitaxial layer 10, an oxide layer 20, a polysilicon layer 30, a first source region 41, a second source region 42, a well region 50 and a first buffer layer 60.
[0033] The oxide layer 20 is arranged on the epitaxial layer 10, and the polysilicon layer 30 is arranged on the side of the oxide layer 20 away from the epitaxial layer 10, i.e. the polysilicon layer 30 is arranged on the oxide layer 20. The oxide layer 20 serves as an insulator, which can for example be silicon dioxide or the like. The polysilicon layer 30 is provided with a gate electrode. The epitaxial layer 10 has a gate oxide under region 101 under the oxide layer 20, i.e. the gate oxide under region 101 is located at one end of the epitaxial layer 10 and on the side of the oxide layer 20 away from the polysilicon layer 30. The first source region 41 and the second source region 42 are located in the epitaxial layer 10, and the first source region 41 and the second source region 42 are arranged on both sides of the gate oxide under region 101 along a first direction X, respectively. The well region 50 is arranged outside the first source region 41 and the second source region 42, and the first source region 41 and the second source region 42 are exposed to the well region 50 near the upper surface of the oxide layer 20. The first buffer layer 60 is arranged in the epitaxial layer 10, and the first buffer layer 60 is arranged on the side of the well region 50 away from the oxide layer 20, and the first buffer layer 60 extends along the first direction X. The doping type of the epitaxial layer 10, the first source region 41 and the second source region 42 is a first doping type, and the doping type of the first buffer layer 60 and the well region 50 is a second doping type. The doping concentration of the first buffer layer 60 and the doping concentration of the well region 50 are different.
[0034] The field effect transistor 100 provided by the embodiment achieves the effect of increasing the width of the depletion region by arranging the first buffer layer 60, so that when the field effect transistor 100 is subjected to a reverse bias voltage, the movement of free electrons in the gate oxide under region 101 to the drain direction can be slowed down, thereby reducing the risk of breakdown of the oxide layer 20 and making the silicon carbide metal oxide semiconductor field effect transistor (i.e. silicon carbide MOSFET) 100 have better pressure resistance characteristics, thereby increasing the reliability of the field effect transistor 100.
[0035] Specifically, when the field effect transistor 100 is used as a power device, the polysilicon layer 30 is provided with a gate electrode, the first source region 41 can be provided with a source electrode for example, and the second source region 42 can be provided with a drain electrode for example. When the external voltage applied to the field effect transistor 100 gradually increases from 0, since the gate electrode and the epitaxial layer 10 form a capacitor, when the gate electrode input voltage gradually rises, the holes in the epitaxial layer 10 are driven away from the gate oxide under region 101 to leave negative ions to mirror the charge on the gate, so that a depletion layer is formed in the contact area between the epitaxial layer 10 and the well region 50, and a depletion layer is also formed in the contact area between the epitaxial layer 10 and the first buffer layer 60. When a reverse bias voltage is applied between the polysilicon layer 30 and the drain electrode as shown, under the influence of the reverse bias voltage, the free electrons in the gate oxide under region 101 first need to overcome the depletion layer formed in the first buffer layer 60 before they can be smoothly conducted to the drain. Therefore, the arrangement of the first buffer layer 60 can slow down the movement of free electrons in the gate oxide under region 101 to the drain electrode direction when the field effect transistor 100 is subjected to a reverse bias voltage, thereby reducing the risk of breakdown of the oxide layer 20 and making the field effect transistor 100 have better pressure resistance characteristics, thereby increasing the reliability of the field effect transistor 100. Figure 1
[0035] Specifically, when the field effect transistor 100 is used as a power device, the polysilicon layer 30 is provided with a gate electrode, the first source region 41 can be provided with a source electrode for example, and the second source region 42 can be provided with a drain electrode for example. When the external voltage applied to the field effect transistor 100 gradually increases from 0, since the gate electrode and the epitaxial layer 10 form a capacitor, when the gate electrode input voltage gradually rises, the holes in the epitaxial layer 10 are driven away from the gate oxide under region 101 to leave negative ions to mirror the charge on the gate, so that a depletion layer is formed in the contact area between the epitaxial layer 10 and the well region 50, and a depletion layer is also formed in the contact area between the epitaxial layer 10 and the first buffer layer 60. When a reverse bias voltage is applied between the polysilicon layer 30 and the drain electrode as shown, under the influence of the reverse bias voltage, the free electrons in the gate oxide under region 101 first need to overcome the depletion layer formed in the first buffer layer 60 before they can be smoothly conducted to the drain. Therefore, the arrangement of the first buffer layer 60 can slow down the movement of free electrons in the gate oxide under region 101 to the drain electrode direction when the field effect transistor 100 is subjected to a reverse bias voltage, thereby reducing the risk of breakdown of the oxide layer 20 and making the field effect transistor 100 have better pressure resistance characteristics, thereby increasing the reliability of the field effect transistor 100.
[0036] The doping concentration of the first buffer layer 60 is different from the doping concentration of the well region 50, and further, the doping concentration of the first buffer layer 60 is less than the doping concentration of the well region 50. Therefore, the width of the depletion layer formed between the first buffer layer 60 and the well region 50 is large, so that a better anti-pressure effect can be achieved. Specifically, the doping concentration per cubic centimeter of the well region 50 can be, for example, in the order of 10 17, and the doping concentration per cubic centimeter of the first buffer layer 60 can be, for example, in the order of 10 15-16. The doping concentration per cubic centimeter of the first source region 41 and the second source region 42 can be, for example, in the order of 10 19, and the doping concentration per cubic centimeter of the epitaxial layer 10 can be, for example, in the order of 10 13-15. In one specific embodiment of the present embodiment, the thickness of the first buffer layer 60 in the third direction Z can be, for example, in the range of 0.5-5 μm.
[0037] Referring to Figure 3 , the number of the first buffer layer 60 can be, for example, one, and the specific position of the first buffer layer 60 in the second direction Y of the epitaxial layer 10 can be set according to actual needs. Referring to Figure 4A , the first buffer layer 60 can include a plurality of first buffer layers 60, and the plurality of first buffer layers 60 can be spaced apart along the second direction Y. In one specific embodiment of the present embodiment, the spacing between two adjacent first buffer layers 60 can be, for example, in the range of 0.3-10 μm.
[0038] Referring to Figure 4B , the field effect transistor 100 provided by the present embodiment can further include a third buffer layer 80, which can be disposed between the plurality of first buffer layers 60. The third buffer layer 80 can be of a second doping type, and the doping concentration of the third buffer layer 80 can be different from the doping concentration of the well region 50 and the doping concentration of the first buffer layer 60. The doping concentration of the third buffer layer 80 can be, for example, higher than the doping concentration of the first buffer layer 60. The third buffer layer 80 can be, for example, higher than the first buffer layer 60 in the third direction Z. By disposing the third buffer layer 80 with a higher doping concentration, the on-resistance of the field effect transistor 100 can be reduced, so that the temperature generated by the field effect transistor 100 when working in a forward on-state as a power device can be reduced, thereby making the field effect transistor 100 more reliable. In one specific embodiment of the present embodiment, the third buffer layer 80 can be disposed in the gate oxide lower region 101 in the third direction Z. The doping concentration of the third buffer layer 80 can be, for example, in the order of 10 17-18.
[0039] In one specific embodiment of the present embodiment, referring again to Figure 1The first buffer layer 60 can be connected with the well region 50, for example. In the third direction Z, the first buffer layer 60 is in contact with the well region 50, i.e. the upper surface of the well region 50 is in contact with the lower surface of the first buffer layer 60. In another specific implementation of the embodiment, referring to Figure 5 The first buffer layer 60 and the well region 50 are spaced apart, i.e. the first buffer layer 60 and the well region 50 are spaced apart in the third direction, and a space is provided between the upper surface of the well region 50 and the lower surface of the first buffer layer 60.
[0040] Referring to Figure 6 and Figure 7 The field effect transistor 100 provided by the embodiment can further include a second buffer layer 70, for example. The second buffer layer 70 is provided in the epitaxial layer 10, and the second buffer layer 70 is provided on the side of the well region 50 away from the oxide layer 20, and the second buffer layer 70 extends along the second direction Y. The second buffer layer 70 is of a second doping type, the doping concentration of the second buffer layer 70 is different from the doping concentration of the well region 50, and the doping concentration of the second buffer layer 70 is the same as the doping concentration of the first buffer layer 60.
[0041] In one implementation of the embodiment, in the third direction Z, the distance between the first buffer layer 60 and the well region 50 is the same as the distance between the second buffer layer 70 and the well region 50, i.e. the second buffer layer 70 and the first buffer layer 60 can be located on the same horizontal plane, and the thicknesses can be the same, for example. In another implementation of the embodiment, the second buffer layer 70 and the first buffer layer 60 can not be located on the same horizontal plane, for example. Of course, the embodiment is not limited in this way.
[0042] Further, referring to Figure 8 The second buffer layer 70 can include a plurality of second buffer layers 70, which are spaced apart in the first direction X, for example. Of course, referring to Figure 9 The second buffer layer 70 can also be one, for example, and the position of the second buffer layer 70 in the first direction X can be set according to actual needs. Referring again to Figure 8 The second buffer layer 70 can include two second buffer layers 70, which are spaced apart in the first direction X at opposite ends of the first buffer layer 60, for example, and the first buffer layer 60 connects the two second buffer layers 70. In some implementations of the embodiment, the third buffer layer 80 can also be provided between the two second buffer layers 70, and the third buffer layer 80 also extends along the second direction Y.
[0043] Further, referring to Figure 9 , the second buffer layer 70 can be disposed, for example, on the lower side of the gate oxide under region 101 along the third direction Z, and the second buffer layer 70 can be disposed continuously along the second direction Y, and the second buffer layer 70 and the well region 50 can be disposed, for example, with an interval. Referring to Figure 10 , in another embodiment of the present embodiment, the second buffer layer 70 can be disposed, for example, on the lower side of the gate oxide under region 101 along the third direction Z, and the second buffer layer 70 can be disposed with an interval in multiple segments along the second direction Y. In some embodiments of the present embodiment, the third buffer layer 80 can also include multiple third buffer layers 80, which can be disposed, for example, between the multiple segments of the second buffer layer 70.
[0044] Specifically, when a forward bias voltage is applied on the field effect transistor 100 along the third direction Z, the forward bias voltage is realized by the polysilicon layer 30 above the oxide layer 20 and the power supply connected across the drain electrode. Therefore, the inversion layer formed by the forward bias voltage in the well region 50 is mainly concentrated at the junction of the well region 50 and the gate oxide under region 101. Therefore, when the second buffer layer 70 is disposed continuously along the second direction Y, the second buffer layer 70 and the well region 50 are disposed with an interval, which can make the free electrons in the epitaxial layer 10 reach the gate oxide under region 101 smoothly and pass through the inversion layer formed at the well region 50 to realize the conduction between the source electrode and the drain electrode.
[0045] Further, in the embodiment as shown in Figure 10 , the second buffer layer 70 is disposed with an interval in multiple segments along the second direction Y, so that the free electrons can move from the drain electrode to the gate oxide under region 101 smoothly and reach the source electrode. In this case, it is not necessary to dispose the second buffer layer 70 and the well region 50 with an interval, and therefore, when the field effect transistor 100 is manufactured, the precision control of the second buffer layer 70 in the third direction Z and in the first direction X can be reduced, thereby reducing the manufacturing difficulty. Specifically, the interval of the multiple second buffer layers 70 along the second direction Y can be, for example, in the range of 0.3 to 10 μm.
[0046] Referring to Figure 11 , the present embodiment also provides a manufacturing method of a field effect transistor, which includes the following steps:
[0047] S10, generating an epitaxial layer;
[0048] S20, generating a first buffer layer in the epitaxial layer along a first direction;
[0049] S30, generating two spaced-apart well regions on the epitaxial layer, a gate oxide under region being formed between the two well regions, and the doping concentration of the first buffer layer being different from the doping concentration of the well regions;
[0050] S40, generating a first source region and a second source region on the well regions;
[0051] S50, forming an oxide layer on the side of the gate oxide under region away from the epitaxial layer; and
[0052] S60, forming a polysilicon layer on the side of the oxide layer away from the epitaxial layer.
[0053] Further, the generating the first buffer layer in the epitaxial layer along the first direction further comprises: generating a second buffer layer in the epitaxial layer along a second direction, the doping concentration of the second buffer layer being different from the doping concentration of the well regions.
[0054] The generating the first buffer layer in the epitaxial layer along the first direction further comprises: generating a third buffer layer in the epitaxial layer, the doping concentration of the third buffer layer being different from the doping concentration of the well regions, and the doping concentration of the third buffer layer being different from the doping concentration of the first buffer layer.
[0055] Referring to Figures 12A to 12F The preparation method of the field effect transistor is described in detail.
[0056] Specifically, as shown in Figure 12A , a substrate 00 is provided first; as shown in Figure 12B , an epitaxial layer 10 is generated on the substrate 00 by ion implantation through epitaxial method, and the substrate 00 and the epitaxial layer 10 together form an epitaxial wafer. As shown in Figure 12C , then a first buffer layer 60 as shown in Figure 12C is generated in the epitaxial layer 10 along a first direction X by ion implantation through mask and epitaxial method. As shown in Figure 12D , then two well regions 50 as shown in Figure 12D are generated on the epitaxial layer 10 by ion implantation through mask and epitaxial method, and a gate oxide under region 101 is formed between the two well regions 50. In this embodiment, the doping concentration of the first buffer layer 60 is different from the doping concentration of the well regions 50.
[0057] Subsequently, a third buffer layer 70 as shown in Figure 12DThe first source region 41 and the second source region 42 are arranged on opposite sides of the gate oxide under region 101, and the first source region 41 and the second source region 42 can be arranged on the same horizontal plane. Finally, the oxide layer 20 and the polysilicon layer 30 can be formed on the epitaxial layer 10 by, for example, a mask and etching method.
[0058] In one specific embodiment of the present embodiment, the first buffer layer 60 can be formed by, for example, ion implantation in the epitaxial layer 10 along the first direction X by, for example, a mask and epitaxial method. Figure 12C The second buffer layer 70 can also be formed by, for example, ion implantation in the epitaxial layer 10 along the second direction Y by, for example, a mask and epitaxial method. The first buffer layer 60 and the second buffer layer 70 can be formed simultaneously, but the present embodiment is not limited thereto.
[0059] In one embodiment of the present embodiment, the doping concentration of the well region 50 per cubic centimeter can be, for example, on the order of 10 to the 17th power, and the doping concentration of the first buffer layer 60 per cubic centimeter can be, for example, on the order of 10 to the 15th to 16th power. The doping concentration of the first source region 41 and the second source region 42 per cubic centimeter can be, for example, on the order of 10 to the 19th power, and the doping concentration of the epitaxial layer 10 per cubic centimeter can be, for example, on the order of 10 to the 13th to 15th power. In one specific embodiment of the present embodiment, the thickness of the first buffer layer 60 in the third direction Z can be, for example, 0.5 to 5 μm.
[0060] By implementing the method for manufacturing the field effect transistor provided by the present embodiment, at least the field effect transistor 100 as shown in Figure 1 By changing the mask pattern in the corresponding steps, the method for manufacturing the field effect transistor provided by the present embodiment can obtain any one of the field effect transistors 100 as shown in Figures 1 to 10
[0061] In summary, the method for manufacturing the field effect transistor 100 provided by the present embodiment can achieve the effect of increasing the width of the depletion region by arranging the first buffer layer 60, so that when the field effect transistor 100 is subjected to a reverse bias voltage, the movement of free electrons in the gate oxide under region 101 to the drain direction can be slowed down, thereby reducing the risk of breakdown of the oxide layer 20 and improving the pressure resistance of the field effect transistor 100, thereby increasing the reliability of the field effect transistor 100.
[0062] In addition, it can be understood that the foregoing various embodiments are only exemplary descriptions of the present application, and under the premise that technical features do not conflict, structures are not contradictory, and do not deviate from the purpose of the application, the technical solutions of various embodiments can be arbitrarily combined and used.
[0063] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A field effect transistor, characterized in that: include: epitaxial layer; An oxide layer is provided on the epitaxial layer, and the epitaxial layer has a sub-gate oxide region located below the oxide layer; a polysilicon layer, disposed on a side of the oxide layer facing away from the epitaxial layer; A first source region and a second source region are respectively arranged on both sides of the region under the gate oxide along a first direction; a well region, disposed outside the first source region and the second source region, wherein upper surfaces of the first source region and the second source region close to the oxide layer are exposed in the well region; as well as A first buffer layer is disposed in the epitaxial layer, and the first buffer layer is disposed on a side of the well region away from the oxide layer, and the first buffer layer extends along the first direction; The doping type of the epitaxial layer, the first source region and the second source region is the first doping type, the doping type of the first buffer layer and the well region is the second doping type, and the doping concentration of the first buffer layer is different from the doping concentration of the well region.
2. The field effect transistor according to claim 1, wherein The first buffer layer includes a plurality of layers, and the plurality of first buffer layers are spaced apart along the second direction.
3. The field effect transistor according to claim 1, wherein The first buffer layer is connected to the well region.
4. The field effect transistor according to claim 1 or 2, characterized in that Also includes: A second buffer layer is arranged in the epitaxial layer, and the second buffer layer is arranged on the side of the well region away from the oxide layer, the second buffer layer extends along the second direction, the doping type of the second buffer layer is a second doping type, and the doping concentration of the second buffer layer is different from the doping concentration of the well region.
5. The field effect transistor according to claim 4, wherein In the third direction, a distance between the first buffer layer and the well region is the same as a distance between the second buffer layer and the well region.
6. The field effect transistor according to claim 5, wherein The second buffer layers include two, the two second buffer layers are spaced apart and arranged at opposite ends of the first buffer layer along the first direction, and the first buffer layer connects the two second buffer layers.
7. The field effect transistor according to claim 2, wherein Also includes: A third buffer layer is arranged between multiple first buffer layers. The doping type of the third buffer layer is the second doping type. The doping concentration of the third buffer layer is different from the doping concentration of the well region, and the doping concentration of the third buffer layer is different from the doping concentration of the first buffer layer.
8. The field effect transistor according to claim 1, wherein The thickness of the first buffer layer is in the range of 0.5 to 5 μm; and / or the doping concentration of the first buffer layer is lower than the doping concentration of the well region.
9. A method for preparing a field effect transistor, characterized in that: include: generating an epitaxial layer; generating a first buffer layer in the epitaxial layer along a first direction; Generating two well regions spaced apart on the epitaxial layer, forming a sub-gate oxide region between the two well regions, and the doping concentration of the first buffer layer is different from the doping concentration of the well regions; generating a first source region and a second source region on the well region; forming an oxide layer on a side of the region under the gate oxide away from the epitaxial layer; as well as A polysilicon layer is formed on a side of the oxide layer facing away from the epitaxial layer.
10. The method for preparing a field effect transistor according to claim 9, wherein: When the first buffer layer is generated in the epitaxial layer along the first direction, the method further includes: A second buffer layer is generated in the epitaxial layer along a second direction, wherein the doping concentration of the second buffer layer is different from the doping concentration of the well region.
Citation Information
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