Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device (1, 2) includes a compound semiconductor layer (15, 115) having a first compound semiconductor layer (14, 114) and a second compound semiconductor layer (16, 116) having a melting point higher than the first compound semiconductor layer; and an insulated gate (40, 140) located on the second compound semiconductor layer. The compound semiconductor layer further includes a drift region (22, 122), a source region (25, 125), and a body region (24, 124) between the drift region and the source region. The insulated gate faces the body region. The body region bridges both the first compound semiconductor layer and the second compound semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] In nitride semiconductors and compound semiconductors such as gallium oxide, it can be difficult to form highly active p-type diffusion regions. For example, in the case of nitride semiconductors, heat treatment at 1200°C or higher is required to activate the p-type dopant. However, when such high-temperature heat treatment is performed, nitrogen may be released from the surface of the nitride semiconductor layer, and pits may form on the surface of the nitride semiconductor layer. Therefore, high-temperature heat treatment may not be performed, and it may be difficult to form highly active p-type diffusion regions.

[0003] Patent document 1 discloses a technique for forming a cap layer made of a high-melting-point material, such as aluminum nitride, on a nitride semiconductor layer. By using such a cap layer, high-temperature heat treatment can be performed while nitrogen leakage is suppressed, thereby enabling the formation of a highly active p-type diffusion region.

[0004] Existing technical documents

[0005] [Patent Documents]

[0006] Patent Document 1: JP-2017-108080-A Summary of the Invention

[0007] In techniques using capping layers, the capping layer is removed by etching after a high-temperature heat treatment. However, etching may be insufficient, leaving capping layer residue. In particular, if capping layer residue remains in the channel region, there is a concern that the threshold voltage may be reduced because the capping layer is n-type or i-type.

[0008] The semiconductor device disclosed in this disclosure includes: a compound semiconductor layer having a first compound semiconductor layer and a second compound semiconductor layer; and an insulating gate disposed on the second compound semiconductor layer. In the compound semiconductor layer, the second compound semiconductor layer is disposed on the first compound semiconductor layer and has a higher melting point than the first compound semiconductor layer. The compound semiconductor layer includes: a drift region having a first conductivity type; a source region having the first conductivity type; and a body region having a second conductivity type, disposed between the drift region and the source region at a location where the body region is exposed on the upper surface of the compound semiconductor layer. The insulating gate faces the body region located between the drift region and the source region. The body region located between the drift region and the source region is arranged to bridge both the first compound semiconductor layer and the second compound semiconductor layer.

[0009] In the semiconductor device, a second compound semiconductor layer remains, serving as a capping layer. However, in the semiconductor device, the body region, i.e., the channel region located between the drift region and the source region, is formed to span both the first and second compound semiconductor layers. Therefore, even with the remaining second compound semiconductor layer serving as a capping layer, the second compound semiconductor layer is configured as a channel region, thereby suppressing the decrease in the threshold voltage of the semiconductor device.

[0010] The method for manufacturing a semiconductor device disclosed in this disclosure includes: a first step of preparing a compound semiconductor layer comprising a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a first conductivity type or type I, wherein, in the first step, the second compound semiconductor layer is disposed on the first compound semiconductor layer and has a higher melting point than the first compound semiconductor layer; a second step of implanting impurity ions of a second conductivity type into an upper portion of the compound semiconductor layer to form a host region, wherein, in the second step, the host region is disposed between a drift region having a first conductivity type and a source region having a first conductivity type, and is arranged to bridge both the first compound semiconductor layer and the second compound semiconductor layer; a third step of heat-treating the compound semiconductor layer after performing the second step; and a fourth step of forming an insulating gate on the second compound semiconductor layer, the insulating gate facing the host region located between the drift region and the source region.

[0011] In the above manufacturing method, the main region, i.e., the channel region, located between the drift region and the source region, is formed in a second compound semiconductor layer serving as a capping layer, and the insulating gate is formed on the second compound semiconductor layer without removing the second compound semiconductor layer. Therefore, in the above manufacturing method, since the second nitride semiconductor layer can be configured as a channel region, a semiconductor device can be manufactured while suppressing the decrease in threshold voltage even if the second compound semiconductor layer serving as a capping layer remains. Attached Figure Description

[0012] The above and other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings:

[0013] Figure 1 This is a schematic cross-sectional view of a portion of a semiconductor device according to an embodiment of the present disclosure;

[0014] Figure 2 It is shown Figure 1 A diagram of the manufacturing process of a part of a semiconductor device;

[0015] Figure 3 It is a schematic illustration of the materials used in manufacturing. Figure 1 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0016] Figure 4 It is a schematic illustration of the materials used in manufacturing. Figure 1 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0017] Figure 5 It is a schematic illustration of the materials used in manufacturing. Figure 1 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0018] Figure 6 This is a schematic cross-sectional view of a portion of another semiconductor device according to one embodiment of the present disclosure;

[0019] Figure 7 It is shown Figure 6 A diagram of the manufacturing process of a part of a semiconductor device;

[0020] Figure 8 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0021] Figure 9 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0022] Figure 10 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device;

[0023] Figure 11 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the main parts of the manufacturing process of a semiconductor device; and

[0024] Figure 12 It is a schematic illustration of the materials used in manufacturing. Figure 6 A cross-sectional view of the main parts of the process for manufacturing a semiconductor device. Detailed Implementation

[0025] In the following description, the semiconductor device and its manufacturing method disclosed herein will be described with reference to the accompanying drawings. In each drawing, for clarity of illustration, a common component may be designated by reference to only one of them.

[0026] (First Embodiment)

[0027] like Figure 1 As shown, the semiconductor device 1 includes a compound semiconductor substrate 12, a compound semiconductor layer 15, a drain electrode 32 disposed to cover the lower surface of the compound semiconductor substrate 12, a source electrode 34 disposed to cover a portion of the upper surface of the compound semiconductor layer 15, and a planar type insulation gate 40 disposed to cover a portion of the upper surface of the compound semiconductor layer 15.

[0028] The compound semiconductor substrate 12 is not particularly limited, but can be, for example, a gallium nitride (GaN) substrate. As described later, the compound semiconductor substrate 12 is the base substrate for epitaxially growing the compound semiconductor layer 15. Additionally, the compound semiconductor substrate 12 contains a high concentration of n-type doping and is also part of the drain region 21. The n-type doping is not particularly limited, but can be, for example, silicon. The drain region 21 has a 2-ohm contact with the drain electrode 32.

[0029] The compound semiconductor layer 15 is disposed in contact with the upper surface of the compound semiconductor substrate 12 and is formed by stacking a first compound semiconductor layer 14 and a second compound semiconductor layer 16. The dashed lines in the figures represent the interface between the first compound semiconductor layer 14 and the second compound semiconductor layer 16. The compound semiconductor layer 15 is not particularly limited, but can be made of, for example, a nitride semiconductor. As an example, the first compound semiconductor layer 14 can be a gallium nitride layer (i.e., a GaN layer), and the second compound semiconductor layer 16 can be an aluminum nitride layer (i.e., an AlN layer). The first compound semiconductor layer 14 is disposed in contact with the upper surface of the compound semiconductor substrate 12 and is located between the compound semiconductor substrate 12 and the second compound semiconductor layer 16. The second compound semiconductor layer 16 is disposed in contact with the upper surface of the first compound semiconductor layer 14 and is located at a position exposed on the upper surface of the compound semiconductor layer 15.

[0030] The compound semiconductor layer 15 has n-type drift regions 22 and p-type drift regions 22. - Body region 24, n + Source region 25 and p + Contact area 26 of the main body.

[0031] Drift region 22 is configured to contact the upper surface of drain region 21 and is disposed between drain region 21 and body region 24. Drift region 22 also has a JFET region 23 configured to be sandwiched between body regions 24 in a planar direction of compound semiconductor layer 15. In other words, JFET region 23 is the portion of drift region 22 configured to extend from the upper surface of compound semiconductor layer 15 through body region 24. JFET region 23 is disposed at a location exposed on the upper surface of compound semiconductor layer 15 and contacts insulating gate 40. JFET region 23 is arranged to span both first compound semiconductor layer 14 and second compound semiconductor layer 16. Drift region 22 contains n-type doping with a lower concentration than drain region 21. The n-type doping is not particularly limited but can be, for example, silicon.

[0032] The body region 24 is configured to contact the upper surface of the drift region 22 and is disposed adjacent to the side surface of the JFET region 23. A portion of the body region 24 is disposed at a location exposed on the upper surface of the compound semiconductor layer 15 and is in contact with the insulating gate 40. A portion of the body region 24 is arranged to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16. The body region 24 contains p-type doping. The p-type doping is not particularly limited, but can be, for example, magnesium.

[0033] Source region 25 is configured to contact the upper surface of body region 24 and is separated from drift region 22 by body region 24. Source region 25 is located at a position exposed on the upper surface of compound semiconductor layer 15 and is in contact with insulating gate 40. Source region 25 is arranged across both first compound semiconductor layer 14 and second compound semiconductor layer 16. Source region 25 contains n-type dopant at a higher concentration than drift region 22. The n-type dopant is not particularly limited but can be, for example, silicon. Source region 25 is in ohmic contact with source electrode 34.

[0034] The main contact region 26 is configured to contact the upper surface of the main region 24. The main contact region 26 is located at an exposed position on the upper surface of the compound semiconductor layer 15 and is arranged to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16. The main contact region 26 contains a higher concentration of p-type dopant than the main region 24. The p-type dopant is not particularly limited, but can be, for example, magnesium. The main contact region 26 is in ohmic contact with the source electrode 34.

[0035] The insulating gate 40 is configured to contact a portion of the upper surface of the second compound semiconductor layer 16 of the compound semiconductor layer 15, and has a silicon oxide gate insulating film 42 and a polysilicon gate electrode 44. The gate electrode 44 faces the body region 24 via the gate insulating film 42 at the location where the JFET region 23, which is part of the drift region 22, is separated from the source region 25.

[0036] Next, the operation of semiconductor device 1 will be described. In use, for example, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the channel region, specifically in the portion of the body region 24 that separates the JFET region 23 from the source region 25. Electrons flow from the source region 25 into the JFET region 23 via the inversion layer formed in the channel region. The electrons flowing into the JFET region 23 flow vertically through the JFET region 23 and the drift region 22, and towards the drain electrode 32. As a result, the drain electrode 32 and the source electrode 34 become conductive, and semiconductor device 1 turns on. When the gate electrode 44 is grounded, the inversion layer disappears, and semiconductor device 1 turns off. Thus, semiconductor device 1 can perform switching operations between the drain electrode 32 and the source electrode 34 based on the voltage applied to the gate electrode 44.

[0037] (Manufacturing method of semiconductor device 1)

[0038] Figure 2 This is a manufacturing process that illustrates a portion of the steps used to manufacture semiconductor device 1. Figures 3 to 5 It corresponds to Figure 2 Cross-sectional views of the main parts of the manufacturing process.

[0039] First, such as Figure 3 As shown, using epitaxial growth technology, a first compound semiconductor layer 14 is grown from the upper surface crystal of a compound semiconductor substrate 12, and further, a second compound semiconductor layer 16 is grown from the upper surface crystal of the first compound semiconductor layer 14 to form a compound semiconductor layer 15 (on...). Figure 2 (Step S1). The first compound semiconductor layer 14 is formed by crystal growth to include n-type doping. The second compound semiconductor layer 16 can be formed by crystal growth to include n-type doping, or it can be formed by crystal growth without doping. The thickness of the second compound semiconductor layer 16 is 15 nm or less. When the thickness of the second compound semiconductor layer 16 is 15 nm or less, it is possible to prevent the second compound semiconductor layer 16 from breaking due to the lattice constant difference between the first compound semiconductor layer 14 (in this example, the GaN layer) and the second compound semiconductor layer 16 (in this example, the AlN layer), thereby forming a high-quality second compound semiconductor layer 16.

[0040] Next, as Figure 4As shown, using ion implantation technology, p-type or n-type dopant is injected into a predetermined region in the upper portion of the compound semiconductor layer 15 to form the host region 24, the source region 25, and the host contact region 26 (in Figure 2 (Step S2 in the process). The order in which these semiconductor regions 24, 25, and 26 are formed is not particularly restricted. The dopant used to form these semiconductor regions 24, 25, and 26 is injected across both the first compound semiconductor layer 14 and the second compound semiconductor layer 16. When the second compound semiconductor layer 16 is i-type (i.e., intrinsic type), n-type dopant can be injected into the portion of the second compound semiconductor layer 16 corresponding to the JFET region 23.

[0041] Next, a heat treatment is performed to activate these semiconductor regions 24, 25, and 26 (in... Figure 2 (Step S3 in the process). The temperature of the heat treatment is not particularly limited, but can be, for example, 1200°C or higher. Through such high-temperature heat treatment, the injected dopant (which is p-type doping), especially magnesium, can be satisfactorily activated. Further, the second compound semiconductor layer 16 (in this example, the AlN layer) is made of a material whose melting point is higher than that of the first compound semiconductor layer 14 (in this example, the GaN layer). Therefore, the second compound semiconductor layer 16 can serve as a capping layer to suppress nitrogen leakage from the upper surface of the compound semiconductor layer 15 and to suppress the formation of pits on the upper surface of the compound semiconductor layer 15.

[0042] Next, as Figure 5 As shown, an insulating gate 40 is formed on the compound semiconductor layer 15. Figure 2 Step S4). Specifically, the gate insulating film 42 is formed on the upper surface of the second compound semiconductor layer 16 covering the compound semiconductor layer 15 using a vapor deposition technique. The vapor deposition technique is not particularly limited, but atomic layer deposition (ALD) or plasma CVD can be used. Next, a heat treatment technique is performed to improve the film quality of the gate insulating film 42. The heat treatment temperature can be 800°C or higher. Next, the gate electrode 44 is formed on the upper surface of the gate insulating film 42 using a vapor deposition technique. Furthermore, the gate insulating film 42 and the gate electrode 44 are processed using an etching technique to form an insulating gate 40. Afterwards, Figure 1 The semiconductor device 1 shown can be manufactured by forming the drain electrode 32 and the source electrode 34 using known manufacturing techniques.

[0043] In conventional manufacturing methods using capping layers, an n-type or i-type capping layer is formed after ion implantation into a compound semiconductor layer. A heat treatment for activation is then performed. After the heat treatment, the capping layer is removed, and an insulating gate is formed on the compound semiconductor layer where the capping layer has been removed. In such conventional manufacturing methods, there is a concern that the threshold voltage may decrease if an n-type or i-type capping layer remains in the channel region. Furthermore, if CMP technology is used to eliminate capping layer residue, there are concerns about increased costs and potential damage to the channel region.

[0044] In the manufacturing method disclosed herein, a diffusion region is also formed in the second compound semiconductor layer 16, which serves as a capping layer, and an insulating gate 40 is formed on the second compound semiconductor layer 16 without removing the second compound semiconductor layer 16. Specifically, in this manufacturing method, the body region, i.e., the channel region at the location separating the drift region 22 and the source region 25, is formed to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16. Therefore, in this manufacturing method, a portion of the second compound semiconductor layer 16 can be configured as a channel region, thereby enabling the fabrication of a semiconductor device 1 in which a reduction in threshold voltage is suppressed, even if the second compound semiconductor layer 16 serving as a capping layer remains.

[0045] (Second Embodiment)

[0046] Figure 6 Semiconductor device 2 is shown, which is Figure 1 The semiconductor device 1 shown is a modification. For comparison with... Figure 1 The semiconductor device 1 shown has common components. "1" can be added to the hundreds place, and the description of these components can be omitted to avoid repetition.

[0047] like Figure 6 As shown, the semiconductor device 2 is characterized by including a trench-type insulating gate 140 disposed in a trench TR formed on the upper surface of the compound semiconductor layer 115. Figure 1 Similar to the semiconductor device 1 shown, the compound semiconductor substrate 112 is a gallium nitride substrate (i.e., GaN substrate), the first compound semiconductor layer 114 is a gallium nitride layer (i.e., GaN layer), and the second compound semiconductor layer 116 is an aluminum nitride layer (i.e., AlN layer).

[0048] The compound semiconductor layer 115 is formed by stacking a first compound semiconductor layer 114 and a second compound semiconductor layer 116. The dashed lines shown in the figures represent the interface between the first compound semiconductor layer 114 and the second compound semiconductor layer 116. The first compound semiconductor layer 114 is disposed in contact with the upper surface of the compound semiconductor substrate 112 and is located between the compound semiconductor substrate 112 and the second compound semiconductor layer 116. The second compound semiconductor layer 116 is disposed in contact with the upper surface of the first compound semiconductor layer 114 and is located at a position exposed on the upper surface of the compound semiconductor layer 115. In this specification, the side and bottom surfaces of the trench TR are also included in the upper surface of the compound semiconductor layer 115.

[0049] The compound semiconductor layer 115 includes n-type drift regions 122 and p-type drift regions 122. - Type main area 124, n + Source region 125, p + Type main body contact area 126 and p - Type of electric field relaxation region 127.

[0050] Drift region 122 is configured to contact the upper surface of drain region 121 and is disposed between drain region 121 and body region 124. A portion of drift region 122 is disposed at a location exposed at the corner between the side surface and bottom surface of trench TR and contacts the side surface and bottom surface of insulating gate 140. Drift region 122 is arranged across both the first compound semiconductor layer 14 and the second compound semiconductor layer 16 at the location exposed at the corner between the side surface and bottom surface of trench TR.

[0051] The main body region 124 is configured to contact the upper surface of the drift region 122. A portion of the main body region 124 is located at a position exposed on the side surface of the trench TR and contacts the side surface of the insulating gate 140. The main body region 124 exposed on the side surface of the trench TR is arranged to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16.

[0052] The source region 125 is configured to contact the upper surface of the body region 124 and is separated from the drift region 122 through the body region 124. The source region 125 is located at a position exposed on the side surface of the trench TR and contacts the side surface of the insulating gate 140. The source region 125 is arranged to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16.

[0053] The main contact area 126 is configured to contact the upper surface of the main area 124. The main contact area 126 is located at a position exposed on the upper surface of the compound semiconductor layer 115 and is arranged to span both the first compound semiconductor layer 114 and the second compound semiconductor layer 116.

[0054] An electric field relaxation region 127 is located on the exposed bottom surface of the trench TR and contacts the bottom surface of the insulating gate 140. The electric field relaxation region 127 is disposed between the insulating gate 140 and the drift region 122 and is configured to relax the electric field on the bottom surface of the insulating gate 140. The electric field relaxation region 127 is arranged to span both the first compound semiconductor layer 114 and the second compound semiconductor layer 116. The electric field relaxation region 127 contains the same degree of p-type doping as the body region 124. The p-type doping is not particularly limited but can be, for example, magnesium.

[0055] An insulating gate 140 is disposed in a trench TR and has a silicon oxide gate insulating film 142 and a polysilicon gate electrode 144. The gate insulating film 142 is configured to cover the side and bottom surfaces of the trench TR. The gate electrode 144 is separated from the compound semiconductor layer 115 by the gate insulating film 142 and faces the body region 124 via the gate insulating film 142 at the location where the drift region 122 and the source region 125 are separated.

[0056] Next, the operation of semiconductor device 2 will be described. In use, for example, a positive voltage is applied to the drain electrode 132, and the source electrode 134 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 144, an inversion layer is formed in the main region 124, i.e., the channel region, separating the drift region 122 and the source region 125. Electrons flow from the source region 125 into the drift region 122 via the inversion layer formed in the channel region. The electrons flowing into the drift region 122 flow vertically through the drift region 122 and towards the drain electrode 132. As a result, the drain electrode 132 and the source electrode 134 become conductive, and semiconductor device 2 is turned on. When the gate electrode 144 is grounded, the inversion layer disappears, and semiconductor device 2 is turned off. Thus, semiconductor device 2 can perform on-off switching operations between the drain electrode 132 and the source electrode 134 based on the voltage applied to the gate electrode 144.

[0057] (Manufacturing method of semiconductor device 2)

[0058] Figure 7 This is a manufacturing process that shows a portion of the steps used to manufacture semiconductor device 2. Figures 8 to 12 Is with Figure 7 The manufacturing process corresponds to a cross-sectional view of the main parts of the manufacturing process.

[0059] First, such as Figure 8As shown, a first compound semiconductor layer 114 is crystally grown from the upper surface of a compound semiconductor substrate 112 using an epitaxial growth technique. Figure 7 (Step S11). The first compound semiconductor layer 14 is formed by crystal growth to contain n-type doping.

[0060] Next, as Figure 9 As shown, trenches TR extending from the upper surface of the first compound semiconductor layer 114 to the depth of the first compound semiconductor layer 114 are formed using photolithography and etching techniques. Figure 7 Step S12 in the process.

[0061] Next, as Figure 10 As shown, a second compound semiconductor layer 116 is crystally grown from the upper surface of the first compound semiconductor layer 114 using an epitaxial growth technique to form a compound semiconductor layer 115 (in... Figure 7 (Step S13). A second compound semiconductor layer 116 is also formed in the trench TR. The second compound semiconductor layer 116 can be formed by crystal growth to include n-type doping, or it can be formed by crystal growth to be undoped. The thickness of the second compound semiconductor layer 116 is 15 nm or less. When the thickness of the second compound semiconductor layer 116 is 15 nm or less, it is possible to prevent the second compound semiconductor layer 116 from cracking due to the lattice constant difference between the first compound semiconductor layer 114 (GaN layer in this example) and the second compound semiconductor layer 116 (AlN layer in this example), thereby forming a high-quality second compound semiconductor layer 116.

[0062] Next, as Figure 11 As shown, using ion implantation technology, p-type or n-type dopant is injected into a predetermined region on the upper portion of the compound semiconductor layer 115 to form a host region 124, a source region 125, a host contact region 126, and an electric field relaxation region 127 (in Figure 7 (Step S14). The order in which these semiconductor regions 124, 125, 126, and 127 are formed is not particularly restricted. The dopant used to form these semiconductor regions 124, 125, 126, and 127 is injected across both the first compound semiconductor layer 114 and the second compound semiconductor layer 116.

[0063] Next, a heat treatment is performed to activate these semiconductor regions 124, 125, 126, and 127 (in... Figure 7(Step S15 in the process). The temperature of the heat treatment is not particularly limited, but can be, for example, 1200°C or higher. Through such high-temperature heat treatment, the injected dopant (which is a p-type dopant), especially magnesium, can be satisfactorily activated. Furthermore, the second compound semiconductor layer 116 (in this example, the AlN layer) is made of a material whose melting point is higher than that of the first compound semiconductor layer 114 (in this example, the GaN layer). Therefore, the second compound semiconductor layer 116 can serve as a capping layer to suppress nitrogen leakage from the upper surface of the compound semiconductor layer 115 and to suppress the formation of pits on the upper surface of the compound semiconductor layer 115.

[0064] Next, as Figure 12 As shown, an insulating gate 140 is formed on the compound semiconductor layer 115, and the insulating gate 140 is arranged in the trench TR (in Figure 7 Step S16 in the process. Specifically, a gate insulating film 142 is formed using thin-film deposition to cover the upper surface of the second compound semiconductor layer 116, including the inner side of the trench TR. Next, a gate electrode 144 is formed on the upper surface of the gate insulating film 142 using vapor deposition. Furthermore, the gate insulating film 142 and the gate electrode 144 are processed using etching to form an insulating gate 140 in the trench TR. Afterwards, as... Figure 7 The semiconductor device 2 shown can be manufactured by forming the drain electrode 132 and the source electrode 134 using known manufacturing techniques.

[0065] Similarly, in this manufacturing method, the portion of the main body region 124 that serves as the channel region is formed to span both the first compound semiconductor layer 14 and the second compound semiconductor layer 16. Therefore, in this manufacturing method, a portion of the second compound semiconductor layer 116 can be configured as the channel region, thereby enabling the manufacture of a semiconductor device 2 in which the reduction of the threshold voltage is suppressed, even if the second compound semiconductor layer 116 used as a capping layer remains.

[0066] The features of the technology disclosed in this disclosure are summarized below. It should be noted that the technical features described below are independent technical features, which individually or in various combinations contribute to technical usefulness, and are not limited to the combinations described in this specification at the time of filing.

[0067] The semiconductor device disclosed in this disclosure includes: a compound semiconductor layer having a first compound semiconductor layer and a second compound semiconductor layer; and an insulating gate disposed on the second compound semiconductor layer, wherein the second compound semiconductor layer is disposed on the first compound semiconductor layer and has a higher melting point than the first compound semiconductor layer. The material of the compound semiconductor layer is not particularly limited and can be, for example, a semiconductor nitride or gallium oxide. When the material of the compound semiconductor layer is a semiconductor nitride, the material of the first compound semiconductor layer can be gallium nitride, and the material of the second compound semiconductor layer can be aluminum nitride. The compound semiconductor layer includes: a drift region having a first conductivity type; a source region having a first conductivity type; and a body region having a second conductivity type disposed between the drift region and the source region, at a location on the upper surface of the compound semiconductor layer exposing the body region. The insulating gate faces the body region located between the drift region and the source region. The body region located between the drift region and the source region is arranged to bridge both the first and second compound semiconductor layers.

[0068] In the aforementioned semiconductor device, when the material of the first compound semiconductor layer is gallium nitride and the material of the second compound semiconductor layer is aluminum nitride, the thickness of the second compound semiconductor layer can be 15 nm or less.

[0069] The insulating gate of the semiconductor device can be planar or trench type. When the insulating gate is planar, the drift region is disposed at a location exposed on the upper surface of the compound semiconductor layer, and the first conductivity type JFET region can be disposed adjacent to the body region. In this case, the insulating gate can face the body region located between the JFET region and the source region. When the insulating gate is trench type, a trench (TR) can be formed on the upper surface of the compound semiconductor layer. The body region located between the drift region and the source region can be disposed at a location exposed on the side surface of the trench. In this case, the insulating gate can be disposed in the trench.

[0070] The method for manufacturing a semiconductor device disclosed in this disclosure includes: a first step: preparing a compound semiconductor layer comprising a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a first conductivity type or type I, wherein, in the first step, the second compound semiconductor layer is disposed on the first compound semiconductor layer, and the second compound semiconductor layer has a higher melting point than the first compound semiconductor layer; a second step: implanting impurity ions of a second conductivity type into an upper portion of the compound semiconductor layer to form a host region, wherein, in the second step, the host region is arranged between a drift region having a first conductivity type and a source region having a first conductivity type, and is arranged to bridge both the first and second compound semiconductor layers; a third step: after performing the second step, subjecting the compound semiconductor layer to a heat treatment; and a fourth step: forming an insulating gate on the second compound semiconductor layer, the insulating gate facing the host region located between the drift region and the source region. The material of the compound semiconductor layer is not particularly limited and can be, for example, a semiconductor nitride or gallium oxide. When the material of the compound semiconductor layer is a semiconductor nitride, the material of the first compound semiconductor layer can be gallium nitride, and the material of the second compound semiconductor layer can be aluminum nitride.

[0071] In the manufacturing method of semiconductor devices, when the material of the first compound semiconductor layer is gallium nitride and the material of the second compound semiconductor layer is aluminum nitride, the thickness of the second compound semiconductor layer can be 15 nm or less. When the thickness of the second compound semiconductor layer is 15 nm or less, due to the influence of the lattice constant difference between the first and second compound semiconductor layers, the cracking in the second compound semiconductor layer is suppressed, and the second compound semiconductor layer is formed with good quality.

[0072] In methods for manufacturing semiconductor devices, when the material of the compound semiconductor layer is a nitride semiconductor, the heat treatment temperature in the third step can be 1200°C or higher. Doping can be effectively activated.

[0073] In the above manufacturing method, the first step may include: growing a first compound semiconductor layer from the surface crystal of the compound semiconductor substrate; and growing a second compound semiconductor layer from the surface crystal of the first compound semiconductor layer. The second compound semiconductor layer, serving as a capping layer, may be formed prior to ion implantation.

[0074] Although specific examples of this disclosure have been described in detail above, these specific examples are merely illustrative and do not limit the scope of this description. The technology described in this specification includes various modifications and variations of the above-described specific examples. Furthermore, the technical features described in this specification or drawings are technically useful individually or in various combinations, and are not limited to the combinations described in this specification at the time of filing. Moreover, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A semiconductor device comprising: a compound semiconductor layer having a first compound semiconductor layer and a second compound semiconductor layer disposed on the first compound semiconductor layer and having a higher melting point than the first compound semiconductor layer; and an insulating gate disposed on the second compound semiconductor layer, wherein: the compound semiconductor layer further comprises: a drift region having a first conductivity type; a source region having the first conductivity type; and a body region having a second conductivity type disposed between the drift region and the source region and disposed at a position exposed on an upper surface of the compound semiconductor layer; the insulating gate faces the body region between the drift region and the source region; and the body region between the drift region and the source region is disposed to bridge both the first compound semiconductor layer and the second compound semiconductor layer.

2. The semiconductor device according to claim 1, wherein: a material of the compound semiconductor layer is a nitride semiconductor.

3. The semiconductor device according to claim 2, wherein: a material of the first compound semiconductor layer is gallium nitride; and a material of the second compound semiconductor layer is aluminum nitride.

4. The semiconductor device according to claim 3, wherein: a thickness of the second compound semiconductor layer is 15 nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein: the drift region is disposed at a position exposed on an upper surface of the compound semiconductor layer and has a JFET region having a first conductivity type and disposed adjacent to the body region; and the insulating gate is of a planar type and faces the body region between the JFET region and the source region.

6. The semiconductor device according to any one of claims 1 to 4, further comprising: a trench (TR) disposed on an upper surface of the compound semiconductor layer, wherein: the body region between the drift region and the source region is disposed at a position exposed on a side surface of the trench; and the insulating gate is of a trench type and disposed in the trench.

7. A method for manufacturing a semiconductor device, comprising: a first step of preparing a compound semiconductor layer including a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having the first conductivity type or an i-type, wherein, in the first step, the second compound semiconductor layer is disposed on the first compound semiconductor layer and has a higher melting point than the first compound semiconductor layer; a second step of implanting an impurity ion of a second conductivity type into an upper layer portion of the compound semiconductor layer to form a body region, wherein, in the second step, the body region is disposed between a drift region having the first conductivity type and a source region having the first conductivity type and is disposed to bridge both the first compound semiconductor layer and the second compound semiconductor layer; a third step of, after the second step is performed, subjecting the compound semiconductor layer to heat treatment; and a fourth step of, after the third step is performed, forming an insulating gate on the second compound semiconductor layer. Fourth step: forming an insulating gate on the second compound semiconductor layer, the insulating gate facing the body region between the drift region and the source region.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: the material of the compound semiconductor layer is a nitride semiconductor.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: the material of the first compound semiconductor layer is gallium nitride (GaN); and the material of the second compound semiconductor layer is aluminum nitride (AIN).

10. The method for manufacturing a semiconductor device according to claim 9, wherein: the thickness of the second compound semiconductor layer is 15 nm or less.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: the heat treatment temperature in the third step is 1200 °C or more.

12. The method for manufacturing a semiconductor device according to any one of claims 7 to 11, wherein: the first step includes: a stage in which the first compound semiconductor layer is crystal-grown from the surface of the compound semiconductor substrate; and a stage in which the second compound semiconductor layer is crystal-grown from the surface of the first compound semiconductor layer.

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