Alignment mark forming method, mask and semiconductor structure

Abstract

The invention discloses a method for forming an alignment mark, a mask plate, and a semiconductor structure, wherein the mask plate includes at least one alignment mask pattern, wherein the alignment mask pattern includes a plurality of first alignment patterns and a plurality of second alignment patterns, wherein the plurality of first alignment patterns and the plurality of second alignment patterns are alternately distributed along a first direction, and each first alignment pattern has a plurality of first mark patterns arranged periodically. According to the mask plate used in the semiconductor self-aligned lithography process of the embodiment of the present invention, the formed alignment mark can avoid forming strong reflected light to interfere with the alignment signal, and the alignment signal is strong and the alignment accuracy is high.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductors, and in particular to a mask plate used in a semiconductor self-alignment lithography process, a method for forming a semiconductor alignment mark, and a semiconductor structure. Background Art

[0002] In the semiconductor structure of the prior art, especially in the film structure formed by the SADP process, the alignment mark is formed on the wafer, and the alignment mark signal is poor, which affects the alignment effect, makes it difficult to control the overlay accuracy, and leads to inaccurate overlay alignment. Summary of the invention

[0003] The object of the present invention is to provide a mask for semiconductor self-alignment lithography process, wherein the alignment mark formed by the mask can avoid the formation of strong reflected light to interfere with the alignment signal, and the alignment signal is strong and the alignment accuracy is high.

[0004] According to an embodiment of the present invention, a mask plate for a semiconductor self-aligned lithography process includes at least one alignment mask pattern, wherein the alignment mask pattern includes a plurality of first alignment patterns and a plurality of second alignment patterns, wherein the plurality of first alignment patterns and the plurality of second alignment patterns are alternately distributed along a first direction, and each of the first alignment patterns has a plurality of first mark patterns arranged periodically.

[0005] According to some embodiments of the present invention, the second alignment pattern has a plurality of second marking patterns, and a pattern density of the first alignment pattern is different from a pattern density of the second alignment pattern.

[0006] According to some embodiments of the present invention, the mask plate used for semiconductor self-aligned lithography process also includes a device area mask pattern, and the graphic width of the second mark pattern and the spacing between adjacent second mark patterns are the same as the graphic width of the device area mask pattern and the spacing between adjacent device area mask patterns.

[0007] According to some embodiments of the present invention, the second marking pattern and the device region pattern of the device region mask pattern extend in the same direction.

[0008] According to some embodiments of the present invention, a pattern density of the first alignment pattern is greater than a pattern density of the second alignment pattern.

[0009] According to some embodiments of the present invention, the graphic width of the second marking pattern is twice the sum of the graphic width of the first marking pattern and the spacing between adjacent first marking patterns, and the spacing between adjacent second marking patterns is the sum of the graphic width of the first marking pattern and the spacing between adjacent first marking patterns.

[0010] According to some embodiments of the present invention, the second marking patterns are arranged at uniform intervals along an extension direction of the second alignment pattern.

[0011] According to some embodiments of the present invention, the alignment mask patterns are a pair, and the pair of alignment mask patterns are formed into axisymmetric patterns.

[0012] The invention also provides a method for forming a semiconductor alignment mark.

[0013] The method for forming a semiconductor alignment mark according to an embodiment of the present invention comprises: forming a semiconductor substrate, wherein an oxide layer is formed on the surface of the semiconductor substrate; forming a mask layer and a photoresist layer on the surface of the oxide layer in sequence; using the mask plate for the semiconductor self-aligned photolithography process of the above embodiment as a mask, exposing and developing the photoresist layer to form a photoresist pattern;

[0014] A first film layer is formed on the surface of the photoresist pattern and the mask layer; a portion of the first film layer located on the top of the photoresist pattern is removed, and the first film layer located on the surface of the photoresist pattern is retained to form a first pattern; the photoresist pattern is removed; the mask layer is etched using the first pattern as a mask; and the oxide layer is continuously etched downward until the semiconductor substrate is exposed to form a second pattern; a metal layer is formed on the surface of the semiconductor substrate, and the metal layer fills the second pattern to form an alignment mark.

[0015] The invention also provides a semiconductor structure.

[0016] A semiconductor structure according to an embodiment of the present invention includes a semiconductor substrate and an alignment mark formed on the surface of the semiconductor substrate, wherein the alignment mark is prepared by the method for forming the semiconductor alignment mark of the above-mentioned embodiment, and the alignment mark includes: a plurality of first alignment figures spaced apart along a first direction, wherein the first alignment figures are formed into a strip shape, each of the first alignment figures includes a plurality of first figures, and the first figures are formed into a hollow rectangle extending along a second direction; a plurality of second alignment figures spaced apart along the first direction, wherein the second alignment figures are formed into a strip shape, each of the second alignment figures includes a plurality of second figures, and the second figures are formed into a hollow rectangular frame extending along the second direction, and the plurality of first alignment figures and the plurality of second alignment figures are alternately distributed at intervals; and a metal layer, wherein the metal layer is formed on the surface of the semiconductor substrate and fills the first alignment figures and the second alignment figures.

[0017] Therefore, according to the mask plate, alignment mark forming method and semiconductor structure used in the semiconductor self-aligned lithography process according to the embodiments of the present invention, the alignment mask pattern of the mask plate includes a first alignment pattern having a plurality of first mark patterns and a second alignment pattern having a plurality of second mark patterns. Therefore, the formed alignment mark can prevent the formation of large continuous metal areas to reduce the reflected light caused by large pieces of metal and reduce signal interference. It can also increase the pattern density and improve the alignment signal. Moreover, the pattern densities of the first alignment pattern and the second alignment pattern are different, so two alignment mark patterns with different densities can be formed to form a clear contrast, thereby reducing the influence of chemical mechanical grinding on the alignment mark and further improving the alignment accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic structural diagram of a mask used in a semiconductor self-aligned lithography process according to an embodiment of the present invention;

[0019] Figure 2-Figure 6 A cross-sectional view of each step of a method for forming a semiconductor alignment mark according to an embodiment of the present invention;

[0020] Figure 7 FIG. 4 is a schematic structural diagram of an alignment mark of a semiconductor structure according to an embodiment of the present invention.

[0021] Reference numerals:

[0022] 100: aligning the mask pattern;

[0023] 11: first alignment pattern, 12: second alignment pattern;

[0024] 21: first marking pattern, 22: second marking pattern;

[0025] 3: Oxide layer;

[0026] 4: mask layer, 41: hard mask layer, 42: hard carbon layer, 43: bottom anti-reflection layer, 44: photoresist pattern;

[0027] 5: first film layer, 51: first pattern;

[0028] 61: second pattern, 62: metal layer;

[0029] 7: alignment mark, 71: first alignment pattern, 72: second alignment pattern, 73: first pattern, 74: second pattern. DETAILED DESCRIPTION

[0030] A semiconductor structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] In the semiconductor structure of the related technology, especially in the SADP (self-aligned double patterning) process, the alignment signal of the alignment mark is poor, which is not conducive to chemical mechanical polishing, affects the symmetry of the alignment mark structure, and increases the difficulty of controlling the overlay alignment during the preparation of the semiconductor structure.

[0032] The inventors have discovered that the alignment mark of the related art is formed by a metal layer and an oxide layer formed between the metal layers. Since the metal layer occupies a large area and is relatively concentrated, while the oxide layer occupies a small area, the entire alignment mark presents a large metal reflection phenomenon, which causes strong reflected light in the photolithography alignment, thereby easily interfering with the alignment signal. Moreover, the metal layer of the alignment mark is generally formed into a large continuous block structure, which makes the pattern density of the alignment mark including multiple metal layers small, which also leads to poor alignment signals.

[0033] Specifically, Figure 3-Figure 6 The figure shows a schematic diagram of the structure of each step of forming an alignment mark by self-alignment imaging, which mainly includes the following steps:

[0034] A semiconductor substrate is provided, an oxide layer 3, such as a silicon oxide layer, is formed on the surface of the semiconductor substrate, a mask layer 4 and a photoresist layer 44 are sequentially formed on the surface of the oxide layer 3, and the photoresist layer is exposed and developed using a mask plate with a self-aligned mark in a self-aligned double imaging lithography process to form a photoresist pattern 44. The photoresist pattern 44 is the same as the graphic pattern of the mask plate. The mask plate pattern of the alignment mark in the related art includes a plurality of continuous strip patterns arranged at intervals.

[0035] like Figure 3 As shown, a first film layer 5 is formed on the surface of the mask layer 4 and the surface of the photoresist pattern 44, and the first film layer 5 covers the upper surface and sidewall of the photoresist pattern 44 and the exposed surface of the mask layer 4, as shown in FIG. Figure 4 As shown, the first film layer 5 located on the upper surface of the photoresist pattern 44 and the first film layer 5 located on the surface of the mask layer 4 are removed, only the first film layer 5 located on the side wall of the photoresist pattern 44 is retained, and the photoresist pattern 44 is removed to form a first pattern 51; as shown Figure 5 As shown, the mask layer 4 is etched with the first pattern 51 as a mask to form a mask pattern, wherein the mask layer can be formed as a composite layer, for example, Figure 2-Figure 5 As shown in FIG. 1 , the mask layer 4 may include a hard mask layer 41, a hard carbon layer 42 and a bottom anti-reflection coating 43 from bottom to top. When etching the mask layer 4, the hard mask layer 41, the hard carbon layer 42 and the bottom anti-reflection coating 43 may be etched in sequence, and the oxide layer 3 may be etched downward to expose the semiconductor substrate to form a second pattern 61. The graphic pattern of the second pattern 61 is the same as the graphic pattern of the first pattern 51. See FIG. Figure 4It can be seen that the first pattern 51 is formed by the first film layer 5 located on the side wall of the photoresist pattern 44, and the photoresist pattern 44 is a continuous strip pattern, so the first pattern 51 forms a plurality of elongated strip shapes, that is, Figure 6 The second pattern 61 shown is formed in a plurality of elongated strip shapes.

[0036] like Figure 6 As shown, a metal layer 62 is formed on the surface of the semiconductor substrate, and the metal layer 62 fills the second pattern 61. The metal layer 62 and the second pattern 61 together form an alignment mark 7. In this way, the metal layer 62 of the alignment mark in the related art forms a continuous large piece of metal between the second pattern 61, resulting in the metal area occupying a larger area and being more densely distributed, which easily causes strong reflected light, thereby interfering with the alignment signal of the alignment mark, resulting in low overlay accuracy and affecting the alignment lithography of the semiconductor structure.

[0037] The present invention proposes a mask for semiconductor self-aligned photolithography. The mask for semiconductor self-aligned photolithography according to an embodiment of the present invention is described below with reference to the accompanying drawings.

[0038] According to an embodiment of the present invention, a mask plate for a semiconductor self-aligned lithography process includes at least one alignment mask pattern 100. The mask plate 100 for a semiconductor self-aligned lithography process is used in a self-aligned double imaging lithography process of an alignment mark in a semiconductor manufacturing process. During the preparation process of a semiconductor structure, multiple deposition and etching steps are required. By forming an alignment mark 7, accurate alignment of each film layer during the preparation process of the semiconductor structure can be achieved. The alignment mark is formed in a cutting path area, which can avoid occupying the area of ​​a device forming area and also avoid affecting the formation of the device area. The mask plate for a semiconductor self-aligned lithography process according to an embodiment of the present invention is used to form an alignment mark.

[0039] like Figure 1 As shown, the alignment mask pattern 100 includes a plurality of first alignment patterns 11 and a plurality of second alignment patterns 12, and the plurality of first alignment patterns 11 and the plurality of second alignment patterns 12 are alternately distributed along a first direction, that is, the first alignment patterns 11 and the second alignment patterns 12 are alternately stacked in the first direction, and the number of the first alignment patterns 11 and the number of the second alignment patterns 12 can be set according to actual needs, which is not limited by the present invention.

[0040] Each first alignment pattern 11 has a plurality of first mark patterns 21 arranged periodically, and the second alignment pattern 12 has a plurality of second mark patterns 22. That is, the first alignment pattern 11 can be formed into a pattern composed of a plurality of first mark patterns 21 and the spacing regions between adjacent first mark patterns 21, and the second alignment pattern 12 can be formed into a pattern composed of a plurality of second mark patterns 22 and the spacing regions between adjacent second mark patterns 22. In this way, the first alignment pattern 11 can be cut into a plurality of first mark patterns 21 spaced apart. When forming alignment marks, for example, Figure 2 When the photoresist pattern 44 is shown, the continuous long strip photoresist pattern 44 can be divided into a plurality of first marking patterns 21. Figure 4 In the steps shown, the first pattern 51 is formed on the side wall of the photoresist pattern 44, and the first pattern 51 can be formed into a plurality of closed graphic patterns wrapping the photoresist pattern 44, thereby increasing the area of ​​the first pattern 51. In this way, when the oxide layer 3 is subsequently etched, the area of ​​the oxide layer in the alignment mark 7 is also increased. Furthermore, when the metal layer 62 is filled, the area occupied by the metal layer 62 is also reduced. Moreover, the metal layer 62 is filled with the oxide layer 3, and the large metal area can also be cut into a plurality of small metal areas, thereby reducing the reflected light caused by the large metal, thereby avoiding interference with the lithography alignment signal, and is also beneficial to chemical mechanical polishing in the preparation process, thereby improving the alignment effect.

[0041] In some embodiments of the present invention, the second alignment pattern 12 may include a plurality of second mark patterns 22, and the plurality of second mark patterns 22 may be periodically and evenly distributed along the extension direction of the second alignment pattern 12, or the second mark patterns 22 may be unevenly distributed along the second alignment pattern 12. In this way, during the formation of the alignment mark 7 through the second alignment pattern 12, a large metal area can also be cut into a small metal area, so as to further reduce the area occupied by the metal area, reduce reflection, and improve the alignment signal strength.

[0042] The pattern density of the first alignment pattern 11 is different from the pattern density of the second alignment pattern 12. Thus, in the subsequent step of forming the alignment mark 7, the alignment mark 7 may include at least two alignment patterns with different pattern densities, for example: Figure 7 As shown, the alignment mark 7 may include a first alignment pattern 71 and a second alignment pattern 72, and the pattern densities of the two alignment patterns of the alignment mark 7 are different and can form a contrast, the pattern densities of the first alignment pattern 11 and the second alignment pattern 12 can form a contrast, and the first alignment pattern 11 and the second alignment pattern 12 can have an obvious contrast, so that the two alignment patterns of the alignment mark 7 have an obvious contrast, and can also further reduce the impact of chemical mechanical polishing on the alignment mark 7 during the preparation of the semiconductor structure and improve the alignment accuracy.

[0043] Therefore, according to the mask for semiconductor self-aligned lithography process according to the embodiment of the present invention, the alignment mask pattern 100 includes a first alignment pattern 11 having a plurality of first mark patterns 21 and a second alignment pattern 12 having a plurality of second mark patterns 22. When the mask for semiconductor self-aligned lithography process of the present invention is used to form alignment marks, it is possible to prevent the formation of large continuous metal areas to reduce reflected light caused by large pieces of metal and reduce signal interference. It is also possible to increase the pattern density and improve the alignment signal. Moreover, the first alignment pattern 11 and the second alignment pattern 12 have different pattern densities and can form a significant contrast, thereby reducing the influence of chemical mechanical polishing on the alignment marks and further improving the alignment accuracy.

[0044] In some embodiments of the present invention, the first alignment pattern 11 and the second alignment pattern 12 are both formed into a strip extending in a perpendicular first direction, and the first mark pattern 21 and the second mark pattern 22 are both formed into a strip extending in a second direction, and the second direction intersects with the direction perpendicular to the first direction. That is, the first mark pattern 21 extends in the second direction, and the second mark pattern 22 extends in the second direction, and the extension direction of the first mark pattern 21 is different from the extension direction of the first alignment pattern 11 and forms a certain angle, and the extension direction of the second mark pattern 22 is different from the extension direction of the second alignment pattern 12 and forms a certain angle, and a plurality of first mark patterns 21 are arranged at intervals along the extension direction of the first alignment direction, and a plurality of second mark patterns 22 are arranged at intervals along the extension direction of the second alignment pattern 12, so that the first mark pattern 21 and the second mark pattern 22 can be formed into a short strip-shaped pattern, which is conducive to the formation of the first mark pattern 21 and the second mark pattern 22, and when forming the alignment mark, a metal area with a large continuous area can also be divided into a plurality of small metal areas.

[0045] Optionally, a plurality of first marking patterns 21 may be evenly spaced along the extension direction of the first alignment pattern 11 and fill the first alignment pattern 11, and a plurality of second marking patterns 22 may be evenly spaced along the extension direction of the second alignment pattern 12 and fill the second marking pattern 22. Specifically, for example, the first alignment pattern 11 is formed into a generally long strip along a first direction perpendicular to the first direction, the first marking pattern 21 may be formed into a filling unit that fills the long strip-shaped first alignment pattern 11, and the second marking pattern 22 may be formed into a filling unit that fills the second alignment pattern 12.

[0046] Furthermore, the lengths of the plurality of first alignment patterns 11 may be the same or different, the lengths of the plurality of second alignment patterns 12 may be the same or different, and the lengths and shapes of the first alignment patterns 11 and the second alignment patterns 12 may be set according to the shape of the actual alignment mask pattern 100. Figure 1In the example shown, there is a pair of alignment mask patterns 100, and the pair of alignment mask patterns 100 are formed into an axially symmetrical figure. Specifically, on the top view plane of the two alignment mask patterns 100, the overall outer contours of the two alignment mask patterns 100 are formed into a rectangle, and the two alignment mask patterns 100 are axially symmetrical about adjacent short sides, and the first alignment pattern 11 and the second alignment pattern 12 in each alignment mask pattern 100 fill the rectangle.

[0047] It is understandable that the first marking pattern 21 and the second marking pattern 22 can have various shapes and spacing distances, and can be evenly distributed or unevenly distributed, as long as the corresponding segmentation and addition functions are met. For example, the first marking pattern 21 and the second marking pattern 22 can also be formed in an S shape.

[0048] In some embodiments of the present invention, the mask plate used for the semiconductor self-aligned lithography process may also include a device area mask pattern, wherein the device area mask pattern is used to form a device functional structure on the surface of the semiconductor substrate, and the device area mask pattern is formed with a plurality of device area graphics, and the device area graphics can be formed as a long strip pattern, each long strip pattern can correspond to a functional structure, and the graphic width of the second mark pattern 22 and the spacing between adjacent second mark patterns 22 are the same as the graphic width of the device area mask pattern and the spacing between adjacent device area graphics. In this way, when the device area and the alignment mark are deposited, the graphic width and spacing of the second mark pattern 22 and the device area graphics are the same, which is conducive to the formation of the second mark pattern 22.

[0049] Furthermore, the second marking pattern 22 has the same extension direction as the device area graphic of the device area mask pattern. Specifically, the first marking pattern 21 is formed in a long strip shape, the second marking pattern 22 is formed in a long strip shape, and the device area graphic is formed in a long strip shape. The first marking pattern 21 and the second marking pattern 22 have the same extension direction and are the same as the extension direction of the device area graphic, which is facilitating the formation of the first marking pattern 21 and the second marking pattern 22.

[0050] In some embodiments of the present invention, the graphic density of the first alignment pattern 11 is greater than the graphic density of the second alignment pattern 12. Optionally, the graphic density of the first alignment pattern 11 is 1-5 times the graphic density of the second alignment pattern 12, thereby increasing the density of the pattern forming the metal layer to improve the signal and alignment effect of the alignment mask pattern 100, while making a clear contrast between the graphic densities of the first alignment pattern 11 and the second alignment pattern 12, and making the mark contrast between the first alignment pattern 11 and the second alignment pattern 12 stronger, and also reducing the influence of the symmetry of the alignment mask pattern 100 during the chemical mechanical polishing process to improve the alignment accuracy and effect.

[0051] In some specific examples of the present invention, the graphic width of the second mark pattern 22 is twice the sum of the graphic width of the first mark pattern 21 and the spacing between adjacent first mark patterns 21, and the spacing between adjacent second mark patterns 22 is the sum of the graphic width of the first mark pattern 21 and the spacing between adjacent first mark patterns 21. Specifically, the first mark pattern 21 and the second mark pattern 22 are both formed as long strip patterns, the graphic width of the first mark pattern 21 is a, and the spacing between adjacent first mark patterns 21 is b, then the width of the second mark pattern 22 is 2(a+b), and the graphic width of adjacent second mark patterns 22 is a+b, so that the alignment effect and alignment performance of the formed alignment mark are better.

[0052] The invention also provides a method for forming a semiconductor alignment mark.

[0053] like Figure 2-Figure 6 As shown, the method for forming a semiconductor alignment mark according to an embodiment of the present invention may include: forming a semiconductor substrate, an oxide layer 3 is formed on the surface of the semiconductor substrate; forming a mask layer 4 and a photoresist layer on the surface of the oxide layer 3 in sequence; using the mask plate for semiconductor self-aligned photolithography process of the above embodiment as a mask, exposing and developing the photoresist layer to form a photoresist pattern 44; forming a first film layer 5 on the surface of the photoresist pattern 44 and the mask layer 4; removing a portion of the first film layer 5 located on the top of the photoresist pattern 44, retaining the first film layer 5 located on the surface of the photoresist pattern 44 to form a first pattern 51; removing the photoresist pattern 44; etching the mask layer 4 using the first pattern 51 as a mask; and continuing to etch the oxide layer 3 downward until the semiconductor substrate is exposed to form a second pattern 61; forming a metal layer 62 on the surface of the semiconductor substrate, and the metal layer 62 fills the second pattern 61 to form an alignment mark 7.

[0054] According to the method for forming a semiconductor alignment mark in an embodiment of the present invention, by adopting the mask plate for semiconductor self-alignment lithography process of the above-mentioned embodiment, the formed alignment mark 7 can avoid forming a continuous large metal area, so as to improve the alignment signal of the alignment mark 7 and improve the overlay accuracy of the alignment mark 7.

[0055] The present invention also proposes a semiconductor structure, which includes a semiconductor substrate and an alignment mark 7 formed on the surface of the semiconductor substrate. The alignment mark 7 is prepared by the semiconductor alignment mark forming method described in the above embodiment, and the alignment mark 7 is formed in the cutting path area of ​​the semiconductor structure.

[0056] like Figure 7As shown, the alignment mark 7 may include a plurality of first alignment patterns 71 spaced apart along a first direction, a plurality of second alignment patterns 72 spaced apart along the first direction, and a metal layer 62 .

[0057] The first alignment pattern 71 is formed into a long strip, and each of the first alignment patterns 71 includes a plurality of first patterns 73, and the first patterns 73 are formed into a hollow rectangle extending along the second direction; the second alignment pattern 72 is formed into a long strip, and each of the second alignment patterns 72 includes a plurality of second patterns 74, and the second patterns 74 are formed into a hollow rectangle extending along the second direction, and the plurality of first alignment patterns 71 and the plurality of second alignment patterns 72 are alternately distributed at intervals; the metal layer 62 is formed on the surface of the semiconductor substrate and fills the first alignment pattern 71 and the second alignment pattern 72.

[0058] According to the semiconductor structure of the embodiment of the present invention, the metal layer 62 occupies a smaller area and does not form a continuous large area, thereby reducing metal reflection, improving alignment signals, and further improving the alignment and overlay accuracy of the semiconductor structure.

[0059] In some embodiments of the present invention, the pattern density of the first pattern 73 is greater than the pattern density of the second pattern 74. The pattern width of the first pattern 73 is smaller than the pattern width of the second pattern 74, so that the first alignment pattern 71 and the second alignment pattern 72 can have a contrast to further improve the alignment signal strength.

[0060] The above are only preferred embodiments of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A mask for semiconductor self-aligned lithography process, It is characterized in that The invention comprises at least one alignment mask pattern, wherein the alignment mask pattern comprises a plurality of first alignment patterns and a plurality of second alignment patterns, wherein the plurality of first alignment patterns and the plurality of second alignment patterns are alternately distributed along a first direction, wherein each of the first alignment patterns has a plurality of first mark patterns arranged periodically, and the second alignment pattern has a plurality of second mark patterns, wherein the graphic density of the first alignment pattern is different from the graphic density of the second alignment pattern, and the mask plate further comprises a device area mask pattern, wherein the graphic width of the second mark pattern and the spacing between adjacent second mark patterns are the same as the graphic width of the device area mask pattern and the spacing between adjacent device area mask patterns.

2. The mask for semiconductor self-aligned lithography process according to claim 1, It is characterized in that The first alignment pattern and the second alignment pattern are both formed into a strip shape extending perpendicular to the first direction, and the first marking pattern and the second marking pattern are both formed into a strip shape extending along a second direction intersecting the first direction.

3. The mask for semiconductor self-aligned lithography process according to claim 1, It is characterized in that The second marking pattern and the device region mask pattern have the same graphic extension direction.

4. The mask for semiconductor self-aligned lithography process according to claim 1, It is characterized in that A pattern density of the first alignment pattern is greater than a pattern density of the second alignment pattern.

5. The mask for semiconductor self-aligned lithography process according to claim 4, It is characterized in that The graphic width of the second marking pattern is twice the sum of the graphic width of the first marking pattern and the spacing between adjacent first marking patterns, and the spacing between adjacent second marking patterns is the sum of the graphic width of the first marking pattern and the spacing between adjacent first marking patterns.

6. The mask for semiconductor self-aligned lithography process according to claim 1, It is characterized in that The second marking patterns are arranged evenly spaced apart along an extending direction of the second alignment pattern.

7. The mask for semiconductor self-aligned lithography process according to claim 1, It is characterized in that The alignment mask patterns are a pair, and the pair of alignment mask patterns are formed into axisymmetric patterns.

8. A method for forming a semiconductor alignment mark, It is characterized in that include: forming a semiconductor substrate, wherein an oxide layer is formed on the surface of the semiconductor substrate; forming a mask layer and a photoresist layer in sequence on the surface of the oxide layer; Using the mask for semiconductor self-aligned photolithography process according to any one of claims 1 to 7 as a mask, the photoresist layer is exposed and developed to form a photoresist pattern; forming a first film layer on the surfaces of the photoresist pattern and the mask layer; removing a portion of the first film layer located on the top of the photoresist pattern, and retaining the first film layer located on the surface of the photoresist pattern to form a first pattern; removing the photoresist pattern; etching the mask layer using the first pattern as a mask; and continuing to etch the oxide layer downward until the semiconductor substrate is exposed to form a second pattern; A metal layer is formed on the surface of the semiconductor substrate, and the metal layer is filled with the second pattern to form an alignment mark.

9. A semiconductor structure, It is characterized in that The semiconductor structure comprises a semiconductor substrate and an alignment mark formed on a surface of the semiconductor substrate, wherein the alignment mark is prepared by the method for forming a semiconductor alignment mark according to claim 8, and the alignment mark comprises: A plurality of first alignment patterns spaced apart along a first direction, the first alignment patterns being formed into a strip shape, each of the first alignment patterns comprising a plurality of first patterns, the first patterns being formed into a hollow rectangle extending along a second direction; A plurality of second alignment patterns spaced apart along a first direction, the second alignment patterns being formed into a strip shape, each of the second alignment patterns comprising a plurality of second patterns, the second patterns being formed into a hollow rectangular frame extending along a second direction, and the plurality of first alignment patterns and the plurality of second alignment patterns being alternately spaced apart; A metal layer is formed on a surface of the semiconductor substrate and fills the first alignment pattern and the second alignment pattern.

10. The semiconductor structure according to claim 9, It is characterized in that A pattern density of the first pattern is greater than a pattern density of the second pattern.

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